Tom Rini
6 years ago
commit
0cba6e906a
@ -0,0 +1,150 @@ |
||||
// SPDX-License-Identifier: (GPL-2.0+ or MIT) |
||||
/* |
||||
* Copyright (C) 2018 Amarula Solutions |
||||
* Author: Jagan Teki <jagan@amarulasolutions.com> |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "sun50i-h6.dtsi" |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
|
||||
/ { |
||||
model = "OrangePi One Plus"; |
||||
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc0_pins>; |
||||
vmmc-supply = <®_cldo1>; |
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; |
||||
bus-width = <4>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&r_i2c { |
||||
status = "okay"; |
||||
|
||||
axp805: pmic@36 { |
||||
compatible = "x-powers,axp805", "x-powers,axp806"; |
||||
reg = <0x36>; |
||||
interrupt-parent = <&r_intc>; |
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <1>; |
||||
x-powers,self-working-mode; |
||||
|
||||
regulators { |
||||
reg_aldo1: aldo1 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-pl"; |
||||
}; |
||||
|
||||
reg_aldo2: aldo2 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-ac200"; |
||||
}; |
||||
|
||||
reg_aldo3: aldo3 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc25-dram"; |
||||
}; |
||||
|
||||
reg_bldo1: bldo1 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-bias-pll"; |
||||
}; |
||||
|
||||
reg_bldo2: bldo2 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-efuse-pcie-hdmi-io"; |
||||
}; |
||||
|
||||
reg_bldo3: bldo3 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-dcxoio"; |
||||
}; |
||||
|
||||
bldo4 { |
||||
/* unused */ |
||||
}; |
||||
|
||||
reg_cldo1: cldo1 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-3v3"; |
||||
}; |
||||
|
||||
reg_cldo2: cldo2 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-wifi-1"; |
||||
}; |
||||
|
||||
reg_cldo3: cldo3 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-wifi-2"; |
||||
}; |
||||
|
||||
reg_dcdca: dcdca { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <810000>; |
||||
regulator-max-microvolt = <1080000>; |
||||
regulator-name = "vdd-cpu"; |
||||
}; |
||||
|
||||
reg_dcdcc: dcdcc { |
||||
regulator-min-microvolt = <810000>; |
||||
regulator-max-microvolt = <1080000>; |
||||
regulator-name = "vdd-gpu"; |
||||
}; |
||||
|
||||
reg_dcdcd: dcdcd { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <960000>; |
||||
regulator-max-microvolt = <960000>; |
||||
regulator-name = "vdd-sys"; |
||||
}; |
||||
|
||||
reg_dcdce: dcdce { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-name = "vcc-dram"; |
||||
}; |
||||
|
||||
sw { |
||||
/* unused */ |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_ph_pins>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,185 @@ |
||||
// SPDX-License-Identifier: (GPL-2.0+ or MIT) |
||||
/* |
||||
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include "sun50i-h6.dtsi" |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
|
||||
/ { |
||||
model = "Pine H64"; |
||||
compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
leds { |
||||
compatible = "gpio-leds"; |
||||
|
||||
heartbeat { |
||||
label = "pine-h64:green:heartbeat"; |
||||
gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ |
||||
}; |
||||
|
||||
link { |
||||
label = "pine-h64:white:link"; |
||||
gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ |
||||
}; |
||||
|
||||
status { |
||||
label = "pine-h64:blue:status"; |
||||
gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc0_pins>; |
||||
vmmc-supply = <®_cldo1>; |
||||
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&mmc2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&mmc2_pins>; |
||||
vmmc-supply = <®_cldo1>; |
||||
vqmmc-supply = <®_bldo2>; |
||||
non-removable; |
||||
cap-mmc-hw-reset; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&r_i2c { |
||||
status = "okay"; |
||||
|
||||
axp805: pmic@36 { |
||||
compatible = "x-powers,axp805", "x-powers,axp806"; |
||||
reg = <0x36>; |
||||
interrupt-parent = <&r_intc>; |
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <1>; |
||||
x-powers,self-working-mode; |
||||
|
||||
regulators { |
||||
reg_aldo1: aldo1 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-pl"; |
||||
}; |
||||
|
||||
reg_aldo2: aldo2 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-ac200"; |
||||
}; |
||||
|
||||
reg_aldo3: aldo3 { |
||||
/* This regulator is connected with CLDO1 */ |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-3v3-1"; |
||||
}; |
||||
|
||||
reg_bldo1: bldo1 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-bias-pll"; |
||||
}; |
||||
|
||||
reg_bldo2: bldo2 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-efuse-pcie-hdmi-io"; |
||||
}; |
||||
|
||||
reg_bldo3: bldo3 { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-name = "vcc-dcxoio"; |
||||
}; |
||||
|
||||
bldo4 { |
||||
/* unused */ |
||||
}; |
||||
|
||||
reg_cldo1: cldo1 { |
||||
/* This regulator is connected with ALDO3 */ |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-3v3-2"; |
||||
}; |
||||
|
||||
reg_cldo2: cldo2 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-wifi-1"; |
||||
}; |
||||
|
||||
reg_cldo3: cldo3 { |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-name = "vcc-wifi-2"; |
||||
}; |
||||
|
||||
reg_dcdca: dcdca { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <810000>; |
||||
regulator-max-microvolt = <1080000>; |
||||
regulator-name = "vdd-cpu"; |
||||
}; |
||||
|
||||
reg_dcdcc: dcdcc { |
||||
regulator-min-microvolt = <810000>; |
||||
regulator-max-microvolt = <1080000>; |
||||
regulator-name = "vdd-gpu"; |
||||
}; |
||||
|
||||
reg_dcdcd: dcdcd { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <960000>; |
||||
regulator-max-microvolt = <960000>; |
||||
regulator-name = "vdd-sys"; |
||||
}; |
||||
|
||||
reg_dcdce: dcdce { |
||||
regulator-always-on; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-name = "vcc-dram"; |
||||
}; |
||||
|
||||
sw { |
||||
/* unused */ |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
pcf8563: rtc@51 { |
||||
compatible = "nxp,pcf8563"; |
||||
reg = <0x51>; |
||||
#clock-cells = <0>; |
||||
}; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_ph_pins>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,288 @@ |
||||
// SPDX-License-Identifier: (GPL-2.0+ or MIT) |
||||
/* |
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
*/ |
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
||||
#include <dt-bindings/clock/sun50i-h6-ccu.h> |
||||
#include <dt-bindings/clock/sun50i-h6-r-ccu.h> |
||||
#include <dt-bindings/reset/sun50i-h6-ccu.h> |
||||
#include <dt-bindings/reset/sun50i-h6-r-ccu.h> |
||||
|
||||
/ { |
||||
interrupt-parent = <&gic>; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
cpu0: cpu@0 { |
||||
compatible = "arm,cortex-a53", "arm,armv8"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
enable-method = "psci"; |
||||
}; |
||||
|
||||
cpu1: cpu@1 { |
||||
compatible = "arm,cortex-a53", "arm,armv8"; |
||||
device_type = "cpu"; |
||||
reg = <1>; |
||||
enable-method = "psci"; |
||||
}; |
||||
|
||||
cpu2: cpu@2 { |
||||
compatible = "arm,cortex-a53", "arm,armv8"; |
||||
device_type = "cpu"; |
||||
reg = <2>; |
||||
enable-method = "psci"; |
||||
}; |
||||
|
||||
cpu3: cpu@3 { |
||||
compatible = "arm,cortex-a53", "arm,armv8"; |
||||
device_type = "cpu"; |
||||
reg = <3>; |
||||
enable-method = "psci"; |
||||
}; |
||||
}; |
||||
|
||||
iosc: internal-osc-clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <16000000>; |
||||
clock-accuracy = <300000000>; |
||||
clock-output-names = "iosc"; |
||||
}; |
||||
|
||||
osc24M: osc24M_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <24000000>; |
||||
clock-output-names = "osc24M"; |
||||
}; |
||||
|
||||
osc32k: osc32k_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32768>; |
||||
clock-output-names = "osc32k"; |
||||
}; |
||||
|
||||
psci { |
||||
compatible = "arm,psci-0.2"; |
||||
method = "smc"; |
||||
}; |
||||
|
||||
timer { |
||||
compatible = "arm,armv8-timer"; |
||||
interrupts = <GIC_PPI 13 |
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
||||
<GIC_PPI 14 |
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
||||
<GIC_PPI 11 |
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, |
||||
<GIC_PPI 10 |
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
}; |
||||
|
||||
soc { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
ccu: clock@3001000 { |
||||
compatible = "allwinner,sun50i-h6-ccu"; |
||||
reg = <0x03001000 0x1000>; |
||||
clocks = <&osc24M>, <&osc32k>, <&iosc>; |
||||
clock-names = "hosc", "losc", "iosc"; |
||||
#clock-cells = <1>; |
||||
#reset-cells = <1>; |
||||
}; |
||||
|
||||
gic: interrupt-controller@3021000 { |
||||
compatible = "arm,gic-400"; |
||||
reg = <0x03021000 0x1000>, |
||||
<0x03022000 0x2000>, |
||||
<0x03024000 0x2000>, |
||||
<0x03026000 0x2000>; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
}; |
||||
|
||||
pio: pinctrl@300b000 { |
||||
compatible = "allwinner,sun50i-h6-pinctrl"; |
||||
reg = <0x0300b000 0x400>; |
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; |
||||
clock-names = "apb", "hosc", "losc"; |
||||
gpio-controller; |
||||
#gpio-cells = <3>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
|
||||
mmc0_pins: mmc0-pins { |
||||
pins = "PF0", "PF1", "PF2", "PF3", |
||||
"PF4", "PF5"; |
||||
function = "mmc0"; |
||||
drive-strength = <30>; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
mmc2_pins: mmc2-pins { |
||||
pins = "PC1", "PC4", "PC5", "PC6", |
||||
"PC7", "PC8", "PC9", "PC10", |
||||
"PC11", "PC12", "PC13", "PC14"; |
||||
function = "mmc2"; |
||||
drive-strength = <30>; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
uart0_ph_pins: uart0-ph { |
||||
pins = "PH0", "PH1"; |
||||
function = "uart0"; |
||||
}; |
||||
}; |
||||
|
||||
mmc0: mmc@4020000 { |
||||
compatible = "allwinner,sun50i-h6-mmc", |
||||
"allwinner,sun50i-a64-mmc"; |
||||
reg = <0x04020000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; |
||||
clock-names = "ahb", "mmc"; |
||||
resets = <&ccu RST_BUS_MMC0>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc1: mmc@4021000 { |
||||
compatible = "allwinner,sun50i-h6-mmc", |
||||
"allwinner,sun50i-a64-mmc"; |
||||
reg = <0x04021000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; |
||||
clock-names = "ahb", "mmc"; |
||||
resets = <&ccu RST_BUS_MMC1>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc2: mmc@4022000 { |
||||
compatible = "allwinner,sun50i-h6-emmc", |
||||
"allwinner,sun50i-a64-emmc"; |
||||
reg = <0x04022000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; |
||||
clock-names = "ahb", "mmc"; |
||||
resets = <&ccu RST_BUS_MMC2>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
uart0: serial@5000000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x05000000 0x400>; |
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART0>; |
||||
resets = <&ccu RST_BUS_UART0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@5000400 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x05000400 0x400>; |
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART1>; |
||||
resets = <&ccu RST_BUS_UART1>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@5000800 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x05000800 0x400>; |
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART2>; |
||||
resets = <&ccu RST_BUS_UART2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart3: serial@5000c00 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x05000c00 0x400>; |
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART3>; |
||||
resets = <&ccu RST_BUS_UART3>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
r_ccu: clock@7010000 { |
||||
compatible = "allwinner,sun50i-h6-r-ccu"; |
||||
reg = <0x07010000 0x400>; |
||||
clocks = <&osc24M>, <&osc32k>, <&iosc>, |
||||
<&ccu CLK_PLL_PERIPH0>; |
||||
clock-names = "hosc", "losc", "iosc", "pll-periph"; |
||||
#clock-cells = <1>; |
||||
#reset-cells = <1>; |
||||
}; |
||||
|
||||
r_intc: interrupt-controller@7021000 { |
||||
compatible = "allwinner,sun50i-h6-r-intc", |
||||
"allwinner,sun6i-a31-r-intc"; |
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
reg = <0x07021000 0x400>; |
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
r_pio: pinctrl@7022000 { |
||||
compatible = "allwinner,sun50i-h6-r-pinctrl"; |
||||
reg = <0x07022000 0x400>; |
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; |
||||
clock-names = "apb", "hosc", "losc"; |
||||
gpio-controller; |
||||
#gpio-cells = <3>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
|
||||
r_i2c_pins: r-i2c { |
||||
pins = "PL0", "PL1"; |
||||
function = "s_i2c"; |
||||
}; |
||||
}; |
||||
|
||||
r_i2c: i2c@7081400 { |
||||
compatible = "allwinner,sun6i-a31-i2c"; |
||||
reg = <0x07081400 0x400>; |
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&r_ccu CLK_R_APB2_I2C>; |
||||
resets = <&r_ccu RST_R_APB2_I2C>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&r_i2c_pins>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,320 @@ |
||||
/*
|
||||
* Allwinner H6 clock register definitions |
||||
* |
||||
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SUNXI_CLOCK_SUN50I_H6_H |
||||
#define _SUNXI_CLOCK_SUN50I_H6_H |
||||
|
||||
struct sunxi_ccm_reg { |
||||
u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ |
||||
u8 reserved_0x004[12]; |
||||
u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ |
||||
u8 reserved_0x014[12]; |
||||
u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ |
||||
u8 reserved_0x020[4]; |
||||
u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ |
||||
u8 reserved_0x028[4]; |
||||
u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ |
||||
u8 reserved_0x034[12]; |
||||
u32 pll3_cfg; /* 0x040 pll3 (video0) control */ |
||||
u8 reserved_0x044[4]; |
||||
u32 pll_video1_cfg; /* 0x048 pll video1 control */ |
||||
u8 reserved_0x04c[12]; |
||||
u32 pll4_cfg; /* 0x058 pll4 (ve) control */ |
||||
u8 reserved_0x05c[4]; |
||||
u32 pll10_cfg; /* 0x060 pll10 (de) control */ |
||||
u8 reserved_0x064[12]; |
||||
u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ |
||||
u8 reserved_0x074[4]; |
||||
u32 pll2_cfg; /* 0x078 pll2 (audio) control */ |
||||
u8 reserved_0x07c[148]; |
||||
u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ |
||||
u8 reserved_0x114[20]; |
||||
u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ |
||||
u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ |
||||
u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ |
||||
u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ |
||||
u8 reserved_0x138[8]; |
||||
u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ |
||||
u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ |
||||
u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ |
||||
u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ |
||||
u8 reserved_0x150[8]; |
||||
u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ |
||||
u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ |
||||
u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ |
||||
u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ |
||||
u8 reserved_0x168[8]; |
||||
u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ |
||||
u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ |
||||
u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ |
||||
u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ |
||||
u8 reserved_0x180[384]; |
||||
u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ |
||||
u8 reserved_0x304[12]; |
||||
u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ |
||||
u8 reserved_0x314[12]; |
||||
u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ |
||||
u8 reserved_0x324[4]; |
||||
u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ |
||||
u8 reserved_0x32c[4]; |
||||
u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ |
||||
u8 reserved_0x334[12]; |
||||
u32 pll3_bias; /* 0x340 pll3 (video0) bias */ |
||||
u8 reserved_0x344[4]; |
||||
u32 pll_video1_bias; /* 0x348 pll video1 bias */ |
||||
u8 reserved_0x34c[12]; |
||||
u32 pll4_bias; /* 0x358 pll4 (ve) bias */ |
||||
u8 reserved_0x35c[4]; |
||||
u32 pll10_bias; /* 0x360 pll10 (de) bias */ |
||||
u8 reserved_0x364[12]; |
||||
u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ |
||||
u8 reserved_0x374[4]; |
||||
u32 pll2_bias; /* 0x378 pll2 (audio) bias */ |
||||
u8 reserved_0x37c[132]; |
||||
u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ |
||||
u8 reserved_0x404[252]; |
||||
u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ |
||||
u8 reserved_0x504[12]; |
||||
u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ |
||||
u8 reserved_0x514[8]; |
||||
u32 ahb3_cfg; /* 0x51c AHB3 clock control */ |
||||
u32 apb1_cfg; /* 0x520 APB1 clock control */ |
||||
u32 apb2_cfg; /* 0x524 APB2 clock control */ |
||||
u8 reserved_0x528[24]; |
||||
u32 mbus_cfg; /* 0x540 MBUS clock control */ |
||||
u8 reserved_0x544[188]; |
||||
u32 de_clk_cfg; /* 0x600 DE clock control */ |
||||
u8 reserved_0x604[8]; |
||||
u32 de_gate_reset; /* 0x60c DE gate/reset control */ |
||||
u8 reserved_0x610[16]; |
||||
u32 di_clk_cfg; /* 0x620 DI clock control */ |
||||
u8 reserved_0x024[8]; |
||||
u32 di_gate_reset; /* 0x62c DI gate/reset control */ |
||||
u8 reserved_0x630[64]; |
||||
u32 gpu_clk_cfg; /* 0x670 GPU clock control */ |
||||
u8 reserved_0x674[8]; |
||||
u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ |
||||
u32 ce_clk_cfg; /* 0x680 CE clock control */ |
||||
u8 reserved_0x684[8]; |
||||
u32 ce_gate_reset; /* 0x68c CE gate/reset control */ |
||||
u32 ve_clk_cfg; /* 0x690 VE clock control */ |
||||
u8 reserved_0x694[8]; |
||||
u32 ve_gate_reset; /* 0x69c VE gate/reset control */ |
||||
u8 reserved_0x6a0[16]; |
||||
u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ |
||||
u8 reserved_0x6b4[8]; |
||||
u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ |
||||
u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ |
||||
u8 reserved_0x6c4[8]; |
||||
u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ |
||||
u8 reserved_0x6d0[60]; |
||||
u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ |
||||
u8 reserved_0x710[12]; |
||||
u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ |
||||
u8 reserved_0x720[12]; |
||||
u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ |
||||
u8 reserved_0x730[12]; |
||||
u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ |
||||
u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ |
||||
u8 reserved_0x744[72]; |
||||
u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ |
||||
u8 reserved_0x790[12]; |
||||
u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ |
||||
u8 reserved_0x7a0[12]; |
||||
u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ |
||||
u8 reserved_0x7b0[12]; |
||||
u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ |
||||
u8 reserved_0x7c0[64]; |
||||
u32 dram_clk_cfg; /* 0x800 DRAM clock control */ |
||||
u32 mbus_gate; /* 0x804 MBUS gate control */ |
||||
u8 reserved_0x808[4]; |
||||
u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ |
||||
u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ |
||||
u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ |
||||
u8 reserved_0x818[20]; |
||||
u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ |
||||
u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ |
||||
u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ |
||||
u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ |
||||
u8 reserved_0x83c[16]; |
||||
u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ |
||||
u8 reserved_0x850[188]; |
||||
u32 uart_gate_reset; /* 0x90c UART gate/reset control */ |
||||
u8 reserved_0x910[12]; |
||||
u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ |
||||
u8 reserved_0x920[28]; |
||||
u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ |
||||
u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ |
||||
u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ |
||||
u8 reserved_0x948[36]; |
||||
u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ |
||||
u8 reserved_0x970[12]; |
||||
u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ |
||||
u8 reserved_0x980[48]; |
||||
u32 ts_clk_cfg; /* 0x9b0 TS clock control */ |
||||
u8 reserved_0x9b4[8]; |
||||
u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ |
||||
u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ |
||||
u8 reserved_0x9c4[8]; |
||||
u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ |
||||
u8 reserved_0x9d0[44]; |
||||
u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ |
||||
u8 reserved_0xa00[12]; |
||||
u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ |
||||
u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ |
||||
u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ |
||||
u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ |
||||
u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ |
||||
u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ |
||||
u8 reserved_0xa24[8]; |
||||
u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ |
||||
u8 reserved_0xa30[16]; |
||||
u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ |
||||
u8 reserved_0xa44[8]; |
||||
u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ |
||||
u8 reserved_0xa50[16]; |
||||
u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ |
||||
u8 reserved_0xa64[8]; |
||||
u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ |
||||
u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ |
||||
u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ |
||||
u8 reserved_0xa78[4]; |
||||
u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ |
||||
u8 reserved_0xa80[12]; |
||||
u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ |
||||
u8 reserved_0xa90[32]; |
||||
u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ |
||||
u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ |
||||
u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ |
||||
u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ |
||||
u8 reserved_0xac0[64]; |
||||
u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ |
||||
u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ |
||||
u8 reserved_0xb08[8]; |
||||
u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ |
||||
u8 reserved_0xb14[8]; |
||||
u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ |
||||
u8 reserved_0xb20[60]; |
||||
u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ |
||||
u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ |
||||
u8 reserved_0xb64[24]; |
||||
u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ |
||||
u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ |
||||
u8 reserved_0xb84[24]; |
||||
u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ |
||||
u8 reserved_0xba0[96]; |
||||
u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ |
||||
u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ |
||||
u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ |
||||
u8 reserved_0xc0c[32]; |
||||
u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ |
||||
u8 reserved_0xc30[16]; |
||||
u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ |
||||
u8 reserved_0xc44[8]; |
||||
u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ |
||||
u8 reserved_0xc50[688]; |
||||
u32 ccu_sec_switch; /* 0xf00 CCU security switch */ |
||||
u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ |
||||
}; |
||||
|
||||
/* pll1 bit field */ |
||||
#define CCM_PLL1_CTRL_EN BIT(31) |
||||
#define CCM_PLL1_LOCK_EN BIT(29) |
||||
#define CCM_PLL1_LOCK BIT(28) |
||||
#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) |
||||
#define CCM_PLL1_CTRL_P(p) ((p) << 16) |
||||
#define CCM_PLL1_CTRL_N(n) ((n) << 8) |
||||
|
||||
/* pll5 bit field */ |
||||
#define CCM_PLL5_CTRL_EN BIT(31) |
||||
#define CCM_PLL5_LOCK_EN BIT(29) |
||||
#define CCM_PLL5_LOCK BIT(28) |
||||
#define CCM_PLL5_CTRL_N(n) ((n) << 8) |
||||
#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) |
||||
#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) |
||||
|
||||
/* pll6 bit field */ |
||||
#define CCM_PLL6_CTRL_EN BIT(31) |
||||
#define CCM_PLL6_LOCK_EN BIT(29) |
||||
#define CCM_PLL6_LOCK BIT(28) |
||||
#define CCM_PLL6_CTRL_N_SHIFT 8 |
||||
#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) |
||||
#define CCM_PLL6_CTRL_DIV1_SHIFT 0 |
||||
#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) |
||||
#define CCM_PLL6_CTRL_DIV2_SHIFT 1 |
||||
#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) |
||||
#define CCM_PLL6_DEFAULT 0xa0006300 |
||||
|
||||
/* cpu_axi bit field*/ |
||||
#define CCM_CPU_AXI_MUX_MASK (0x3 << 24) |
||||
#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) |
||||
#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) |
||||
#define CCM_CPU_AXI_APB_MASK 0x300 |
||||
#define CCM_CPU_AXI_AXI_MASK 0x3 |
||||
#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 |
||||
|
||||
/* psi_ahb1_ahb2 bit field */ |
||||
#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 |
||||
|
||||
/* ahb3 bit field */ |
||||
#define CCM_AHB3_DEFAULT 0x03000002 |
||||
|
||||
/* apb1 bit field */ |
||||
#define CCM_APB1_DEFAULT 0x03000102 |
||||
|
||||
/* apb2 bit field */ |
||||
#define APB2_CLK_SRC_OSC24M (0x0 << 24) |
||||
#define APB2_CLK_SRC_OSC32K (0x1 << 24) |
||||
#define APB2_CLK_SRC_PSI (0x2 << 24) |
||||
#define APB2_CLK_SRC_PLL6 (0x3 << 24) |
||||
#define APB2_CLK_SRC_MASK (0x3 << 24) |
||||
#define APB2_CLK_RATE_N_1 (0x0 << 8) |
||||
#define APB2_CLK_RATE_N_2 (0x1 << 8) |
||||
#define APB2_CLK_RATE_N_4 (0x2 << 8) |
||||
#define APB2_CLK_RATE_N_8 (0x3 << 8) |
||||
#define APB2_CLK_RATE_N_MASK (3 << 8) |
||||
#define APB2_CLK_RATE_M(m) (((m)-1) << 0) |
||||
#define APB2_CLK_RATE_M_MASK (3 << 0) |
||||
|
||||
/* MBUS clock bit field */ |
||||
#define MBUS_ENABLE BIT(31) |
||||
#define MBUS_RESET BIT(30) |
||||
#define MBUS_CLK_SRC_MASK GENMASK(25, 24) |
||||
#define MBUS_CLK_SRC_OSCM24 (0 << 24) |
||||
#define MBUS_CLK_SRC_PLL6X2 (1 << 24) |
||||
#define MBUS_CLK_SRC_PLL5 (2 << 24) |
||||
#define MBUS_CLK_SRC_PLL6X4 (3 << 24) |
||||
#define MBUS_CLK_M(m) (((m)-1) << 0) |
||||
|
||||
/* Module gate/reset shift*/ |
||||
#define RESET_SHIFT (16) |
||||
|
||||
/* DRAM clock bit field */ |
||||
#define DRAM_MOD_RESET BIT(30) |
||||
#define DRAM_CLK_UPDATE BIT(27) |
||||
#define DRAM_CLK_SRC_MASK GENMASK(25, 24) |
||||
#define DRAM_CLK_SRC_PLL5 (0 << 24) |
||||
#define DRAM_CLK_M(m) (((m)-1) << 0) |
||||
|
||||
/* MMC clock bit field */ |
||||
#define CCM_MMC_CTRL_M(x) ((x) - 1) |
||||
#define CCM_MMC_CTRL_N(x) ((x) << 8) |
||||
#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) |
||||
#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) |
||||
#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) |
||||
#define CCM_MMC_CTRL_ENABLE (0x1 << 31) |
||||
/* H6 doesn't have these delays */ |
||||
#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) |
||||
#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
void clock_set_pll1(unsigned int hz); |
||||
unsigned int clock_get_pll6(void); |
||||
#endif |
||||
|
||||
#endif /* _SUNXI_CLOCK_SUN50I_H6_H */ |
||||
@ -0,0 +1,73 @@ |
||||
/*
|
||||
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SUNXI_CPU_SUN50I_H6_H |
||||
#define _SUNXI_CPU_SUN50I_H6_H |
||||
|
||||
#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS |
||||
#define SUNXI_SRAM_C_BASE 0x00028000 |
||||
#define SUNXI_SRAM_A2_BASE 0x00100000 |
||||
|
||||
#define SUNXI_DE3_BASE 0x01000000 |
||||
#define SUNXI_SS_BASE 0x01904000 |
||||
#define SUNXI_EMCE_BASE 0x01905000 |
||||
|
||||
#define SUNXI_SRAMC_BASE 0x03000000 |
||||
#define SUNXI_CCM_BASE 0x03001000 |
||||
#define SUNXI_DMA_BASE 0x03002000 |
||||
/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ |
||||
#define SUNXI_SIDC_BASE 0x03006000 |
||||
#define SNUXI_SID_BASE 0x03006200 |
||||
#define SUNXI_TIMER_BASE 0x03009000 |
||||
#define SUNXI_PIO_BASE 0x0300B000 |
||||
#define SUNXI_PSI_BASE 0x0300C000 |
||||
|
||||
#define SUNXI_GIC400_BASE 0x03020000 |
||||
#define SUNXI_IOMMU_BASE 0x030F0000 |
||||
|
||||
#define SUNXI_DRAM_COM_BASE 0x04002000 |
||||
#define SUNXI_DRAM_CTL0_BASE 0x04003000 |
||||
#define SUNXI_DRAM_PHY0_BASE 0x04005000 |
||||
#define SUNXI_NFC_BASE 0x04011000 |
||||
#define SUNXI_MMC0_BASE 0x04020000 |
||||
#define SUNXI_MMC1_BASE 0x04021000 |
||||
#define SUNXI_MMC2_BASE 0x04022000 |
||||
|
||||
#define SUNXI_UART0_BASE 0x05000000 |
||||
#define SUNXI_UART1_BASE 0x05000400 |
||||
#define SUNXI_UART2_BASE 0x05000800 |
||||
#define SUNXI_UART3_BASE 0x05000C00 |
||||
#define SUNXI_TWI0_BASE 0x05002000 |
||||
#define SUNXI_TWI1_BASE 0x05002400 |
||||
#define SUNXI_TWI2_BASE 0x05002800 |
||||
#define SUNXI_TWI3_BASE 0x05002C00 |
||||
#define SUNXI_SPI0_BASE 0x05010000 |
||||
#define SUNXI_SPI1_BASE 0x05011000 |
||||
#define SUNXI_GMAC_BASE 0x05020000 |
||||
#define SUNXI_USB0_BASE 0x05100000 |
||||
#define SUNXI_XHCI_BASE 0x05200000 |
||||
#define SUNXI_USB3_BASE 0x05311000 |
||||
#define SUNXI_PCIE_BASE 0x05400000 |
||||
|
||||
#define SUNXI_HDMI_BASE 0x06000000 |
||||
#define SUNXI_TCON_TOP_BASE 0x06510000 |
||||
#define SUNXI_TCON_LCD0_BASE 0x06511000 |
||||
#define SUNXI_TCON_TV0_BASE 0x06515000 |
||||
|
||||
#define SUNXI_RTC_BASE 0x07000000 |
||||
#define SUNXI_R_CPUCFG_BASE 0x07000400 |
||||
#define SUNXI_PRCM_BASE 0x07010000 |
||||
#define SUNXI_R_PIO_BASE 0x07022000 |
||||
#define SUNXI_R_UART_BASE 0x07080000 |
||||
#define SUNXI_R_TWI_BASE 0x07081400 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
void sunxi_board_init(void); |
||||
void sunxi_reset(void); |
||||
int sunxi_get_sid(unsigned int *sid); |
||||
#endif |
||||
|
||||
#endif /* _SUNXI_CPU_SUN9I_H */ |
||||
@ -0,0 +1,297 @@ |
||||
/*
|
||||
* H6 dram controller register and constant defines |
||||
* |
||||
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SUNXI_DRAM_SUN50I_H6_H |
||||
#define _SUNXI_DRAM_SUN50I_H6_H |
||||
|
||||
enum sunxi_dram_type { |
||||
SUNXI_DRAM_TYPE_DDR3 = 3, |
||||
SUNXI_DRAM_TYPE_DDR4, |
||||
SUNXI_DRAM_TYPE_LPDDR2 = 6, |
||||
SUNXI_DRAM_TYPE_LPDDR3, |
||||
}; |
||||
|
||||
/*
|
||||
* The following information is mainly retrieved by disassembly and some FPGA |
||||
* test code of sun50iw3 platform. |
||||
*/ |
||||
struct sunxi_mctl_com_reg { |
||||
u32 cr; /* 0x000 control register */ |
||||
u8 reserved_0x004[4]; /* 0x004 */ |
||||
u32 unk_0x008; /* 0x008 */ |
||||
u32 tmr; /* 0x00c timer register */ |
||||
u8 reserved_0x010[4]; /* 0x010 */ |
||||
u32 unk_0x014; /* 0x014 */ |
||||
u8 reserved_0x018[8]; /* 0x018 */ |
||||
u32 maer0; /* 0x020 master enable register 0 */ |
||||
u32 maer1; /* 0x024 master enable register 1 */ |
||||
u32 maer2; /* 0x028 master enable register 2 */ |
||||
u8 reserved_0x02c[468]; /* 0x02c */ |
||||
u32 bwcr; /* 0x200 bandwidth control register */ |
||||
u8 reserved_0x204[12]; /* 0x204 */ |
||||
/*
|
||||
* The last master configured by BSP libdram is at 0x49x, so the |
||||
* size of this struct array is set to 41 (0x29) now. |
||||
*/ |
||||
struct { |
||||
u32 cfg0; /* 0x0 */ |
||||
u32 cfg1; /* 0x4 */ |
||||
u8 reserved_0x8[8]; /* 0x8 */ |
||||
} master[41]; /* 0x210 + index * 0x10 */ |
||||
}; |
||||
check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498); |
||||
|
||||
/*
|
||||
* The following register information are retrieved from some similar DRAM |
||||
* controllers, including the DRAM controllers in Allwinner A23/A80 SoCs, |
||||
* Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs. |
||||
* |
||||
* The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems |
||||
* to be older than the one in Allwinner H6, as the DRAMTMG9 register |
||||
* is missing in these SoCs. (From the product specifications of these |
||||
* SoCs they're not capable of DDR4) |
||||
* |
||||
* Information sources: |
||||
* - dram_sun9i.h and dram_sun8i_a23.h in the same directory. |
||||
* - sdram_rk3328.h from the RK3328 TPL DRAM patchset |
||||
* - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM) |
||||
* - Zynq UltraScale+ MPSoC Register Reference (UG1087) |
||||
*/ |
||||
struct sunxi_mctl_ctl_reg { |
||||
u32 mstr; /* 0x000 */ |
||||
u32 statr; /* 0x004 unused */ |
||||
u32 mstr1; /* 0x008 unused */ |
||||
u32 unk_0x00c; /* 0x00c */ |
||||
u32 mrctrl0; /* 0x010 unused */ |
||||
u32 mrctrl1; /* 0x014 unused */ |
||||
u32 mrstatr; /* 0x018 unused */ |
||||
u32 mrctrl2; /* 0x01c unused */ |
||||
u32 derateen; /* 0x020 unused */ |
||||
u32 derateint; /* 0x024 unused */ |
||||
u8 reserved_0x028[8]; /* 0x028 */ |
||||
u32 pwrctl; /* 0x030 unused */ |
||||
u32 pwrtmg; /* 0x034 unused */ |
||||
u32 hwlpctl; /* 0x038 unused */ |
||||
u8 reserved_0x03c[20]; /* 0x03c */ |
||||
u32 rfshctl0; /* 0x050 unused */ |
||||
u32 rfshctl1; /* 0x054 unused */ |
||||
u8 reserved_0x058[8]; /* 0x05c */ |
||||
u32 rfshctl3; /* 0x060 */ |
||||
u32 rfshtmg; /* 0x064 */ |
||||
u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */ |
||||
u32 init[8]; /* 0x0d0 */ |
||||
u32 dimmctl; /* 0x0f0 unused */ |
||||
u32 rankctl; /* 0x0f4 */ |
||||
u8 reserved_0x0f8[8]; /* 0x0f8 */ |
||||
u32 dramtmg[17]; /* 0x100 */ |
||||
u8 reserved_0x144[60]; /* 0x144 */ |
||||
u32 zqctl[3]; /* 0x180 */ |
||||
u32 zqstat; /* 0x18c unused */ |
||||
u32 dfitmg0; /* 0x190 */ |
||||
u32 dfitmg1; /* 0x194 */ |
||||
u32 dfilpcfg[2]; /* 0x198 unused */ |
||||
u32 dfiupd[3]; /* 0x1a0 */ |
||||
u32 reserved_0x1ac; /* 0x1ac */ |
||||
u32 dfimisc; /* 0x1b0 */ |
||||
u32 dfitmg2; /* 0x1b4 unused, may not exist */ |
||||
u8 reserved_0x1b8[8]; /* 0x1b8 */ |
||||
u32 dbictl; /* 0x1c0 */ |
||||
u8 reserved_0x1c4[60]; /* 0x1c4 */ |
||||
u32 addrmap[12]; /* 0x200 */ |
||||
u8 reserved_0x230[16]; /* 0x230 */ |
||||
u32 odtcfg; /* 0x240 */ |
||||
u32 odtmap; /* 0x244 */ |
||||
u8 reserved_0x248[8]; /* 0x248 */ |
||||
u32 sched[2]; /* 0x250 */ |
||||
u8 reserved_0x258[180]; /* 0x258 */ |
||||
u32 dbgcmd; /* 0x30c unused */ |
||||
u32 dbgstat; /* 0x310 unused */ |
||||
u8 reserved_0x314[12]; /* 0x314 */ |
||||
u32 swctl; /* 0x320 */ |
||||
u32 swstat; /* 0x324 */ |
||||
}; |
||||
check_member(sunxi_mctl_ctl_reg, swstat, 0x324); |
||||
|
||||
#define MSTR_DEVICETYPE_DDR3 BIT(0) |
||||
#define MSTR_DEVICETYPE_LPDDR2 BIT(2) |
||||
#define MSTR_DEVICETYPE_LPDDR3 BIT(3) |
||||
#define MSTR_DEVICETYPE_DDR4 BIT(4) |
||||
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) |
||||
#define MSTR_2TMODE BIT(10) |
||||
#define MSTR_BUSWIDTH_FULL (0 << 12) |
||||
#define MSTR_BUSWIDTH_HALF (1 << 12) |
||||
#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) |
||||
#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) |
||||
|
||||
/*
|
||||
* The following register information is based on Zynq UltraScale+ |
||||
* MPSoC Register Reference, as it's the currently only known |
||||
* DDR PHY similar to the one used in H6; however although the |
||||
* map is similar, the bit fields definitions are different. |
||||
* |
||||
* Other DesignWare DDR PHY's have similar register names, but the |
||||
* offset and definitions are both different. |
||||
*/ |
||||
struct sunxi_mctl_phy_reg { |
||||
u32 ver; /* 0x000 guess based on similar PHYs */ |
||||
u32 pir; /* 0x004 */ |
||||
u8 reserved_0x008[8]; /* 0x008 */ |
||||
/*
|
||||
* The ZynqMP manual didn't document PGCR1, however this register |
||||
* exists on H6 and referenced by libdram. |
||||
*/ |
||||
u32 pgcr[8]; /* 0x010 */ |
||||
/*
|
||||
* By comparing the hardware and the ZynqMP manual, the PGSR seems |
||||
* to start at 0x34 on H6. |
||||
*/ |
||||
u8 reserved_0x030[4]; /* 0x030 */ |
||||
u32 pgsr[3]; /* 0x034 */ |
||||
u32 ptr[7]; /* 0x040 */ |
||||
/*
|
||||
* According to ZynqMP reference there's PLLCR0~6 in this area, |
||||
* but they're tagged "Type B PLL Only" and H6 seems to have |
||||
* no them. |
||||
* 0x080 is not present in ZynqMP reference but it seems to be |
||||
* present on H6. |
||||
*/ |
||||
u8 reserved_0x05c[36]; /* 0x05c */ |
||||
u32 unk_0x080; /* 0x080 */ |
||||
u8 reserved_0x084[4]; /* 0x084 */ |
||||
u32 dxccr; /* 0x088 */ |
||||
u8 reserved_0x08c[4]; /* 0x08c */ |
||||
u32 dsgcr; /* 0x090 */ |
||||
u8 reserved_0x094[4]; /* 0x094 */ |
||||
u32 odtcr; /* 0x098 */ |
||||
u8 reserved_0x09c[4]; /* 0x09c */ |
||||
u32 aacr; /* 0x0a0 */ |
||||
u8 reserved_0x0a4[32]; /* 0x0a4 */ |
||||
u32 gpr1; /* 0x0c4 */ |
||||
u8 reserved_0x0c8[56]; /* 0x0c8 */ |
||||
u32 dcr; /* 0x100 */ |
||||
u8 reserved_0x104[12]; /* 0x104 */ |
||||
u32 dtpr[7]; /* 0x110 */ |
||||
u8 reserved_0x12c[20]; /* 0x12c */ |
||||
u32 rdimmgcr[3]; /* 0x140 */ |
||||
u8 reserved_0x14c[4]; /* 0x14c */ |
||||
u32 rdimmcr[5]; /* 0x150 */ |
||||
u8 reserved_0x164[4]; /* 0x164 */ |
||||
u32 schcr[2]; /* 0x168 */ |
||||
u8 reserved_0x170[16]; /* 0x170 */ |
||||
/*
|
||||
* The ZynqMP manual documents MR0~7, 11~14 and 22. |
||||
*/ |
||||
u32 mr[23]; /* 0x180 */ |
||||
u8 reserved_0x1dc[36]; /* 0x1dc */ |
||||
u32 dtcr[2]; /* 0x200 */ |
||||
u32 dtar[3]; /* 0x208 */ |
||||
u8 reserved_0x214[4]; /* 0x214 */ |
||||
u32 dtdr[2]; /* 0x218 */ |
||||
u8 reserved_0x220[16]; /* 0x220 */ |
||||
u32 dtedr0; /* 0x230 */ |
||||
u32 dtedr1; /* 0x234 */ |
||||
u32 dtedr2; /* 0x238 */ |
||||
u32 vtdr; /* 0x23c */ |
||||
u32 catr[2]; /* 0x240 */ |
||||
u8 reserved_0x248[8]; |
||||
u32 dqsdr[3]; /* 0x250 */ |
||||
u32 dtedr3; /* 0x25c */ |
||||
u8 reserved_0x260[160]; /* 0x260 */ |
||||
u32 dcuar; /* 0x300 */ |
||||
u32 dcudr; /* 0x304 */ |
||||
u32 dcurr; /* 0x308 */ |
||||
u32 dculr; /* 0x30c */ |
||||
u32 dcugcr; /* 0x310 */ |
||||
u32 dcutpr; /* 0x314 */ |
||||
u32 dcusr[2]; /* 0x318 */ |
||||
u8 reserved_0x320[444]; /* 0x320 */ |
||||
u32 rankidr; /* 0x4dc */ |
||||
u32 riocr[6]; /* 0x4e0 */ |
||||
u8 reserved_0x4f8[8]; /* 0x4f8 */ |
||||
u32 aciocr[6]; /* 0x500 */ |
||||
u8 reserved_0x518[8]; /* 0x518 */ |
||||
u32 iovcr[2]; /* 0x520 */ |
||||
u32 vtcr[2]; /* 0x528 */ |
||||
u8 reserved_0x530[16]; /* 0x530 */ |
||||
u32 acbdlr[17]; /* 0x540 */ |
||||
u32 aclcdlr; /* 0x584 */ |
||||
u8 reserved_0x588[24]; /* 0x588 */ |
||||
u32 acmdlr[2]; /* 0x5a0 */ |
||||
u8 reserved_0x5a8[216]; /* 0x5a8 */ |
||||
struct { |
||||
u32 zqcr; /* 0x00 only the first one valid */ |
||||
u32 zqpr[2]; /* 0x04 */ |
||||
u32 zqdr[2]; /* 0x0c */ |
||||
u32 zqor[2]; /* 0x14 */ |
||||
u32 zqsr; /* 0x1c */ |
||||
} zq[2]; /* 0x680, 0x6a0 */ |
||||
u8 reserved_0x6c0[64]; /* 0x6c0 */ |
||||
struct { |
||||
u32 gcr[7]; /* 0x00 */ |
||||
u8 reserved_0x1c[36]; /* 0x1c */ |
||||
u32 bdlr0; /* 0x40 */ |
||||
u32 bdlr1; /* 0x44 */ |
||||
u32 bdlr2; /* 0x48 */ |
||||
u8 reserved_0x4c[4]; /* 0x4c */ |
||||
u32 bdlr3; /* 0x50 */ |
||||
u32 bdlr4; /* 0x54 */ |
||||
u32 bdlr5; /* 0x58 */ |
||||
u8 reserved_0x5c[4]; /* 0x5c */ |
||||
u32 bdlr6; /* 0x60 */ |
||||
u8 reserved_0x64[28]; /* 0x64 */ |
||||
u32 lcdlr[6]; /* 0x80 */ |
||||
u8 reserved_0x98[8]; /* 0x98 */ |
||||
u32 mdlr[2]; /* 0xa0 */ |
||||
u8 reserved_0xa8[24]; /* 0xa8 */ |
||||
u32 gtr0; /* 0xc0 */ |
||||
u8 reserved_0xc4[12]; /* 0xc4 */ |
||||
/*
|
||||
* DXnRSR0 is not documented in ZynqMP manual but |
||||
* it's used in libdram. |
||||
*/ |
||||
u32 rsr[4]; /* 0xd0 */ |
||||
u32 gsr[4]; /* 0xe0 */ |
||||
u8 reserved_0xf0[16]; /* 0xf0 */ |
||||
} dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */ |
||||
}; |
||||
check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); |
||||
|
||||
#define PIR_INIT BIT(0) |
||||
#define PIR_ZCAL BIT(1) |
||||
#define PIR_CA BIT(2) |
||||
#define PIR_PLLINIT BIT(4) |
||||
#define PIR_DCAL BIT(5) |
||||
#define PIR_PHYRST BIT(6) |
||||
#define PIR_DRAMRST BIT(7) |
||||
#define PIR_DRAMINIT BIT(8) |
||||
#define PIR_WL BIT(9) |
||||
#define PIR_QSGATE BIT(10) |
||||
#define PIR_WLADJ BIT(11) |
||||
#define PIR_RDDSKW BIT(12) |
||||
#define PIR_WRDSKW BIT(13) |
||||
#define PIR_RDEYE BIT(14) |
||||
#define PIR_WREYE BIT(15) |
||||
#define PIR_VREF BIT(17) |
||||
#define PIR_CTLDINIT BIT(18) |
||||
#define PIR_DQS2DQ BIT(20) |
||||
#define PIR_DCALPSE BIT(29) |
||||
#define PIR_ZCALBYP BIT(30) |
||||
|
||||
#define DCR_LPDDR3 (1 << 0) |
||||
#define DCR_DDR3 (3 << 0) |
||||
#define DCR_DDR4 (4 << 0) |
||||
#define DCR_DDR8BANK BIT(3) |
||||
|
||||
static inline int ns_to_t(int nanoseconds) |
||||
{ |
||||
const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; |
||||
|
||||
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); |
||||
} |
||||
|
||||
#endif /* _SUNXI_DRAM_SUN50I_H6_H */ |
||||
@ -0,0 +1,94 @@ |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/clock.h> |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
void clock_init_safe(void) |
||||
{ |
||||
struct sunxi_ccm_reg *const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
clock_set_pll1(408000000); |
||||
|
||||
writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); |
||||
while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) |
||||
; |
||||
|
||||
clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, |
||||
CCM_CPU_AXI_DEFAULT_FACTORS); |
||||
|
||||
writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); |
||||
writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); |
||||
writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); |
||||
|
||||
/*
|
||||
* The mux and factor are set, but the clock will be enabled in |
||||
* DRAM initialization code. |
||||
*/ |
||||
writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); |
||||
} |
||||
#endif |
||||
|
||||
void clock_init_uart(void) |
||||
{ |
||||
struct sunxi_ccm_reg *const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
|
||||
/* uart clock source is apb2 */ |
||||
writel(APB2_CLK_SRC_OSC24M| |
||||
APB2_CLK_RATE_N_1| |
||||
APB2_CLK_RATE_M(1), |
||||
&ccm->apb2_cfg); |
||||
|
||||
/* open the clock for uart */ |
||||
setbits_le32(&ccm->uart_gate_reset, |
||||
1 << (CONFIG_CONS_INDEX - 1)); |
||||
|
||||
/* deassert uart reset */ |
||||
setbits_le32(&ccm->uart_gate_reset, |
||||
1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
void clock_set_pll1(unsigned int clk) |
||||
{ |
||||
struct sunxi_ccm_reg * const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
u32 val; |
||||
|
||||
/* Do not support clocks < 288MHz as they need factor P */ |
||||
if (clk < 288000000) clk = 288000000; |
||||
|
||||
/* Switch to 24MHz clock while changing PLL1 */ |
||||
val = readl(&ccm->cpu_axi_cfg); |
||||
val &= ~CCM_CPU_AXI_MUX_MASK; |
||||
val |= CCM_CPU_AXI_MUX_OSC24M; |
||||
writel(val, &ccm->cpu_axi_cfg); |
||||
|
||||
/* clk = 24*n/p, p is ignored if clock is >288MHz */ |
||||
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | |
||||
CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); |
||||
while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} |
||||
|
||||
/* Switch CPU to PLL1 */ |
||||
val = readl(&ccm->cpu_axi_cfg); |
||||
val &= ~CCM_CPU_AXI_MUX_MASK; |
||||
val |= CCM_CPU_AXI_MUX_PLL_CPUX; |
||||
writel(val, &ccm->cpu_axi_cfg); |
||||
} |
||||
#endif |
||||
|
||||
unsigned int clock_get_pll6(void) |
||||
{ |
||||
struct sunxi_ccm_reg *const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
|
||||
uint32_t rval = readl(&ccm->pll6_cfg); |
||||
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); |
||||
int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> |
||||
CCM_PLL6_CTRL_DIV1_SHIFT) + 1; |
||||
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> |
||||
CCM_PLL6_CTRL_DIV2_SHIFT) + 1; |
||||
/* The register defines PLL6-4X, not plain PLL6 */ |
||||
return 24000000 / 4 * n / div1 / div2; |
||||
} |
||||
@ -0,0 +1,755 @@ |
||||
/*
|
||||
* sun50i H6 platform dram controller init |
||||
* |
||||
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/dram.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <linux/bitops.h> |
||||
#include <linux/kconfig.h> |
||||
|
||||
/*
|
||||
* The DRAM controller structure on H6 is similar to the ones on A23/A80: |
||||
* they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64 |
||||
* /H5/R40 CTL and PHY is composed). |
||||
* |
||||
* COM is allwinner-specific. On H6, the address mapping function is moved |
||||
* from COM to CTL (with the standard ADDRMAP registers on DesignWare memory |
||||
* controller). |
||||
* |
||||
* CTL (controller) and PHY is from DesignWare. |
||||
* |
||||
* The CTL part is a bit similar to the one on A23/A80 (because they all |
||||
* originate from DesignWare), but gets more registers added. |
||||
* |
||||
* The PHY part is quite new, not seen in any previous Allwinner SoCs, and |
||||
* not seen on other SoCs in U-Boot. The only SoC that is also known to have |
||||
* similar PHY is ZynqMP. |
||||
*/ |
||||
|
||||
/*
|
||||
* The delay parameters below allow to allegedly specify delay times of some |
||||
* unknown unit for each individual bit trace in each of the four data bytes |
||||
* the 32-bit wide access consists of. Also three control signals can be |
||||
* adjusted individually. |
||||
*/ |
||||
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) |
||||
/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ |
||||
#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) |
||||
/*
|
||||
* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, |
||||
* Termination and Power down |
||||
*/ |
||||
#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) |
||||
struct dram_para { |
||||
u32 clk; |
||||
enum sunxi_dram_type type; |
||||
u8 cols; |
||||
u8 rows; |
||||
u8 ranks; |
||||
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; |
||||
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; |
||||
}; |
||||
|
||||
static void mctl_sys_init(struct dram_para *para); |
||||
static void mctl_com_init(struct dram_para *para); |
||||
static void mctl_set_timing_lpddr3(struct dram_para *para); |
||||
static void mctl_channel_init(struct dram_para *para); |
||||
|
||||
static void mctl_core_init(struct dram_para *para) |
||||
{ |
||||
mctl_sys_init(para); |
||||
mctl_com_init(para); |
||||
switch (para->type) { |
||||
case SUNXI_DRAM_TYPE_LPDDR3: |
||||
mctl_set_timing_lpddr3(para); |
||||
break; |
||||
default: |
||||
panic("Unsupported DRAM type!"); |
||||
}; |
||||
mctl_channel_init(para); |
||||
} |
||||
|
||||
static void mctl_phy_pir_init(u32 val) |
||||
{ |
||||
struct sunxi_mctl_phy_reg * const mctl_phy = |
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; |
||||
|
||||
writel(val | BIT(0), &mctl_phy->pir); |
||||
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); |
||||
} |
||||
|
||||
enum { |
||||
MBUS_PORT_CPU = 0, |
||||
MBUS_PORT_GPU = 1, |
||||
MBUS_PORT_MAHB = 2, |
||||
MBUS_PORT_DMA = 3, |
||||
MBUS_PORT_VE = 4, |
||||
MBUS_PORT_CE = 5, |
||||
MBUS_PORT_TSC0 = 6, |
||||
MBUS_PORT_NDFC0 = 8, |
||||
MBUS_PORT_CSI0 = 11, |
||||
MBUS_PORT_DI0 = 14, |
||||
MBUS_PORT_DI1 = 15, |
||||
MBUS_PORT_DE300 = 16, |
||||
MBUS_PORT_IOMMU = 25, |
||||
MBUS_PORT_VE2 = 26, |
||||
MBUS_PORT_USB3 = 37, |
||||
MBUS_PORT_PCIE = 38, |
||||
MBUS_PORT_VP9 = 39, |
||||
MBUS_PORT_HDCP2 = 40, |
||||
}; |
||||
|
||||
enum { |
||||
MBUS_QOS_LOWEST = 0, |
||||
MBUS_QOS_LOW, |
||||
MBUS_QOS_HIGH, |
||||
MBUS_QOS_HIGHEST |
||||
}; |
||||
inline void mbus_configure_port(u8 port, |
||||
bool bwlimit, |
||||
bool priority, |
||||
u8 qos, |
||||
u8 waittime, |
||||
u8 acs, |
||||
u16 bwl0, |
||||
u16 bwl1, |
||||
u16 bwl2) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
|
||||
const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) |
||||
| (priority ? (1 << 1) : 0) |
||||
| ((qos & 0x3) << 2) |
||||
| ((waittime & 0xf) << 4) |
||||
| ((acs & 0xff) << 8) |
||||
| (bwl0 << 16) ); |
||||
const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff); |
||||
|
||||
debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); |
||||
writel(cfg0, &mctl_com->master[port].cfg0); |
||||
writel(cfg1, &mctl_com->master[port].cfg1); |
||||
} |
||||
|
||||
#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ |
||||
mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
|
||||
MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2) |
||||
|
||||
static void mctl_set_master_priority(void) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
|
||||
/* enable bandwidth limit windows and set windows size 1us */ |
||||
writel(399, &mctl_com->tmr); |
||||
writel(BIT(16), &mctl_com->bwcr); |
||||
|
||||
MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100); |
||||
MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256); |
||||
MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96); |
||||
MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80); |
||||
MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000); |
||||
MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32); |
||||
MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32); |
||||
MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64); |
||||
MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100); |
||||
MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64); |
||||
MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400); |
||||
MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32); |
||||
MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000); |
||||
MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64); |
||||
MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32); |
||||
MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000); |
||||
MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32); |
||||
} |
||||
|
||||
static u32 mr_lpddr3[12] = { |
||||
0x00000000, 0x00000043, 0x0000001a, 0x00000001, |
||||
0x00000000, 0x00000000, 0x00000048, 0x00000000, |
||||
0x00000000, 0x00000000, 0x00000000, 0x00000003, |
||||
}; |
||||
|
||||
/* TODO: flexible timing */ |
||||
static void mctl_set_timing_lpddr3(struct dram_para *para) |
||||
{ |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
struct sunxi_mctl_phy_reg * const mctl_phy = |
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; |
||||
|
||||
u8 tccd = 2; |
||||
u8 tfaw = max(ns_to_t(50), 4); |
||||
u8 trrd = max(ns_to_t(10), 2); |
||||
u8 trcd = max(ns_to_t(24), 2); |
||||
u8 trc = ns_to_t(70); |
||||
u8 txp = max(ns_to_t(8), 2); |
||||
u8 twtr = max(ns_to_t(8), 2); |
||||
u8 trtp = max(ns_to_t(8), 2); |
||||
u8 twr = max(ns_to_t(15), 2); |
||||
u8 trp = ns_to_t(18); |
||||
u8 tras = ns_to_t(42); |
||||
u8 twtr_sa = ns_to_t(5); |
||||
u8 tcksrea = ns_to_t(11); |
||||
u16 trefi = ns_to_t(3900) / 32; |
||||
u16 trfc = ns_to_t(210); |
||||
u16 txsr = ns_to_t(220); |
||||
|
||||
if (CONFIG_DRAM_CLK % 400 == 0) { |
||||
/* Round up these parameters */ |
||||
twtr_sa++; |
||||
tcksrea++; |
||||
} |
||||
|
||||
u8 tmrw = 5; |
||||
u8 tmrd = 5; |
||||
u8 tmod = 12; |
||||
u8 tcke = 3; |
||||
u8 tcksrx = 5; |
||||
u8 tcksre = 5; |
||||
u8 tckesr = 5; |
||||
u8 trasmax = CONFIG_DRAM_CLK / 60; |
||||
u8 txs = 4; |
||||
u8 txsdll = 4; |
||||
u8 txsabort = 4; |
||||
u8 txsfast = 4; |
||||
|
||||
u8 tcl = 5; /* CL 10 */ |
||||
u8 tcwl = 3; /* CWL 6 */ |
||||
u8 t_rdata_en = twtr_sa + 8; |
||||
|
||||
u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ |
||||
u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ |
||||
u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ |
||||
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ |
||||
|
||||
u8 twtp = tcwl + 4 + twr + 1; |
||||
/*
|
||||
* The code below for twr2rd and trd2wr follows the IP core's |
||||
* document from ZynqMP and i.MX7. The BSP has both number |
||||
* substracted by 2. |
||||
*/ |
||||
u8 twr2rd = tcwl + 4 + 1 + twtr; |
||||
u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; |
||||
|
||||
/* set mode register */ |
||||
memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3)); |
||||
|
||||
/* set DRAM timing */ |
||||
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, |
||||
&mctl_ctl->dramtmg[0]); |
||||
writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); |
||||
writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, |
||||
&mctl_ctl->dramtmg[2]); |
||||
writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); |
||||
writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, |
||||
&mctl_ctl->dramtmg[4]); |
||||
writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, |
||||
&mctl_ctl->dramtmg[5]); |
||||
/* Value suggested by ZynqMP manual and used by libdram */ |
||||
writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); |
||||
writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, |
||||
&mctl_ctl->dramtmg[8]); |
||||
writel(txsr, &mctl_ctl->dramtmg[14]); |
||||
|
||||
clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); |
||||
writel(0, &mctl_ctl->dfimisc); |
||||
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); |
||||
|
||||
/*
|
||||
* Set timing registers of the PHY. |
||||
* Note: the PHY is clocked 2x from the DRAM frequency. |
||||
*/ |
||||
writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), |
||||
&mctl_phy->dtpr[0]); |
||||
writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); |
||||
writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); |
||||
writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8), |
||||
&mctl_phy->dtpr[3]); |
||||
writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); |
||||
writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); |
||||
writel(0x0505, &mctl_phy->dtpr[6]); |
||||
|
||||
/* Configure DFI timing */ |
||||
writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, |
||||
&mctl_ctl->dfitmg0); |
||||
writel(0x040201, &mctl_ctl->dfitmg1); |
||||
|
||||
/* Configure PHY timing */ |
||||
writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); |
||||
writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); |
||||
|
||||
/* set refresh timing */ |
||||
writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); |
||||
} |
||||
|
||||
static void mctl_sys_init(struct dram_para *para) |
||||
{ |
||||
struct sunxi_ccm_reg * const ccm = |
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
|
||||
/* Put all DRAM-related blocks to reset state */ |
||||
clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); |
||||
writel(0, &ccm->dram_gate_reset); |
||||
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); |
||||
clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); |
||||
|
||||
udelay(5); |
||||
|
||||
/* Set PLL5 rate to doubled DRAM clock rate */ |
||||
writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | |
||||
CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg); |
||||
mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); |
||||
|
||||
/* Configure DRAM mod clock */ |
||||
writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); |
||||
setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); |
||||
writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset); |
||||
|
||||
/* Disable all channels */ |
||||
writel(0, &mctl_com->maer0); |
||||
writel(0, &mctl_com->maer1); |
||||
writel(0, &mctl_com->maer2); |
||||
|
||||
/* Configure MBUS and enable DRAM mod reset */ |
||||
setbits_le32(&ccm->mbus_cfg, MBUS_RESET); |
||||
setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); |
||||
setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); |
||||
udelay(5); |
||||
|
||||
/* Unknown hack from the BSP, which enables access of mctl_ctl regs */ |
||||
writel(0x8000, &mctl_ctl->unk_0x00c); |
||||
} |
||||
|
||||
static void mctl_set_addrmap(struct dram_para *para) |
||||
{ |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
u8 cols = para->cols; |
||||
u8 rows = para->rows; |
||||
u8 ranks = para->ranks; |
||||
|
||||
/* Ranks */ |
||||
if (ranks == 2) |
||||
mctl_ctl->addrmap[0] = rows + cols - 3; |
||||
else |
||||
mctl_ctl->addrmap[0] = 0x1F; |
||||
|
||||
/* Banks, hardcoded to 8 banks now */ |
||||
mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16; |
||||
|
||||
/* Columns */ |
||||
mctl_ctl->addrmap[2] = 0; |
||||
switch (cols) { |
||||
case 8: |
||||
mctl_ctl->addrmap[3] = 0x1F1F0000; |
||||
mctl_ctl->addrmap[4] = 0x1F1F; |
||||
break; |
||||
case 9: |
||||
mctl_ctl->addrmap[3] = 0x1F000000; |
||||
mctl_ctl->addrmap[4] = 0x1F1F; |
||||
break; |
||||
case 10: |
||||
mctl_ctl->addrmap[3] = 0; |
||||
mctl_ctl->addrmap[4] = 0x1F1F; |
||||
break; |
||||
case 11: |
||||
mctl_ctl->addrmap[3] = 0; |
||||
mctl_ctl->addrmap[4] = 0x1F00; |
||||
break; |
||||
case 12: |
||||
mctl_ctl->addrmap[3] = 0; |
||||
mctl_ctl->addrmap[4] = 0; |
||||
break; |
||||
default: |
||||
panic("Unsupported DRAM configuration: column number invalid\n"); |
||||
} |
||||
|
||||
/* Rows */ |
||||
mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24); |
||||
switch (rows) { |
||||
case 13: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00; |
||||
mctl_ctl->addrmap[7] = 0x0F0F; |
||||
break; |
||||
case 14: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000; |
||||
mctl_ctl->addrmap[7] = 0x0F0F; |
||||
break; |
||||
case 15: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000; |
||||
mctl_ctl->addrmap[7] = 0x0F0F; |
||||
break; |
||||
case 16: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24); |
||||
mctl_ctl->addrmap[7] = 0x0F0F; |
||||
break; |
||||
case 17: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24); |
||||
mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00; |
||||
break; |
||||
case 18: |
||||
mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24); |
||||
mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8); |
||||
break; |
||||
default: |
||||
panic("Unsupported DRAM configuration: row number invalid\n"); |
||||
} |
||||
|
||||
/* Bank groups, DDR4 only */ |
||||
mctl_ctl->addrmap[8] = 0x3F3F; |
||||
} |
||||
|
||||
static void mctl_com_init(struct dram_para *para) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
struct sunxi_mctl_phy_reg * const mctl_phy = |
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; |
||||
u32 reg_val, tmp; |
||||
|
||||
mctl_set_addrmap(para); |
||||
|
||||
setbits_le32(&mctl_com->cr, BIT(31)); |
||||
/*
|
||||
* This address is magic; it's in SID memory area, but there's no |
||||
* known definition of it. |
||||
* On my Pine H64 board it has content 7. |
||||
*/ |
||||
if (readl(0x03006100) == 7) |
||||
clrbits_le32(&mctl_com->cr, BIT(27)); |
||||
else if (readl(0x03006100) == 3) |
||||
setbits_le32(&mctl_com->cr, BIT(27)); |
||||
|
||||
if (para->clk > 408) |
||||
reg_val = 0xf00; |
||||
else if (para->clk > 246) |
||||
reg_val = 0x1f00; |
||||
else |
||||
reg_val = 0x3f00; |
||||
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); |
||||
|
||||
/* TODO: half DQ, non-LPDDR3 types */ |
||||
writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL | |
||||
MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) | |
||||
0x80000000, &mctl_ctl->mstr); |
||||
writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr); |
||||
|
||||
if (para->ranks == 2) |
||||
writel(0x0303, &mctl_ctl->odtmap); |
||||
else |
||||
writel(0x0201, &mctl_ctl->odtmap); |
||||
|
||||
/* TODO: non-LPDDR3 types */ |
||||
tmp = para->clk * 7 / 2000; |
||||
reg_val = 0x0400; |
||||
reg_val |= (tmp + 7) << 24; |
||||
reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16; |
||||
writel(reg_val, &mctl_ctl->odtcfg); |
||||
|
||||
/* TODO: half DQ */ |
||||
} |
||||
|
||||
static void mctl_bit_delay_set(struct dram_para *para) |
||||
{ |
||||
struct sunxi_mctl_phy_reg * const mctl_phy = |
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; |
||||
int i, j; |
||||
u32 val; |
||||
|
||||
for (i = 0; i < 4; i++) { |
||||
val = readl(&mctl_phy->dx[i].bdlr0); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_write_delays[i][j] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr0); |
||||
|
||||
val = readl(&mctl_phy->dx[i].bdlr1); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_write_delays[i][j + 4] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr1); |
||||
|
||||
val = readl(&mctl_phy->dx[i].bdlr2); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_write_delays[i][j + 8] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr2); |
||||
} |
||||
clrbits_le32(&mctl_phy->pgcr[0], BIT(26)); |
||||
|
||||
for (i = 0; i < 4; i++) { |
||||
val = readl(&mctl_phy->dx[i].bdlr3); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_read_delays[i][j] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr3); |
||||
|
||||
val = readl(&mctl_phy->dx[i].bdlr4); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_read_delays[i][j + 4] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr4); |
||||
|
||||
val = readl(&mctl_phy->dx[i].bdlr5); |
||||
for (j = 0; j < 4; j++) |
||||
val += para->dx_read_delays[i][j + 8] << (j * 8); |
||||
writel(val, &mctl_phy->dx[i].bdlr5); |
||||
|
||||
val = readl(&mctl_phy->dx[i].bdlr6); |
||||
val += (para->dx_read_delays[i][12] << 8) | |
||||
(para->dx_read_delays[i][13] << 16); |
||||
writel(val, &mctl_phy->dx[i].bdlr6); |
||||
} |
||||
setbits_le32(&mctl_phy->pgcr[0], BIT(26)); |
||||
udelay(1); |
||||
|
||||
for (i = 1; i < 14; i++) { |
||||
val = readl(&mctl_phy->acbdlr[i]); |
||||
val += 0x0a0a0a0a; |
||||
writel(val, &mctl_phy->acbdlr[i]); |
||||
} |
||||
} |
||||
|
||||
static void mctl_channel_init(struct dram_para *para) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
struct sunxi_mctl_ctl_reg * const mctl_ctl = |
||||
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
||||
struct sunxi_mctl_phy_reg * const mctl_phy = |
||||
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; |
||||
int i; |
||||
u32 val; |
||||
|
||||
setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30)); |
||||
setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30)); |
||||
writel(0x2f05, &mctl_ctl->sched[0]); |
||||
setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); |
||||
setbits_le32(&mctl_ctl->dfimisc, BIT(0)); |
||||
setbits_le32(&mctl_ctl->unk_0x00c, BIT(8)); |
||||
clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0); |
||||
/* TODO: non-LPDDR3 types */ |
||||
clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800)); |
||||
clrbits_le32(&mctl_phy->pgcr[6], BIT(0)); |
||||
clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220); |
||||
/* TODO: VT compensation */ |
||||
clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060); |
||||
clrbits_le32(&mctl_phy->vtcr[1], BIT(1)); |
||||
|
||||
for (i = 0; i < 4; i++) |
||||
clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); |
||||
for (i = 0; i < 4; i++) |
||||
clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); |
||||
for (i = 0; i < 4; i++) |
||||
clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); |
||||
|
||||
udelay(100); |
||||
|
||||
if (para->ranks == 2) |
||||
setbits_le32(&mctl_phy->dtcr[1], 0x30000); |
||||
else |
||||
clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); |
||||
|
||||
clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); |
||||
if (para->ranks == 2) { |
||||
writel(0x00010001, &mctl_phy->rankidr); |
||||
writel(0x20000, &mctl_phy->odtcr); |
||||
} else { |
||||
writel(0x0, &mctl_phy->rankidr); |
||||
writel(0x10000, &mctl_phy->odtcr); |
||||
} |
||||
|
||||
/* TODO: non-LPDDR3 types */ |
||||
clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040); |
||||
if (para->clk <= 792) { |
||||
if (para->clk <= 672) { |
||||
if (para->clk <= 600) |
||||
val = 0x300; |
||||
else |
||||
val = 0x400; |
||||
} else { |
||||
val = 0x500; |
||||
} |
||||
} else { |
||||
val = 0x600; |
||||
} |
||||
/* FIXME: NOT REVIEWED YET */ |
||||
clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val); |
||||
clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff, |
||||
CONFIG_DRAM_ZQ & 0xff); |
||||
clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff); |
||||
setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff); |
||||
setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100); |
||||
setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4); |
||||
clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff); |
||||
setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff); |
||||
setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100); |
||||
setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4); |
||||
if (para->type == SUNXI_DRAM_TYPE_LPDDR3) { |
||||
for (i = 1; i < 14; i++) |
||||
writel(0x06060606, &mctl_phy->acbdlr[i]); |
||||
} |
||||
|
||||
/* TODO: non-LPDDR3 types */ |
||||
mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | |
||||
PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | |
||||
PIR_WREYE); |
||||
|
||||
/* TODO: non-LPDDR3 types */ |
||||
for (i = 0; i < 4; i++) |
||||
writel(0x00000909, &mctl_phy->dx[i].gcr[5]); |
||||
|
||||
for (i = 0; i < 4; i++) { |
||||
if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) |
||||
val = 0x0; |
||||
else |
||||
val = 0xaaaa; |
||||
clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); |
||||
|
||||
if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) |
||||
val = 0x0; |
||||
else |
||||
val = 0x2020; |
||||
clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); |
||||
} |
||||
|
||||
mctl_bit_delay_set(para); |
||||
udelay(1); |
||||
|
||||
setbits_le32(&mctl_phy->pgcr[6], BIT(0)); |
||||
clrbits_le32(&mctl_phy->pgcr[6], 0xfff8); |
||||
for (i = 0; i < 4; i++) |
||||
clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); |
||||
udelay(10); |
||||
|
||||
if (readl(&mctl_phy->pgsr[0]) & 0x400000) |
||||
{ |
||||
/*
|
||||
* Detect single rank. |
||||
* TODO: also detect half DQ. |
||||
*/ |
||||
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && |
||||
(readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 && |
||||
(readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 && |
||||
(readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) { |
||||
para->ranks = 1; |
||||
/* Restart DRAM initialization from scratch. */ |
||||
mctl_core_init(para); |
||||
return; |
||||
} |
||||
else { |
||||
panic("This DRAM setup is currently not supported.\n"); |
||||
} |
||||
} |
||||
|
||||
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { |
||||
/* Oops! There's something wrong! */ |
||||
debug("PLL = %x\n", readl(0x3001010)); |
||||
debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0])); |
||||
for (i = 0; i < 4; i++) |
||||
debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0])); |
||||
panic("Error while initializing DRAM PHY!\n"); |
||||
} |
||||
|
||||
clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40); |
||||
clrbits_le32(&mctl_phy->pgcr[1], 0x40); |
||||
clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); |
||||
writel(1, &mctl_ctl->swctl); |
||||
mctl_await_completion(&mctl_ctl->swstat, 1, 1); |
||||
clrbits_le32(&mctl_ctl->rfshctl3, BIT(0)); |
||||
|
||||
setbits_le32(&mctl_com->unk_0x014, BIT(31)); |
||||
writel(0xffffffff, &mctl_com->maer0); |
||||
writel(0x7ff, &mctl_com->maer1); |
||||
writel(0xffff, &mctl_com->maer2); |
||||
} |
||||
|
||||
static void mctl_auto_detect_dram_size(struct dram_para *para) |
||||
{ |
||||
/* TODO: non-LPDDR3, half DQ */ |
||||
/*
|
||||
* Detect rank number by the code in mctl_channel_init. Furtherly |
||||
* when DQ detection is available it will also be executed there. |
||||
*/ |
||||
mctl_core_init(para); |
||||
|
||||
/* detect row address bits */ |
||||
para->cols = 8; |
||||
para->rows = 18; |
||||
mctl_core_init(para); |
||||
|
||||
for (para->rows = 13; para->rows < 18; para->rows++) { |
||||
/* 8 banks, 8 bit per byte and 32 bit width */ |
||||
if (mctl_mem_matches((1 << (para->rows + para->cols + 5)))) |
||||
break; |
||||
} |
||||
|
||||
/* detect column address bits */ |
||||
para->cols = 11; |
||||
mctl_core_init(para); |
||||
|
||||
for (para->cols = 8; para->cols < 11; para->cols++) { |
||||
/* 8 bits per byte and 32 bit width */ |
||||
if (mctl_mem_matches(1 << (para->cols + 2))) |
||||
break; |
||||
} |
||||
} |
||||
|
||||
unsigned long mctl_calc_size(struct dram_para *para) |
||||
{ |
||||
/* TODO: non-LPDDR3, half DQ */ |
||||
|
||||
/* 8 banks, 32-bit (4 byte) data width */ |
||||
return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks; |
||||
} |
||||
|
||||
#define SUN50I_H6_DX_WRITE_DELAYS \ |
||||
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} |
||||
#define SUN50I_H6_DX_READ_DELAYS \ |
||||
{{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
|
||||
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
|
||||
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
|
||||
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }} |
||||
|
||||
unsigned long sunxi_dram_init(void) |
||||
{ |
||||
struct sunxi_mctl_com_reg * const mctl_com = |
||||
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
||||
struct dram_para para = { |
||||
.clk = CONFIG_DRAM_CLK, |
||||
.type = SUNXI_DRAM_TYPE_LPDDR3, |
||||
.ranks = 2, |
||||
.cols = 11, |
||||
.rows = 14, |
||||
.dx_read_delays = SUN50I_H6_DX_READ_DELAYS, |
||||
.dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS, |
||||
}; |
||||
|
||||
unsigned long size; |
||||
|
||||
/* RES_CAL_CTRL_REG in BSP U-boot*/ |
||||
setbits_le32(0x7010310, BIT(8)); |
||||
clrbits_le32(0x7010318, 0x3f); |
||||
|
||||
mctl_auto_detect_dram_size(¶); |
||||
|
||||
mctl_core_init(¶); |
||||
|
||||
size = mctl_calc_size(¶); |
||||
|
||||
clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0); |
||||
|
||||
mctl_set_master_priority(); |
||||
|
||||
return size; |
||||
}; |
||||
@ -0,0 +1,14 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN50I_H6=y |
||||
CONFIG_DRAM_ODT_EN=y |
||||
CONFIG_MMC0_CD_PIN="PF6" |
||||
# CONFIG_PSCI_RESET is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_SPL_DOS_PARTITION is not set |
||||
# CONFIG_SPL_ISO_PARTITION is not set |
||||
# CONFIG_SPL_EFI_PARTITION is not set |
||||
@ -0,0 +1,15 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SUNXI=y |
||||
CONFIG_MACH_SUN50I_H6=y |
||||
CONFIG_DRAM_ODT_EN=y |
||||
CONFIG_MMC0_CD_PIN="PF6" |
||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2 |
||||
# CONFIG_PSCI_RESET is not set |
||||
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" |
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
||||
CONFIG_SPL=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_SPL_DOS_PARTITION is not set |
||||
# CONFIG_SPL_ISO_PARTITION is not set |
||||
# CONFIG_SPL_EFI_PARTITION is not set |
||||
@ -0,0 +1,125 @@ |
||||
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ |
||||
#define _DT_BINDINGS_CLK_SUN50I_H6_H_ |
||||
|
||||
#define CLK_PLL_PERIPH0 3 |
||||
|
||||
#define CLK_CPUX 21 |
||||
|
||||
#define CLK_APB1 26 |
||||
|
||||
#define CLK_DE 29 |
||||
#define CLK_BUS_DE 30 |
||||
#define CLK_DEINTERLACE 31 |
||||
#define CLK_BUS_DEINTERLACE 32 |
||||
#define CLK_GPU 33 |
||||
#define CLK_BUS_GPU 34 |
||||
#define CLK_CE 35 |
||||
#define CLK_BUS_CE 36 |
||||
#define CLK_VE 37 |
||||
#define CLK_BUS_VE 38 |
||||
#define CLK_EMCE 39 |
||||
#define CLK_BUS_EMCE 40 |
||||
#define CLK_VP9 41 |
||||
#define CLK_BUS_VP9 42 |
||||
#define CLK_BUS_DMA 43 |
||||
#define CLK_BUS_MSGBOX 44 |
||||
#define CLK_BUS_SPINLOCK 45 |
||||
#define CLK_BUS_HSTIMER 46 |
||||
#define CLK_AVS 47 |
||||
#define CLK_BUS_DBG 48 |
||||
#define CLK_BUS_PSI 49 |
||||
#define CLK_BUS_PWM 50 |
||||
#define CLK_BUS_IOMMU 51 |
||||
|
||||
#define CLK_MBUS_DMA 53 |
||||
#define CLK_MBUS_VE 54 |
||||
#define CLK_MBUS_CE 55 |
||||
#define CLK_MBUS_TS 56 |
||||
#define CLK_MBUS_NAND 57 |
||||
#define CLK_MBUS_CSI 58 |
||||
#define CLK_MBUS_DEINTERLACE 59 |
||||
|
||||
#define CLK_NAND0 61 |
||||
#define CLK_NAND1 62 |
||||
#define CLK_BUS_NAND 63 |
||||
#define CLK_MMC0 64 |
||||
#define CLK_MMC1 65 |
||||
#define CLK_MMC2 66 |
||||
#define CLK_BUS_MMC0 67 |
||||
#define CLK_BUS_MMC1 68 |
||||
#define CLK_BUS_MMC2 69 |
||||
#define CLK_BUS_UART0 70 |
||||
#define CLK_BUS_UART1 71 |
||||
#define CLK_BUS_UART2 72 |
||||
#define CLK_BUS_UART3 73 |
||||
#define CLK_BUS_I2C0 74 |
||||
#define CLK_BUS_I2C1 75 |
||||
#define CLK_BUS_I2C2 76 |
||||
#define CLK_BUS_I2C3 77 |
||||
#define CLK_BUS_SCR0 78 |
||||
#define CLK_BUS_SCR1 79 |
||||
#define CLK_SPI0 80 |
||||
#define CLK_SPI1 81 |
||||
#define CLK_BUS_SPI0 82 |
||||
#define CLK_BUS_SPI1 83 |
||||
#define CLK_BUS_EMAC 84 |
||||
#define CLK_TS 85 |
||||
#define CLK_BUS_TS 86 |
||||
#define CLK_IR_TX 87 |
||||
#define CLK_BUS_IR_TX 88 |
||||
#define CLK_BUS_THS 89 |
||||
#define CLK_I2S3 90 |
||||
#define CLK_I2S0 91 |
||||
#define CLK_I2S1 92 |
||||
#define CLK_I2S2 93 |
||||
#define CLK_BUS_I2S0 94 |
||||
#define CLK_BUS_I2S1 95 |
||||
#define CLK_BUS_I2S2 96 |
||||
#define CLK_BUS_I2S3 97 |
||||
#define CLK_SPDIF 98 |
||||
#define CLK_BUS_SPDIF 99 |
||||
#define CLK_DMIC 100 |
||||
#define CLK_BUS_DMIC 101 |
||||
#define CLK_AUDIO_HUB 102 |
||||
#define CLK_BUS_AUDIO_HUB 103 |
||||
#define CLK_USB_OHCI0 104 |
||||
#define CLK_USB_PHY0 105 |
||||
#define CLK_USB_PHY1 106 |
||||
#define CLK_USB_OHCI3 107 |
||||
#define CLK_USB_PHY3 108 |
||||
#define CLK_USB_HSIC_12M 109 |
||||
#define CLK_USB_HSIC 110 |
||||
#define CLK_BUS_OHCI0 111 |
||||
#define CLK_BUS_OHCI3 112 |
||||
#define CLK_BUS_EHCI0 113 |
||||
#define CLK_BUS_XHCI 114 |
||||
#define CLK_BUS_EHCI3 115 |
||||
#define CLK_BUS_OTG 116 |
||||
#define CLK_PCIE_REF_100M 117 |
||||
#define CLK_PCIE_REF 118 |
||||
#define CLK_PCIE_REF_OUT 119 |
||||
#define CLK_PCIE_MAXI 120 |
||||
#define CLK_PCIE_AUX 121 |
||||
#define CLK_BUS_PCIE 122 |
||||
#define CLK_HDMI 123 |
||||
#define CLK_HDMI_SLOW 124 |
||||
#define CLK_HDMI_CEC 125 |
||||
#define CLK_BUS_HDMI 126 |
||||
#define CLK_BUS_TCON_TOP 127 |
||||
#define CLK_TCON_LCD0 128 |
||||
#define CLK_BUS_TCON_LCD0 129 |
||||
#define CLK_TCON_TV0 130 |
||||
#define CLK_BUS_TCON_TV0 131 |
||||
#define CLK_CSI_CCI 132 |
||||
#define CLK_CSI_TOP 133 |
||||
#define CLK_CSI_MCLK 134 |
||||
#define CLK_BUS_CSI 135 |
||||
#define CLK_HDCP 136 |
||||
#define CLK_BUS_HDCP 137 |
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ |
||||
@ -0,0 +1,24 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0 */ |
||||
/*
|
||||
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ |
||||
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ |
||||
|
||||
#define CLK_AR100 0 |
||||
|
||||
#define CLK_R_APB1 2 |
||||
|
||||
#define CLK_R_APB1_TIMER 4 |
||||
#define CLK_R_APB1_TWD 5 |
||||
#define CLK_R_APB1_PWM 6 |
||||
#define CLK_R_APB2_UART 7 |
||||
#define CLK_R_APB2_I2C 8 |
||||
#define CLK_R_APB1_IR 9 |
||||
#define CLK_R_APB1_W1 10 |
||||
|
||||
#define CLK_IR 11 |
||||
#define CLK_W1 12 |
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ |
||||
@ -0,0 +1,73 @@ |
||||
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ |
||||
#define _DT_BINDINGS_RESET_SUN50I_H6_H_ |
||||
|
||||
#define RST_MBUS 0 |
||||
#define RST_BUS_DE 1 |
||||
#define RST_BUS_DEINTERLACE 2 |
||||
#define RST_BUS_GPU 3 |
||||
#define RST_BUS_CE 4 |
||||
#define RST_BUS_VE 5 |
||||
#define RST_BUS_EMCE 6 |
||||
#define RST_BUS_VP9 7 |
||||
#define RST_BUS_DMA 8 |
||||
#define RST_BUS_MSGBOX 9 |
||||
#define RST_BUS_SPINLOCK 10 |
||||
#define RST_BUS_HSTIMER 11 |
||||
#define RST_BUS_DBG 12 |
||||
#define RST_BUS_PSI 13 |
||||
#define RST_BUS_PWM 14 |
||||
#define RST_BUS_IOMMU 15 |
||||
#define RST_BUS_DRAM 16 |
||||
#define RST_BUS_NAND 17 |
||||
#define RST_BUS_MMC0 18 |
||||
#define RST_BUS_MMC1 19 |
||||
#define RST_BUS_MMC2 20 |
||||
#define RST_BUS_UART0 21 |
||||
#define RST_BUS_UART1 22 |
||||
#define RST_BUS_UART2 23 |
||||
#define RST_BUS_UART3 24 |
||||
#define RST_BUS_I2C0 25 |
||||
#define RST_BUS_I2C1 26 |
||||
#define RST_BUS_I2C2 27 |
||||
#define RST_BUS_I2C3 28 |
||||
#define RST_BUS_SCR0 29 |
||||
#define RST_BUS_SCR1 30 |
||||
#define RST_BUS_SPI0 31 |
||||
#define RST_BUS_SPI1 32 |
||||
#define RST_BUS_EMAC 33 |
||||
#define RST_BUS_TS 34 |
||||
#define RST_BUS_IR_TX 35 |
||||
#define RST_BUS_THS 36 |
||||
#define RST_BUS_I2S0 37 |
||||
#define RST_BUS_I2S1 38 |
||||
#define RST_BUS_I2S2 39 |
||||
#define RST_BUS_I2S3 40 |
||||
#define RST_BUS_SPDIF 41 |
||||
#define RST_BUS_DMIC 42 |
||||
#define RST_BUS_AUDIO_HUB 43 |
||||
#define RST_USB_PHY0 44 |
||||
#define RST_USB_PHY1 45 |
||||
#define RST_USB_PHY3 46 |
||||
#define RST_USB_HSIC 47 |
||||
#define RST_BUS_OHCI0 48 |
||||
#define RST_BUS_OHCI3 49 |
||||
#define RST_BUS_EHCI0 50 |
||||
#define RST_BUS_XHCI 51 |
||||
#define RST_BUS_EHCI3 52 |
||||
#define RST_BUS_OTG 53 |
||||
#define RST_BUS_PCIE 54 |
||||
#define RST_PCIE_POWERUP 55 |
||||
#define RST_BUS_HDMI 56 |
||||
#define RST_BUS_HDMI_SUB 57 |
||||
#define RST_BUS_TCON_TOP 58 |
||||
#define RST_BUS_TCON_LCD0 59 |
||||
#define RST_BUS_TCON_TV0 60 |
||||
#define RST_BUS_CSI 61 |
||||
#define RST_BUS_HDCP 62 |
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ |
||||
@ -0,0 +1,17 @@ |
||||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ |
||||
/*
|
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ |
||||
#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ |
||||
|
||||
#define RST_R_APB1_TIMER 0 |
||||
#define RST_R_APB1_TWD 1 |
||||
#define RST_R_APB1_PWM 2 |
||||
#define RST_R_APB2_UART 3 |
||||
#define RST_R_APB2_I2C 4 |
||||
#define RST_R_APB1_IR 5 |
||||
#define RST_R_APB1_W1 6 |
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ |
||||
Loading…
Reference in new issue