@ -26,12 +26,6 @@
# if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
# if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
# define CACHE_SETUP 0x1a
# else
# define CACHE_SETUP 0x1e
# endif
DECLARE_GLOBAL_DATA_PTR ;
void __arm_init_before_mmu ( void )
@ -50,9 +44,41 @@ static void cp_delay (void)
asm volatile ( " " : : : " memory " ) ;
}
static inline void dram_bank_mmu_setup ( int bank )
void set_section_dcache ( int section , enum dcache_option option )
{
u32 * page_table = ( u32 * ) gd - > tlb_addr ;
u32 value ;
value = ( section < < MMU_SECTION_SHIFT ) | ( 3 < < 10 ) ;
value | = option ;
page_table [ section ] = value ;
}
void __mmu_page_table_flush ( unsigned long start , unsigned long stop )
{
debug ( " %s: Warning: not implemented \n " , __func__ ) ;
}
void mmu_page_table_flush ( unsigned long start , unsigned long stop )
__attribute__ ( ( weak , alias ( " __mmu_page_table_flush " ) ) ) ;
void mmu_set_region_dcache_behaviour ( u32 start , int size ,
enum dcache_option option )
{
u32 * page_table = ( u32 * ) gd - > tlb_addr ;
u32 upto , end ;
end = ALIGN ( start + size , MMU_SECTION_SIZE ) > > MMU_SECTION_SHIFT ;
start = start > > MMU_SECTION_SHIFT ;
debug ( " %s: start=%x, size=%x, option=%d \n " , __func__ , start , size ,
option ) ;
for ( upto = start ; upto < end ; upto + + )
set_section_dcache ( upto , option ) ;
mmu_page_table_flush ( ( u32 ) & page_table [ start ] , ( u32 ) & page_table [ end ] ) ;
}
static inline void dram_bank_mmu_setup ( int bank )
{
bd_t * bd = gd - > bd ;
int i ;
@ -60,21 +86,24 @@ static inline void dram_bank_mmu_setup(int bank)
for ( i = bd - > bi_dram [ bank ] . start > > 20 ;
i < ( bd - > bi_dram [ bank ] . start + bd - > bi_dram [ bank ] . size ) > > 20 ;
i + + ) {
page_table [ i ] = i < < 20 | ( 3 < < 10 ) | CACHE_SETUP ;
# if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache ( i , DCACHE_WRITETHROUGH ) ;
# else
set_section_dcache ( i , DCACHE_WRITEBACK ) ;
# endif
}
}
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup ( void )
{
u32 * page_table = ( u32 * ) gd - > tlb_addr ;
int i ;
u32 reg ;
arm_init_before_mmu ( ) ;
/* Set up an identity-mapping for all 4GB, rw for everyone */
for ( i = 0 ; i < 4096 ; i + + )
page_table [ i ] = i < < 20 | ( 3 < < 10 ) | 0x12 ;
set_section_dcache ( i , DCACHE_OFF ) ;
for ( i = 0 ; i < CONFIG_NR_DRAM_BANKS ; i + + ) {
dram_bank_mmu_setup ( i ) ;
@ -82,7 +111,7 @@ static inline void mmu_setup(void)
/* Copy the page table address to cp15 */
asm volatile ( " mcr p15, 0, %0, c2, c0, 0 "
: : " r " ( page_table ) : " memory " ) ;
: : " r " ( gd - > tlb_addr ) : " memory " ) ;
/* Set the access control to all-supervisor */
asm volatile ( " mcr p15, 0, %0, c3, c0, 0 "
: : " r " ( ~ 0 ) ) ;