In the programmable clock mode, the SDCLK frequency is incorrectly assigned when the maximum clock has been assigned during probe, this causes the SDHCI not work well. In the programmable clock mode, when calculating the SDCLK Frequency Select, when the maximum clock has been assigned, it is the actual value, should not be multiplied by host->clk_mul. Otherwise, the maximum clock is multiplied host->clk_mul by the base clock achieved from the BASECLKF field of the Capabilities 0 Register. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>master
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