Ocotea: - Add IBM PPC440GX Ref Platform support (Ocotea) Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> Adapted to U-Boot and 440GX port 440gx_enet.c: - Add gracious handling of all Ethernet Pin Selections for 440GX - Add RGMII selection for Cicada CIS8201 Gigabit PHY ppc440.h: - Add needed bit definitions - Fix formatting * Patch by Carl Riechers, 1 Mar 2004: Add PPC440GX prbdv0 divider to fix memory clock calculation. * Patch by Stephan Linz, 27 Feb 2004 - avoid problems for targets without NFS download supportmaster
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@ -0,0 +1,47 @@ |
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend *~
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# IBM 440GX Reference Platform (Ocotea) board
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#
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#TEXT_BASE = 0xFFFE0000
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ifeq ($(ramsym),1) |
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TEXT_BASE = 0x07FD0000
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else |
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TEXT_BASE = 0xFFF80000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
@ -0,0 +1,595 @@ |
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/*
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* (C) Copyright 2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com> |
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* Add support for Am29F016D and dynamic switch setting. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* Modified 4/5/2001 |
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* Wait for completion of each sector erase command issued |
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* 4/5/2001 |
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DEBUGF(x...) printf(x) |
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#else |
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#define DEBUGF(x...) |
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#endif /* DEBUG */ |
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#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
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#define FLASH_ONBD_N 2 /* 00000010 */ |
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#define FLASH_SRAM_SEL 1 /* 00000001 */ |
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#define BOOT_SMALL_FLASH_VAL 4 |
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#define FLASH_ONBD_N_VAL 2 |
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#define FLASH_SRAM_SEL_VAL 1 |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { |
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{0xFF800000, 0xFF900000, 0xFFC00000}, /* 0:000: configuraton 4 */ |
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{0xFF900000, 0xFF800000, 0xFFC00000}, /* 1:001: configuraton 3 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ |
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{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ |
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{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ |
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{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ |
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}; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size(vu_long * addr, flash_info_t * info); |
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static int write_word(flash_info_t * info, ulong dest, ulong data); |
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#ifdef CONFIG_OCOTEA |
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#define ADDR0 0x5555 |
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#define ADDR1 0x2aaa |
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#define FLASH_WORD_SIZE unsigned char |
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#endif |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init(void) |
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{ |
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unsigned long total_b = 0; |
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unsigned long size_b[CFG_MAX_FLASH_BANKS]; |
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unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; |
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unsigned char switch_status; |
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unsigned short index = 0; |
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int i; |
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/* read FPGA base register FPGA_REG0 */ |
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switch_status = *fpga_base; |
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/* check the bitmap of switch status */ |
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if (switch_status & BOOT_SMALL_FLASH) { |
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index += BOOT_SMALL_FLASH_VAL; |
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} |
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if (switch_status & FLASH_ONBD_N) { |
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index += FLASH_ONBD_N_VAL; |
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} |
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if (switch_status & FLASH_SRAM_SEL) { |
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index += FLASH_SRAM_SEL_VAL; |
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} |
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DEBUGF("\n"); |
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DEBUGF("FLASH: Index: %d\n", index); |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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/* check whether the address is 0 */ |
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if (flash_addr_table[index][i] == 0) { |
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continue; |
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} |
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/* call flash_get_size() to initialize sector address */ |
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size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]); |
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flash_info[i].size = size_b[i]; |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
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i, size_b[i], size_b[i] << 20); |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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} |
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total_b += flash_info[i].size; |
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} |
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return total_b; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info(flash_info_t * info) |
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{ |
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int i; |
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int k; |
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int size; |
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int erased; |
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volatile unsigned long *flash; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: |
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printf("AMD "); |
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break; |
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case FLASH_MAN_FUJ: |
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printf("FUJITSU "); |
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break; |
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case FLASH_MAN_SST: |
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printf("SST "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AM040: |
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printf("AM29F040 (512 Kbit, uniform sector size)\n"); |
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break; |
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case FLASH_AM400B: |
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printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: |
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printf("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: |
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printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: |
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printf("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: |
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printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: |
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printf("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: |
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printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: |
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printf("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AMDLV033C: |
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printf("AM29LV033C (32 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_SST800A: |
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printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); |
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break; |
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case FLASH_SST160A: |
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printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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break; |
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} |
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printf(" Size: %ld KB in %d Sectors\n", |
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info->size >> 10, info->sector_count); |
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printf(" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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/*
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* Check if whole sector is erased |
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*/ |
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if (i != (info->sector_count - 1)) |
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size = info->start[i + 1] - info->start[i]; |
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else |
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size = info->start[0] + info->size - info->start[i]; |
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erased = 1; |
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flash = (volatile unsigned long *) info->start[i]; |
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size = size >> 2; /* divide by 4 for longword access */ |
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for (k = 0; k < size; k++) { |
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if (*flash++ != 0xffffffff) { |
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erased = 0; |
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break; |
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} |
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} |
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if ((i % 5) == 0) |
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printf("\n "); |
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printf(" %08lX%s%s", |
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info->start[i], |
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erased ? " E" : " ", info->protect[i] ? "RO " : " "); |
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} |
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printf("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size(vu_long * addr, flash_info_t * info) |
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{ |
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short i; |
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FLASH_WORD_SIZE value; |
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ulong base = (ulong) addr; |
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; |
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DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr); |
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/* Write auto select command: read Manufacturer ID */ |
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udelay(10000); |
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addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
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udelay(1000); |
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addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
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udelay(1000); |
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addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; |
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udelay(1000); |
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value = addr2[0]; |
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DEBUGF("FLASH MANUFACT: %x\n", value); |
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switch (value) { |
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case (FLASH_WORD_SIZE) AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case (FLASH_WORD_SIZE) FUJ_MANUFACT: |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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case (FLASH_WORD_SIZE) SST_MANUFACT: |
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info->flash_id = FLASH_MAN_SST; |
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break; |
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case (FLASH_WORD_SIZE) STM_MANUFACT: |
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info->flash_id = FLASH_MAN_STM; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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value = addr2[1]; /* device ID */ |
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DEBUGF("\nFLASH DEVICEID: %x\n", value); |
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switch (value) { |
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case (FLASH_WORD_SIZE) AMD_ID_LV040B: |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x0080000; /* => 512 ko */ |
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break; |
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case (FLASH_WORD_SIZE) AMD_ID_F040B: |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x0080000; /* => 512 ko */ |
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break; |
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case (FLASH_WORD_SIZE) AMD_ID_LV033C: |
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info->flash_id += FLASH_AMDLV033C; |
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info->sector_count = 64; |
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info->size = 0x00400000; |
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break; /* => 4 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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|
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/* set up sector start address table */ |
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
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(info->flash_id == FLASH_AM040) || |
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(info->flash_id == FLASH_AMD016)) { |
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for (i = 0; i < info->sector_count; i++) |
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info->start[i] = base + (i * 0x00010000); |
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} else { |
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if (info->flash_id & FLASH_BTYPE) { |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00004000; |
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info->start[2] = base + 0x00006000; |
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info->start[3] = base + 0x00008000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000) - 0x00030000; |
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} |
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} else { |
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/* set sector offsets for top boot block type */ |
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i = info->sector_count - 1; |
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info->start[i--] = base + info->size - 0x00004000; |
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info->start[i--] = base + info->size - 0x00006000; |
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info->start[i--] = base + info->size - 0x00008000; |
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for (; i >= 0; i--) { |
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info->start[i] = base + i * 0x00010000; |
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} |
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} |
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} |
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|
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) |
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info->protect[i] = 0; |
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else |
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info->protect[i] = addr2[2] & 1; |
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} |
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|
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/*
|
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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} |
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|
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return (info->size); |
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} |
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|
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int wait_for_DQ7(flash_info_t * info, int sect) |
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{ |
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ulong start, now, last; |
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volatile FLASH_WORD_SIZE *addr = |
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(FLASH_WORD_SIZE *) (info->start[sect]); |
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|
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start = get_timer(0); |
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last = start; |
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while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != |
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(FLASH_WORD_SIZE) 0x00800080) { |
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
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printf("Timeout\n"); |
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return -1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc('.'); |
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last = now; |
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} |
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} |
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return 0; |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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|
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int flash_erase(flash_info_t * info, int s_first, int s_last) |
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{ |
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); |
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volatile FLASH_WORD_SIZE *addr2; |
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int flag, prot, sect, l_sect; |
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int i; |
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|
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf("- missing\n"); |
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} else { |
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printf("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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|
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf("Can't erase unknown flash type - aborted\n"); |
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return 1; |
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} |
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|
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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|
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if (prot) { |
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printf("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf("\n"); |
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} |
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|
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l_sect = -1; |
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|
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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|
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/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); |
||||
printf("Erasing sector %p\n", addr2); |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ |
||||
for (i = 0; i < 50; i++) |
||||
udelay(1000); /* wait 1 ms */ |
||||
} else { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ |
||||
} |
||||
l_sect = sect; |
||||
/*
|
||||
* Wait for each sector to complete, it's more |
||||
* reliable. According to AMD Spec, you must |
||||
* issue all erase commands within a specified |
||||
* timeout. This has been seen to fail, especially |
||||
* if printf()s are included (for debug)!! |
||||
*/ |
||||
wait_for_DQ7(info, sect); |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay(1000); |
||||
|
||||
/* reset to read mode */ |
||||
addr = (FLASH_WORD_SIZE *) info->start[0]; |
||||
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ |
||||
|
||||
printf(" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
for (; i < 4 && cnt > 0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < 4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i = 0; i < 4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i < 4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word(flash_info_t * info, ulong dest, ulong data) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); |
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; |
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; |
||||
ulong start; |
||||
int i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) & |
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { |
||||
return (2); |
||||
} |
||||
|
||||
for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) { |
||||
int flag; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; |
||||
|
||||
dest2[i] = data2[i]; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer(0); |
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != |
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { |
||||
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
@ -0,0 +1,96 @@ |
||||
/* |
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <config.h> |
||||
|
||||
/* General */ |
||||
#define TLB_VALID 0x00000200 |
||||
|
||||
/* Supported page sizes */ |
||||
|
||||
#define SZ_1K 0x00000000 |
||||
#define SZ_4K 0x00000010 |
||||
#define SZ_16K 0x00000020 |
||||
#define SZ_64K 0x00000030 |
||||
#define SZ_256K 0x00000040 |
||||
#define SZ_1M 0x00000050 |
||||
#define SZ_16M 0x00000070 |
||||
#define SZ_256M 0x00000090 |
||||
|
||||
/* Storage attributes */ |
||||
#define SA_W 0x00000800 /* Write-through */ |
||||
#define SA_I 0x00000400 /* Caching inhibited */ |
||||
#define SA_M 0x00000200 /* Memory coherence */ |
||||
#define SA_G 0x00000100 /* Guarded */ |
||||
#define SA_E 0x00000080 /* Endian */ |
||||
|
||||
/* Access control */ |
||||
#define AC_X 0x00000024 /* Execute */ |
||||
#define AC_W 0x00000012 /* Write */ |
||||
#define AC_R 0x00000009 /* Read */ |
||||
|
||||
/* Some handy macros */ |
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00) |
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
||||
#define TLB2(a) ( (a)&0x00000fbf ) |
||||
|
||||
#define tlbtab_start\ |
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\ |
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\ |
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
||||
|
||||
|
||||
/************************************************************************** |
||||
* TLB TABLE |
||||
* |
||||
* This table is used by the cpu boot code to setup the initial tlb |
||||
* entries. Rather than make broad assumptions in the cpu source tree, |
||||
* this table lets each board set things up however they like. |
||||
* |
||||
* Pointer to the table is returned in r1 |
||||
* |
||||
*************************************************************************/ |
||||
|
||||
.section .bootpg,"ax" |
||||
.globl tlbtab
|
||||
|
||||
tlbtab: |
||||
tlbtab_start |
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) |
||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) |
||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) |
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbtab_end |
@ -0,0 +1,459 @@ |
||||
/*
|
||||
* Copyright (C) 2004 PaulReynolds@lhsolutions.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include "ocotea.h" |
||||
#include <asm/processor.h> |
||||
#include <spd_sdram.h> |
||||
#include <440gx_enet.h> |
||||
|
||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
||||
#define FLASH_ONBD_N 2 /* 00000010 */ |
||||
#define FLASH_SRAM_SEL 1 /* 00000001 */ |
||||
|
||||
long int fixed_sdram (void); |
||||
void fpga_init (void); |
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
/*-------------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(xbcfg, EBC_CFG_LE_UNLOCK | |
||||
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | |
||||
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | |
||||
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | |
||||
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)| |
||||
EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| |
||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 4 MB FLASH. Initialize bank 2 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)| |
||||
EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| FPGA. Initialize bank 7 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| |
||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
*-------------------------------------------------------------------*/ |
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic0er, 0x00000000); /* disable all */ |
||||
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ |
||||
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ |
||||
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ |
||||
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic1er, 0x00000000); /* disable all */ |
||||
mtdcr (uic1cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ |
||||
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ |
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
|
||||
fpga_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
|
||||
get_sys_info (&sysinfo); |
||||
|
||||
printf ("Board: IBM 440GX Evaluation Board\n"); |
||||
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); |
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); |
||||
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); |
||||
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); |
||||
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); |
||||
return (0); |
||||
} |
||||
|
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (0); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) 0x00000000; |
||||
uint *pend = (uint *) 0x08000000; |
||||
uint *p; |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
* |
||||
* Assumes: 128 MB, non-ECC, non-registered |
||||
* PLB @ 133 MHz |
||||
* |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
uint reg; |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ |
||||
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
||||
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ |
||||
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ |
||||
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem |
||||
*------------------------------------------------------------------*/ |
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB |
||||
*/ |
||||
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
||||
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ |
||||
/* RA=10 RD=3 */ |
||||
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
||||
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ |
||||
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ |
||||
udelay (400); /* Delay 200 usecs (min) */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ |
||||
for (;;) { |
||||
mfsdram (mem_mcsts, reg); |
||||
if (reg & 0x80000000) |
||||
break; |
||||
} |
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */ |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init(struct pci_controller * hose ) |
||||
{ |
||||
unsigned long strap; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* The ocotea board is always configured as the host & requires the |
||||
* PCI arbiter to be enabled. |
||||
*--------------------------------------------------------------------------*/ |
||||
mfsdr(sdr_sdstp1, strap); |
||||
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ |
||||
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller * hose ) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */ |
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
||||
* options to not support sizes such as 128/256 MB. |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); |
||||
out32r( PCIX0_PIM0LAH, 0 ); |
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
||||
|
||||
out32r( PCIX0_BAR0, 0 ); |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id |
||||
*--------------------------------------------------------------------------*/ |
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); |
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); |
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
/* The ocotea board is always configured as host. */ |
||||
return(1); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
|
||||
void fpga_init(void) |
||||
{ |
||||
unsigned long group; |
||||
unsigned long sdr0_pfc0; |
||||
unsigned long sdr0_pfc1; |
||||
unsigned long sdr0_cust0; |
||||
unsigned long pvr; |
||||
|
||||
mfsdr (sdr_pfc0, sdr0_pfc0); |
||||
mfsdr (sdr_pfc1, sdr0_pfc1); |
||||
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); |
||||
pvr = get_pvr (); |
||||
|
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; |
||||
if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { |
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_ENABLE); |
||||
mtsdr (sdr_pfc0, sdr0_pfc0); |
||||
mtsdr (sdr_pfc1, sdr0_pfc1); |
||||
} else { |
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; |
||||
switch (group) |
||||
{ |
||||
case 0: |
||||
case 1: |
||||
case 2: |
||||
/* CPU trace A */ |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_ENABLE); |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; |
||||
mtsdr (sdr_pfc0, sdr0_pfc0); |
||||
mtsdr (sdr_pfc1, sdr0_pfc1); |
||||
break; |
||||
case 3: |
||||
case 4: |
||||
case 5: |
||||
case 6: |
||||
/* CPU trace B - Over EBMI */ |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; |
||||
mtsdr (sdr_pfc0, sdr0_pfc0); |
||||
mtsdr (sdr_pfc1, sdr0_pfc1); |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_DISABLE); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* Initialize the ethernet specific functions in the fpga */ |
||||
mfsdr(sdr_pfc1, sdr0_pfc1); |
||||
mfsdr(sdr_cust0, sdr0_cust0); |
||||
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && |
||||
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || |
||||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | |
||||
FPGA_REG3_ENET_GROUP7); |
||||
} |
||||
else |
||||
{ |
||||
if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_GROUP7); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_GROUP8); |
||||
} |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | |
||||
FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); |
||||
} |
||||
} |
||||
out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | |
||||
FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | |
||||
FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); |
||||
|
||||
/* reset the gigabyte phy if necessary */ |
||||
if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); |
||||
udelay(10000); |
||||
out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); |
||||
udelay(10000); |
||||
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); |
||||
} |
||||
} |
||||
|
||||
/* Turn off the LED's */ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | |
||||
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | |
||||
FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); |
||||
|
||||
return; |
||||
} |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
|
||||
return (ctrlc()); |
||||
} |
||||
#endif |
||||
|
@ -0,0 +1,140 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* Board specific FPGA stuff ... */ |
||||
#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) |
||||
#define FPGA_REG0_SSCG_MASK 0x80 |
||||
#define FPGA_REG0_SSCG_DISABLE 0x00 |
||||
#define FPGA_REG0_SSCG_ENABLE 0x80 |
||||
#define FPGA_REG0_BOOT_MASK 0x40 |
||||
#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 |
||||
#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 |
||||
#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ARBITER_MASK 0x04 |
||||
#define FPGA_REG0_ARBITER_EXT 0x00 |
||||
#define FPGA_REG0_ARBITER_INT 0x04 |
||||
#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 |
||||
#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 |
||||
#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 |
||||
#define FPGA_REG0_FLASH 0x01 |
||||
#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) |
||||
#define FPGA_REG1_9772_FSELFBX_MASK 0x80 |
||||
#define FPGA_REG1_9772_FSELFBX_6 0x00 |
||||
#define FPGA_REG1_9772_FSELFBX_10 0x80 |
||||
#define FPGA_REG1_9531_SX_MASK 0x60 |
||||
#define FPGA_REG1_9531_SX_33MHZ 0x00 |
||||
#define FPGA_REG1_9531_SX_100MHZ 0x20 |
||||
#define FPGA_REG1_9531_SX_66MHZ 0x40 |
||||
#define FPGA_REG1_9531_SX_133MHZ 0x60 |
||||
#define FPGA_REG1_9772_FSELBX_MASK 0x18 |
||||
#define FPGA_REG1_9772_FSELBX_4 0x00 |
||||
#define FPGA_REG1_9772_FSELBX_6 0x08 |
||||
#define FPGA_REG1_9772_FSELBX_8 0x10 |
||||
#define FPGA_REG1_9772_FSELBX_10 0x18 |
||||
#define FPGA_REG1_SOURCE_MASK 0x07 |
||||
#define FPGA_REG1_SOURCE_TC 0x00 |
||||
#define FPGA_REG1_SOURCE_66MHZ 0x01 |
||||
#define FPGA_REG1_SOURCE_50MHZ 0x02 |
||||
#define FPGA_REG1_SOURCE_33MHZ 0x03 |
||||
#define FPGA_REG1_SOURCE_25MHZ 0x04 |
||||
#define FPGA_REG1_SOURCE_SSDIV1 0x05 |
||||
#define FPGA_REG1_SOURCE_SSDIV2 0x06 |
||||
#define FPGA_REG1_SOURCE_SSDIV4 0x07 |
||||
#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) |
||||
#define FPGA_REG2_TC0 0x80 |
||||
#define FPGA_REG2_TC1 0x40 |
||||
#define FPGA_REG2_TC2 0x20 |
||||
#define FPGA_REG2_TC3 0x10 |
||||
#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG2_EXT_INTFACE_MASK 0x04 |
||||
#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 |
||||
#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 |
||||
#define FPGA_REG2_DEFAULT_UART1_N 0x01 |
||||
#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) |
||||
#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ |
||||
#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ |
||||
#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG3_ENET_GROUP0 0x00 |
||||
#define FPGA_REG3_ENET_GROUP1 0x10 |
||||
#define FPGA_REG3_ENET_GROUP2 0x20 |
||||
#define FPGA_REG3_ENET_GROUP3 0x30 |
||||
#define FPGA_REG3_ENET_GROUP4 0x40 |
||||
#define FPGA_REG3_ENET_GROUP5 0x50 |
||||
#define FPGA_REG3_ENET_GROUP6 0x60 |
||||
#define FPGA_REG3_ENET_GROUP7 0x70 |
||||
#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ |
||||
#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ |
||||
#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ |
||||
#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ |
||||
#define FPGA_REG3_STAT_MASK 0x0F |
||||
#define FPGA_REG3_STAT_LED8_ENAB 0x08 |
||||
#define FPGA_REG3_STAT_LED4_ENAB 0x04 |
||||
#define FPGA_REG3_STAT_LED2_ENAB 0x02 |
||||
#define FPGA_REG3_STAT_LED1_ENAB 0x01 |
||||
#define FPGA_REG3_STAT_LED8_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED4_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED2_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED1_DISAB 0x00 |
||||
#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) |
||||
#define FPGA_REG4_GPHY_MODE10 0x80 |
||||
#define FPGA_REG4_GPHY_MODE100 0x40 |
||||
#define FPGA_REG4_GPHY_MODE1000 0x20 |
||||
#define FPGA_REG4_GPHY_FRC_DPLX 0x10 |
||||
#define FPGA_REG4_GPHY_ANEG_DIS 0x08 |
||||
#define FPGA_REG4_CONNECT_PHYS 0x04 |
||||
|
||||
|
||||
#define SDR0_CUST0_ENET3_MASK 0x00000080 |
||||
#define SDR0_CUST0_ENET3_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET3_FIBER 0x00000080 |
||||
#define SDR0_CUST0_RGMII3_MASK 0x00000070 |
||||
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) |
||||
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) |
||||
#define SDR0_CUST0_RGMII3_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII3_RTBI 0x00000040 |
||||
#define SDR0_CUST0_RGMII3_RGMII 0x00000050 |
||||
#define SDR0_CUST0_RGMII3_TBI 0x00000060 |
||||
#define SDR0_CUST0_RGMII3_GMII 0x00000070 |
||||
#define SDR0_CUST0_ENET2_MASK 0x00000008 |
||||
#define SDR0_CUST0_ENET2_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET2_FIBER 0x00000008 |
||||
#define SDR0_CUST0_RGMII2_MASK 0x00000007 |
||||
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) |
||||
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) |
||||
#define SDR0_CUST0_RGMII2_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII2_RTBI 0x00000004 |
||||
#define SDR0_CUST0_RGMII2_RGMII 0x00000005 |
||||
#define SDR0_CUST0_RGMII2_TBI 0x00000006 |
||||
#define SDR0_CUST0_RGMII2_GMII 0x00000007 |
@ -0,0 +1,155 @@ |
||||
/* |
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/ocotea/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
cpu/ppc4xx/440gx_enet.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,144 @@ |
||||
/* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/ocotea/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
cpu/ppc4xx/440gx_enet.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* common/environment.o(.text) */ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,248 @@ |
||||
/*
|
||||
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com> |
||||
* Adapted to current Das U-Boot source |
||||
***********************************************************************/ |
||||
|
||||
|
||||
/************************************************************************
|
||||
* OCOTEA.h - configuration for IBM 440GX Ref (Ocotea) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_OCOTEA 1 /* Board is ebony */ |
||||
#define CONFIG_440_GX 1 /* Specifc GX support */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ |
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) |
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC |
||||
* |
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base |
||||
* address for the RTC registers is: |
||||
* |
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE |
||||
* |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ |
||||
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ |
||||
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
#define CFG_ENV_ADDR \ |
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " |
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
||||
#define CONFIG_BOOTDELAY -1 /* disable autoboot */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
||||
#define CONFIG_PHY1_ADDR 2 |
||||
#define CONFIG_PHY2_ADDR 0x10 |
||||
#define CONFIG_PHY3_ADDR 0x18 |
||||
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_IPADDR 10.1.2.3 |
||||
#define CONFIG_ETHADDR 00:04:AC:E3:28:8A |
||||
#define CONFIG_ETHADDR1 00:04:AC:E3:28:8B |
||||
#define CONFIG_ETHADDR2 00:04:AC:E3:28:8C |
||||
#define CONFIG_ETHADDR3 00:04:AC:E3:28:8D |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
#define CONFIG_SERVERIP 10.1.2.2 |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_ELF ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 100 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue