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/*
|
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ |
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#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */ |
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#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#define CONFIG_CPUCLOCK 66 |
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#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) |
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#define CONFIG_BAUDRATE 9600 |
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
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#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_PHY_ADDR 0 /* PHY address */ |
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#define CONFIG_IPADDR 10.0.18.222 |
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#define CONFIG_SERVERIP 10.0.18.190 |
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
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CFG_CMD_DHCP | \
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CFG_CMD_IRQ | \
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CFG_CMD_ELF | \
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CFG_CMD_ASKENV ) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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/* The following table includes the supported baudrates */ |
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#define CFG_BAUDRATE_TABLE \ |
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
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#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#define CFG_FLASH_BASE 0xFFFD0000 |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
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#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ |
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#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ |
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/*
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* The following defines are added for buggy IOP480 byte interface. |
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* All other boards should use the standard values (CPCI405 etc.) |
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*/ |
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#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ |
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#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ |
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#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ |
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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#if 1 /* Use NVRAM for environment variables */ |
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/*-----------------------------------------------------------------------
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* NVRAM organization |
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*/ |
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#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
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#define CFG_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */ |
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#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ |
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#define CFG_ENV_SIZE 0x0400 /* Size of Environment vars */ |
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#define CFG_ENV_ADDR \ |
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ |
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#define CFG_NVRAM_VXWORKS_OFFS 0x7800 /* Offset for VxWorks eth-addr */ |
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#else /* Use FLASH for environment variables */ |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ |
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ |
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#endif |
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/*-----------------------------------------------------------------------
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* PCI stuff |
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*/ |
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#define CONFIG_PCI /* include pci support */ |
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#undef CONFIG_PCI_PNP |
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
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#define CONFIG_TULIP |
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#define CFG_ETH_DEV_FN 0x0000 |
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#define CFG_ETH_IOBASE 0x0fff0000 |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ |
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#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */ |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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#endif /* __CONFIG_H */ |
@ -0,0 +1,287 @@ |
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/*
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* (C) Copyright 2002 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/************************************************************************
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* board/config_CPCI440.h - configuration for esd CPCI-440 board |
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***********************************************************************/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*-----------------------------------------------------------------------
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* High Level Configuration Options |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_EBONY 1 /* Board is ebony */ |
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#define CONFIG_4xx 1 /* ... PPC4xx family */ |
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#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
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#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the |
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* actual resources get mapped (not physical addresses) |
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*----------------------------------------------------------------------*/ |
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
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#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ |
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#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ |
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
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#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) |
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#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM) |
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*----------------------------------------------------------------------*/ |
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ |
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
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/*-----------------------------------------------------------------------
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* Serial Port |
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*----------------------------------------------------------------------*/ |
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#undef CONFIG_SERIAL_SOFTWARE_FIFO |
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#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ |
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#define CONFIG_BAUDRATE 9600 |
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#define CFG_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
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/*-----------------------------------------------------------------------
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* NVRAM/RTC |
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* |
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* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
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* The DS1743 code assumes this condition (i.e. -- it assumes the base |
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* address for the RTC registers is: |
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* |
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* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE |
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* |
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*----------------------------------------------------------------------*/ |
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#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
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#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
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/*-----------------------------------------------------------------------
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* FLASH related |
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*----------------------------------------------------------------------*/ |
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#if 1 /* test-only */ |
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#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ |
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#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ |
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
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#undef CFG_FLASH_BASE |
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#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ |
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#else /* test-only */ |
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#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
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#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ |
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#undef CFG_FLASH_CHECKSUM |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#endif |
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/*-----------------------------------------------------------------------
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* Environment |
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*----------------------------------------------------------------------*/ |
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#if 0 /* test-only */
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#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ |
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#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ |
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#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
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#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
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#define CFG_ENV_ADDR \ |
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) |
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#else |
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#if 0 /* test-only */
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
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#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ |
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#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ |
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/* total size of a CAT24WC16 is 2048 bytes */ |
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#else |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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#endif |
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment |
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*/ |
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#define CONFIG_HARD_I2C /* I2c with hardware support */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
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/* mask of address bits that overflow into the "EEPROM chip address" */ |
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
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/* 16 byte page write mode using*/ |
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/* last 4 bits of the address */ |
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
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#define CFG_EEPROM_PAGE_WRITE_ENABLE |
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#endif |
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#define CONFIG_BOOTARGS "root=/dev/hda1 " |
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#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
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#define CONFIG_BOOTDELAY -1 /* disable autoboot */ |
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#define CONFIG_BAUDRATE 9600 |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_PHY_ADDR 1 /* PHY address */ |
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#if 0 /* test-only */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
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CFG_CMD_IRQ | \
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CFG_CMD_I2C | \
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CFG_CMD_KGDB | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE | \
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CFG_CMD_BEDBUG | \
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CFG_CMD_ELF ) |
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#else |
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
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CFG_CMD_IRQ | \
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CFG_CMD_ELF | \
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CFG_CMD_DATE | \
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CFG_CMD_I2C | \
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CFG_CMD_EEPROM ) |
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/* test-only: support fehlt bisher... */ |
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/* CFG_CMD_IDE | \*/ |
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/* CFG_CMD_PCI | \*/ |
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#endif |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#if 0 /* test-only */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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#endif |
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/*-----------------------------------------------------------------------
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* PCI stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#if 0 |
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
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#define PCI_HOST_FORCE 1 /* configure as pci host */ |
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
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#define CONFIG_PCI /* include pci support */ |
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
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#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
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/* resource configuration */ |
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
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#endif |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
/* Configuration Port location */ |
||||
#define CONFIG_PORT_ADDR 0xF0000500 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,654 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_CPU86 1 /* ...on a CPU86 board */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
||||
#define CONFIG_BAUDRATE 230400 |
||||
#else |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#endif |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
* |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK11 |
||||
* - Tx-CLK is CLK12 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 64000000 /* in Hz */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT \ |
||||
"echo; " \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C/EEPROM/RTC configuration |
||||
*/ |
||||
#define CONFIG_SOFT_I2C /* Software I2C support enabled */ |
||||
|
||||
# define CFG_I2C_SPEED 50000 |
||||
# define CFG_I2C_SLAVE 0xFE |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CONFIG_RTC_PCF8563 |
||||
#define CFG_I2C_RTC_ADDR 0x51 |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Disk-On-Chip configuration |
||||
*/ |
||||
|
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
|
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#define CFG_DOC_SUPPORT_MILLENNIUM |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configuration options |
||||
*/ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DOC) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash configuration |
||||
*/ |
||||
|
||||
#define CFG_BOOTROM_BASE 0xFF800000 |
||||
#define CFG_BOOTROM_SIZE 0x00080000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#define CFG_FLASH_SIZE 0x00800000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Other areas to be mapped |
||||
*/ |
||||
|
||||
/* CS3: Dual ported SRAM */ |
||||
#define CFG_DPSRAM_BASE 0x40000000 |
||||
#define CFG_DPSRAM_SIZE 0x00020000 |
||||
|
||||
/* CS4: DiskOnChip */ |
||||
#define CFG_DOC_BASE 0xF4000000 |
||||
#define CFG_DOC_SIZE 0x00100000 |
||||
|
||||
/* CS5: FDC37C78 controller */ |
||||
#define CFG_FDC37C78_BASE 0xF1000000 |
||||
#define CFG_FDC37C78_SIZE 0x00100000 |
||||
|
||||
/* CS6: Board configuration registers */ |
||||
#define CFG_BCRS_BASE 0xF2000000 |
||||
#define CFG_BCRS_SIZE 0x00010000 |
||||
|
||||
/* CS7: VME Extended Access Range */ |
||||
#define CFG_VMEEAR_BASE 0x80000000 |
||||
#define CFG_VMEEAR_SIZE 0x01000000 |
||||
|
||||
/* CS8: VME Standard Access Range */ |
||||
#define CFG_VMESAR_BASE 0xFE000000 |
||||
#define CFG_VMESAR_SIZE 0x01000000 |
||||
|
||||
/* CS9: VME Short I/O Access Range */ |
||||
#define CFG_VMESIOAR_BASE 0xFD000000 |
||||
#define CFG_VMESIOAR_SIZE 0x01000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#if defined(CONFIG_BOOT_ROM) |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ |
||||
HRCW_BPS01 | HRCW_CS10PC01) |
||||
#else |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) |
||||
#endif |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#if 0 |
||||
/* environment is in Flash */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#ifdef CONFIG_BOOT_ROM |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) |
||||
# define CFG_ENV_SIZE 0x10000 |
||||
# define CFG_ENV_SECT_SIZE 0x10000 |
||||
#endif |
||||
#else |
||||
/* environment is in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ |
||||
HID0_DCI|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ |
||||
SIUMCR_CS10PC01|SIUMCR_BCTLC10) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR SCCR_DFBRG01 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
#define CFG_MIN_AM_MASK 0xC0000000 |
||||
/*-----------------------------------------------------------------------
|
||||
* MPTPR - Memory Refresh Timer Prescaler Register 10-18 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MPTPR 0x1F00 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PSRT - Refresh Timer Register 10-16 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_PSRT 0x0f |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PSRT - SDRAM Mode Register 10-10 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
||||
PSDMR_BSMA_A14_A16 |\
|
||||
PSDMR_SDA10_PBI0_A10 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A7 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI0_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 8 bit Boot ROM |
||||
* 1 60x GPCM 64 bit FLASH |
||||
* 2 60x SDRAM 64 bit SDRAM |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_MRS_OFFS 0x00000000 |
||||
|
||||
#ifdef CONFIG_BOOT_ROM |
||||
/* Bank 0 - Boot ROM
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
/* Bank 1 - FLASH
|
||||
*/ |
||||
#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
#else /* CONFIG_BOOT_ROM */ |
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
/* Bank 1 - Boot ROM
|
||||
*/ |
||||
#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
#endif /* CONFIG_BOOT_ROM */ |
||||
|
||||
|
||||
/* Bank 2 - 60x bus SDRAM
|
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_9COL |
||||
|
||||
#define CFG_PSDMR CFG_PSDMR_9COL |
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
/* Bank 3 - Dual Ported SRAM
|
||||
*/ |
||||
#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_SETA) |
||||
|
||||
/* Bank 4 - DiskOnChip
|
||||
*/ |
||||
#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ |
||||
ORxG_ACS_DIV2 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
/* Bank 5 - FDC37C78 controller
|
||||
*/ |
||||
#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ |
||||
ORxG_ACS_DIV2 |\
|
||||
ORxG_SCY_8_CLK |\
|
||||
ORxU_EHTR_8IDLE) |
||||
|
||||
/* Bank 6 - Board control registers
|
||||
*/ |
||||
#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_SCY_5_CLK) |
||||
|
||||
/* Bank 7 - VME Extended Access Range
|
||||
*/ |
||||
#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_SETA) |
||||
|
||||
/* Bank 8 - VME Standard Access Range
|
||||
*/ |
||||
#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_SETA) |
||||
|
||||
/* Bank 9 - VME Short I/O Access Range
|
||||
*/ |
||||
#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_SETA) |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */ |
||||
#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_CPUCLOCK 66 |
||||
#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK) |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_IPADDR 10.0.18.222 |
||||
#define CONFIG_SERVERIP 10.0.18.190 |
||||
|
||||
#if 0 |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_ELF ) |
||||
#else |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_BSP ) |
||||
#endif |
||||
|
||||
#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
|
||||
#define CONFIG_SOFT_I2C /* Software I2C support enabled */ |
||||
#endif |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFFD0000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 128 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
||||
#define CFG_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */ |
||||
#define CFG_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CFG_FLASH_READ0 0x0002 /* 0 is standard */ |
||||
#define CFG_FLASH_READ1 0x0000 /* 1 is standard */ |
||||
#define CFG_FLASH_READ2 0x0004 /* 2 is standard */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
|
||||
#if 0 |
||||
#define CFG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */ |
||||
#else |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*/ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#undef CONFIG_PCI_PNP |
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
|
||||
#define CONFIG_TULIP |
||||
|
||||
#define CFG_ETH_DEV_FN 0x0000 |
||||
#define CFG_ETH_IOBASE 0x0fff0000 |
||||
#define CFG_PCI9054_DEV_FN 0x0800 |
||||
#define CFG_PCI9054_IOBASE 0x0eff0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ |
||||
#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */ |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,322 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
||||
#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */ |
||||
|
||||
#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */ |
||||
#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */ |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \ |
||||
"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 " |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 8 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
||||
|
||||
/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
/*#define CFG_DER 0x02002000 */ |
||||
|
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH 0x00000160 |
||||
/*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
|
||||
OR_SCY_5_CLK | OR_EHTR) */ |
||||
|
||||
#define CFG_OR0_REMAP 0x80000160 /*(CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)*/ |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 ) |
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CFG_OR2_PRELIM 0xFC000E00 |
||||
#define CFG_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081) |
||||
|
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM |
||||
#define CFG_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL 0x18803112 |
||||
#define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ |
||||
|
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,422 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T FADS board. Copied from the MBX stuff. |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/*
|
||||
* 1999-nov-26: The FADS is using the following physical memorymap: |
||||
* |
||||
* ff020000 -> ff02ffff : pcmcia |
||||
* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom |
||||
* ff000000 -> ff00ffff : IMAP internal in the cpu |
||||
* fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom |
||||
* 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#include <mpc8xx_irq.h> |
||||
|
||||
#define CONFIG_MPC850 1 |
||||
#define CONFIG_MPC850SAR 1 |
||||
#define CONFIG_FADS 1 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#if 0 |
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 50000000 /* 50 MHz in */ |
||||
#else |
||||
#define MPC8XX_FACT 12 /* Multiply by 12 */ |
||||
#define MPC8XX_XIN 4000000 /* 4 MHz in */ |
||||
#endif |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS " " |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT ":>" /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* Also NOTE that it doesn't mean SDRAM - it means MEMORY. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x02800000 |
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
#if 0 |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer * |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
|
||||
#define BCSR_ADDR ((uint) 0x02100000) |
||||
#define BCSR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */ |
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/* BCSRx - Board Control and Status Registers */ |
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */ |
||||
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V ) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CFG_MAMR 0x13a01114 |
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/* values according to the manual */ |
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description |
||||
* of the following structures |
||||
*/ |
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000) |
||||
#define BCSR0_IP ((uint)0x40000000) |
||||
#define BCSR0_BDIS ((uint)0x10000000) |
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000) |
||||
#define BCSR0_ISB_MASK ((uint)0x01800000) |
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000) |
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000) |
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000) |
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000) |
||||
#define BCSR1_DRAM_EN ((uint)0x40000000) |
||||
#define BCSR1_ETHEN ((uint)0x20000000) |
||||
#define BCSR1_IRDEN ((uint)0x10000000) |
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
||||
#define BCSR1_BCSR_EN ((uint)0x02000000) |
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000) |
||||
#define BCSR1_PCCEN ((uint)0x00800000) |
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000) |
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000) |
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000) |
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000) |
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT (23) |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG0 ((uint)0x04000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHFDE ((uint)0x02000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHCFG1 ((uint)0x00400000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETHRST ((uint)0x00200000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
|
||||
#define CONFIG_DRAM_50MHZ 1 |
||||
#define CONFIG_SDRAM_50MHZ |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/* Machine type
|
||||
*/ |
||||
#define _MACH_8xx (_MACH_fads) |
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,302 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */ |
||||
#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/ |
||||
|
||||
#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ |
||||
#define CONFIG_8xx_CONS_SMC2 1 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp" |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram ip=off panic=1;" \
|
||||
"bootm 40040000 400e0000" |
||||
#else |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1" |
||||
#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000" |
||||
#endif /* 0|1*/ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \ |
||||
CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
|
||||
CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x40040000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
/* This is a litlebit wasteful, but one sector is 128kb and we have to
|
||||
* assigne a whole sector for the environment, so that we can safely |
||||
* erase and write it without disturbing the boot sector |
||||
*/ |
||||
#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#ifdef CONFIG_WATCHDOG |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \ |
||||
SIUMCR_MLRC01 | SIUMCR_GB5E) |
||||
#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit miltiplier of 0x00b i.e. operation clock is |
||||
* 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz |
||||
*/ |
||||
#define CFG_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* In the Flaga DM we have: |
||||
* Flash on BR0/OR0/CS0a at 0x40000000 |
||||
* Display on BR1/OR1/CS1 at 0x20000000 |
||||
* SDRAM on BR2/OR2/CS2 at 0x00000000 |
||||
* Free BR3/OR3/CS3 |
||||
* DSP1 on BR4/OR4/CS4 at 0x80000000 |
||||
* DSP2 on BR5/OR5/CS5 at 0xa0000000 |
||||
* |
||||
* For now we just configure the Flash and the SDRAM and leave the others |
||||
* untouched. |
||||
*/ |
||||
|
||||
#define CFG_FLASH_PROTECTION 0 |
||||
|
||||
#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_OR_AM 0xff000000 /* OR addr mask */ |
||||
#define CFG_OR_ATM 0x00006000 |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \ |
||||
OR_SCY_3_CLK | OR_TRLX | OR_EHTR ) |
||||
|
||||
#define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* BR2 and OR2 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM ( 0x00000800 ) |
||||
|
||||
#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#define CFG_BR2 CFG_BR2_PRELIM |
||||
#define CFG_OR2 CFG_OR2_PRELIM |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \ |
||||
| MAMR_G0CLA_A11) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 0x0F000000 |
||||
|
||||
/*
|
||||
* BR4 and OR4 (DSP1) |
||||
* |
||||
* We do not wan't preliminary setup of the DSP, anyway we need the |
||||
* UPMB setup correctly before we can access the DSP. |
||||
* |
||||
*/ |
||||
#define DSP_BASE 0x80000000 |
||||
|
||||
#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS) |
||||
#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V ) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,374 @@ |
||||
/*
|
||||
* Parameters for GTH board |
||||
* Based on FADS860T |
||||
* by thomas.lange@corelatus.com |
||||
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T FADS board. Copied from the MBX stuff. |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/*
|
||||
* ff000000 -> ff00ffff : IMAP internal in the cpu |
||||
* e0000000 -> ennnnnnn : pcmcia |
||||
* 98000000 -> 983nnnnn : FPGA 4MB |
||||
* 90000000 -> 903nnnnn : FPGA 4MB |
||||
* 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location |
||||
* 00000000 -> nnnnnnnn : sdram |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#include <mpc8xx_irq.h> |
||||
|
||||
#define CONFIG_MPC860 1 |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_GTH 1 |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
|
||||
#define MPC8XX_FACT 3 /* Multiply by 3 */ |
||||
#define MPC8XX_XIN 16384000 /* 16.384 MHz */ |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ |
||||
|
||||
#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ |
||||
|
||||
#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ |
||||
|
||||
/* Only interrupt boot if space is pressed */ |
||||
/* If a long serial cable is connected but */ |
||||
/* other end is dead, garbage will be read */ |
||||
#define CONFIG_AUTOBOOT_KEYED 1 |
||||
#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" |
||||
#define CONFIG_AUTOBOOT_DELAY_STR "d" |
||||
#define CONFIG_AUTOBOOT_STOP_STR " " |
||||
|
||||
#if 0 |
||||
/* Net boot */ |
||||
/* Loads a tftp image and starts it */ |
||||
#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "panic=1" |
||||
#else |
||||
/* Compact flash boot */ |
||||
#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7" |
||||
#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000" |
||||
#endif |
||||
|
||||
/* Enable watchdog */ |
||||
#define CONFIG_WATCHDOG 1 |
||||
|
||||
/* choose SCC1 ethernet (10BASET on motherboard)
|
||||
* or FEC ethernet (10/100 on daughterboard) |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ |
||||
#undef CONFIG_FEC_ENET /* disable FEC ethernet */ |
||||
#define CFG_DISCOVER_PHY |
||||
#else |
||||
#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ |
||||
#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
||||
#define CFG_DISCOVER_PHY |
||||
#endif |
||||
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) |
||||
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured |
||||
#endif |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_PROMPT "=>" /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
||||
|
||||
/* Default location to load data from net */ |
||||
#define CFG_LOAD_ADDR 0x100000 |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
|
||||
#define CFG_FLASH_BASE 0x80000000 |
||||
|
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
|
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
|
||||
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#undef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_ENV_OFFSET 0x000E0000 |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
/*FIXME dont use for now */ |
||||
/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
||||
/*#define CFG_RTCSC (RTCSC_RTF) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
/* PITE */ |
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set the PLL, the low-power modes and the reset control (15-29) |
||||
*/ |
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
|
||||
/* FIXME check values */ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
|
||||
#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
||||
|
||||
#define FPGA_2_BASE 0x90000000 |
||||
#define FPGA_3_BASE 0x98000000 |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
|
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 ) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */ |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/* Machine type
|
||||
*/ |
||||
#define _MACH_8xx (_MACH_gth) |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ |
||||
|
||||
#define PA_FRONT_LED ((u16)0x4) /* PA 13 */ |
||||
#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */ |
||||
#define PA_FL_CE ((u16)0x1000) /* PA 3 */ |
||||
|
||||
#define PB_ID_GND ((u32)1) /* PB 31 */ |
||||
#define PB_REV_1 ((u32)2) /* PB 30 */ |
||||
#define PB_REV_0 ((u32)4) /* PB 29 */ |
||||
#define PB_BLUE_LED ((u32)0x400) /* PB 21 */ |
||||
#define PB_EEPROM ((u32)0x800) /* PB 20 */ |
||||
#define PB_ID_3 ((u32)0x2000) /* PB 18 */ |
||||
#define PB_ID_2 ((u32)0x4000) /* PB 17 */ |
||||
#define PB_ID_1 ((u32)0x8000) /* PB 16 */ |
||||
#define PB_ID_0 ((u32)0x10000) /* PB 15 */ |
||||
|
||||
/* NOTE. This is reset for 100Mbit port only */ |
||||
#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,378 @@ |
||||
/*
|
||||
* (C) Copyright 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <mpc8xx_irq.h> |
||||
|
||||
|
||||
# ifdef DEBUG |
||||
# warning DEBUG Defined |
||||
# endif /* DEBUG */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MPC860 1 |
||||
#define CONFIG_IAD210 1 /* ...on a IAD210 module */ |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_MPC862 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
|
||||
#undef CONFIG_8xx_CONS_SMC1 |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
|
||||
# define MPC8XX_FACT 16 |
||||
# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ |
||||
# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 0 |
||||
# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
/* using this define saves us updating another source file */ |
||||
#define CONFIG_BOARD_PRE_INIT 1 |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
/* #define CONFIG_BOOTCOMMAND \
|
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm" |
||||
*/ |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs" \
|
||||
"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ |
||||
# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ |
||||
# define CFG_DISCOVER_PHY 1 |
||||
# define CONFIG_FEC_UTOPIA 1 |
||||
# define CONFIG_ETHADDR 08:00:06:26:A2:6D |
||||
# define CONFIG_IPADDR 192.168.28.128 |
||||
# define CONFIG_SERVERIP 139.10.137.138 |
||||
# define CFG_DISCOVER_PHY 1 |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
# define CFG_I2C_SPEED 50000 |
||||
# define CFG_I2C_SLAVE 0xDD |
||||
# define CFG_I2C_EEPROM_ADDR 0x50 |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL 0x00000020 /* PB 26 */ |
||||
#define PB_SDA 0x00000010 /* PB 27 */ |
||||
|
||||
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
||||
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
||||
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
||||
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SDA |
||||
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
||||
else immr->im_cpm.cp_pbdat &= ~PB_SCL |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x08000000 |
||||
#define CFG_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 |
||||
|
||||
#if defined(DEBUG) |
||||
# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
|
||||
# define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
# define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set the PLL, the low-power modes and the reset control (15-29) |
||||
*/ |
||||
#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
|
||||
#define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ |
||||
SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
|
||||
SCCR_DFLCD000 |SCCR_DFALCD00 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ |
||||
#define CFG_RCCR 0x0020 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0 and OR0 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0xF8000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing:
|
||||
TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ |
||||
OR_SCY_3_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 124 /* start with divider for 64 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLB_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,475 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_IVML24 1 /* ...on a IVML24 board */ |
||||
|
||||
#if defined (CONFIG_IVML24_16M) |
||||
# define CONFIG_IDENT_STRING " IVML24" |
||||
#elif defined (CONFIG_IVML24_32M) |
||||
# define CONFIG_IDENT_STRING " IVML24_128" |
||||
#elif defined (CONFIG_IVML24_64M) |
||||
# define CONFIG_IDENT_STRING " IVML24_256" |
||||
#endif |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ 50331648 |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_BOOTP_MASK \ |
||||
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
#define CFG_PB_12V_ENABLE 0x00002000 /* PB 18 */ |
||||
#define CFG_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ |
||||
#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ |
||||
#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ |
||||
#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ |
||||
|
||||
#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ |
||||
#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
|
||||
#if defined (CONFIG_IVML24_16M) |
||||
# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#elif defined (CONFIG_IVML24_32M) |
||||
# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
||||
#elif defined (CONFIG_IVML24_64M) |
||||
# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
||||
#endif |
||||
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
|
||||
# if defined (CONFIG_IVML24_16M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
# elif defined (CONFIG_IVML24_32M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWP) |
||||
# elif defined (CONFIG_IVML24_64M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWP) |
||||
# endif |
||||
|
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* EARB, DBGC and DBPC are initialised by the HCW */ |
||||
/* => 0x000000C0 */ |
||||
#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* 0x00B0C0C0 */ |
||||
#define CFG_PLPRCR \ |
||||
( (11 << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
/* 0x01800014 */ |
||||
#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD101 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* 0x00C3 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* TIMEP=2 */ |
||||
#define CFG_RCCR 0x0200 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
* Interrupt Levels |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ |
||||
#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xFE100000 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0 and OR0 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
/* EPROMs are 512kb */ |
||||
#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* BR1/OR1 - ELIC SACCO bank @ 0xFE000000 |
||||
* |
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 |
||||
*/ |
||||
#define ELIC_SACCO_BASE 0xFE000000 |
||||
#define ELIC_SACCO_OR_AM 0xFFFF8000 |
||||
#define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) |
||||
|
||||
#define CFG_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
||||
ELIC_SACCO_TIMING) |
||||
#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/OR2 - ELIC EPIC bank @ 0xFE008000 |
||||
* |
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 |
||||
*/ |
||||
#define ELIC_EPIC_BASE 0xFE008000 |
||||
#define ELIC_EPIC_OR_AM 0xFFFF8000 |
||||
#define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) |
||||
|
||||
#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
||||
ELIC_EPIC_TIMING) |
||||
#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR3/OR3: SDRAM |
||||
* |
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care) |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
||||
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
||||
|
||||
#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) |
||||
|
||||
/*
|
||||
* BR4/OR4 - HDLC Address |
||||
* |
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 |
||||
*/ |
||||
#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ |
||||
#define HDLC_ADDR_OR_AM 0xFFFF8000 |
||||
#define HDLC_ADDR_TIMING OR_SCY_1_CLK |
||||
|
||||
#define CFG_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) |
||||
#define CFG_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) |
||||
|
||||
/*
|
||||
* BR5/OR5: SHARC ADSP-2165L |
||||
* |
||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 |
||||
*/ |
||||
#define SHARC_BASE 0xFE400000 |
||||
#define SHARC_OR_AM 0xFFC00000 |
||||
#define SHARC_TIMING OR_SCY_0_CLK |
||||
|
||||
#define CFG_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) |
||||
#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTB 204 |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
|
||||
#if defined (CONFIG_IVML24_16M) |
||||
# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
#elif defined (CONFIG_IVML24_32M) |
||||
# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
#elif defined (CONFIG_IVML24_64M) |
||||
# define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM |
||||
*/ |
||||
|
||||
#if defined (CONFIG_IVML24_16M) |
||||
/* 8 column SDRAM */ |
||||
# define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
#elif defined (CONFIG_IVML24_32M) |
||||
/* 128 MBit SDRAM */ |
||||
# define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
#elif defined (CONFIG_IVML24_64M) |
||||
/* 128 MBit SDRAM */ |
||||
# define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,459 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
||||
#define CONFIG_IVMS8 1 /* ...on a IVMS8 board */ |
||||
|
||||
#if defined (CONFIG_IVMS8_16M) |
||||
# define CONFIG_IDENT_STRING " IVMS8" |
||||
#elif defined (CONFIG_IVMS8_32M) |
||||
# define CONFIG_IDENT_STRING " IVMS8_128" |
||||
#elif defined (CONFIG_IVMS8_64M) |
||||
# define CONFIG_IDENT_STRING " IVMS8_256" |
||||
#endif |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ 50331648 |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_BOOTP_MASK \ |
||||
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
#define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ |
||||
#define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ |
||||
#define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */ |
||||
|
||||
#define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ |
||||
#define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#if defined (CONFIG_IVMS8_16M) |
||||
# define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#elif defined (CONFIG_IVMS8_32M) |
||||
# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
||||
#elif defined (CONFIG_IVMS8_64M) |
||||
# define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ |
||||
#endif |
||||
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
# if defined (CONFIG_IVMS8_16M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
# elif defined (CONFIG_IVMS8_32M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWP) |
||||
# elif defined (CONFIG_IVMS8_64M) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWP) |
||||
# endif |
||||
#else |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* EARB, DBGC and DBPC are initialised by the HCW */ |
||||
/* => 0x000000C0 */ |
||||
#define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* 0x00B0C0C0 */ |
||||
#define CFG_PLPRCR \ |
||||
( (11 << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
/* 0x01800014 */ |
||||
#define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD101 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* 0x00C3 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* TIMEP=2 */ |
||||
#define CFG_RCCR 0x0200 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
* Interrupt Levels |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* The IVMS8 has only 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xFE100000 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */ |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0 and OR0 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
/* EPROMs are 512kb */ |
||||
#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ |
||||
OR_SCY_5_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* BR1/OR1 - ELIC SACCO bank @ 0xFE000000 |
||||
* |
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 |
||||
*/ |
||||
#define ELIC_SACCO_BASE 0xFE000000 |
||||
#define ELIC_SACCO_OR_AM 0xFFFF8000 |
||||
#define ELIC_SACCO_TIMING 0x00000F26 |
||||
|
||||
#define CFG_OR1 (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING) |
||||
#define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/OR2 - ELIC EPIC bank @ 0xFE008000 |
||||
* |
||||
* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 |
||||
*/ |
||||
#define ELIC_EPIC_BASE 0xFE008000 |
||||
#define ELIC_EPIC_OR_AM 0xFFFF8000 |
||||
#define ELIC_EPIC_TIMING 0x00000F26 |
||||
|
||||
#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING) |
||||
#define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR3/OR3: SDRAM |
||||
* |
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care) |
||||
*/ |
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
||||
#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
||||
|
||||
#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) |
||||
|
||||
/*
|
||||
* BR4/OR4: not used |
||||
*/ |
||||
|
||||
/*
|
||||
* BR5/OR5: SHARC ADSP-2165L |
||||
* |
||||
* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 |
||||
*/ |
||||
#define SHARC_BASE 0xFE400000 |
||||
#define SHARC_OR_AM 0xFFC00000 |
||||
#define SHARC_TIMING 0x00000700 |
||||
|
||||
#define CFG_OR5 (SHARC_OR_AM | SHARC_TIMING ) |
||||
#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTB 204 |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#if defined (CONFIG_IVMS8_16M) |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
#elif defined (CONFIG_IVMS8_32M) |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
#elif defined (CONFIG_IVMS8_64M) |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM |
||||
*/ |
||||
|
||||
#if defined (CONFIG_IVMS8_16M) |
||||
/* 8 column SDRAM */ |
||||
# define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
#elif defined (CONFIG_IVMS8_32M) |
||||
/* 128 MBit SDRAM */ |
||||
#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
#elif defined (CONFIG_IVMS8_64M) |
||||
/* 128 MBit SDRAM */ |
||||
#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,407 @@ |
||||
/*
|
||||
* A collection of structures, addresses, and values associated with |
||||
* the Motorola 860T MBX board. |
||||
* Copied from the FADS stuff, which was originally copied from the MBX stuff! |
||||
* Magnus Damm added defines for 8xxrom and extended bd_info. |
||||
* Helmut Buchsbaum added bitvalues for BCSRx |
||||
* Rob Taylor coverted it back to MBX |
||||
* |
||||
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net) |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#include <mpc8xx_irq.h> |
||||
|
||||
#define CONFIG_MPC860 1 |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_MBX 1 |
||||
|
||||
#define CONFIG_8xx_CPUCLOCK 40 |
||||
#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK) |
||||
#define TARGET_SYSTEM_FREQUENCY 40 |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define MPC8XX_FACT 10 /* Multiply by 10 */ |
||||
#define MPC8XX_XIN 40000000 /* 50 MHz in */ |
||||
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */ |
||||
#define CONFIG_8xx_TFTP_MODE |
||||
#else |
||||
#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#undef CONFIG_8xx_TFTP_MODE |
||||
#endif |
||||
|
||||
#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */ |
||||
#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS " " |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#undef CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT ":>" /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFA00000 |
||||
#define CFG_IMMR_SIZE ((uint)(64 * 1024)) |
||||
#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */ |
||||
#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */ |
||||
#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */ |
||||
#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */ |
||||
#define CFG_PCIMEM_OR 0xA0000108 |
||||
#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */ |
||||
#define CFG_PCIBRIDGE_OR 0xFFFF0108 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */ |
||||
#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE) |
||||
#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Offset in DPMEM where we keep the VPD data |
||||
*/ |
||||
#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x00000000 |
||||
/*0xFE000000*/ |
||||
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN) |
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration |
||||
* |
||||
* Note: the MBX is special because there is already a firmware on this |
||||
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we |
||||
* access the NVRAM at the offset 0x1000. |
||||
*/ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */ |
||||
#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000) |
||||
#define CFG_ENV_SIZE 0x1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) |
||||
#define CFG_SCCR SCCR_TBS |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller |
||||
* differently. Normally, you write the option register |
||||
* first, and then enable the chip select by writing the |
||||
* base register. For CS0, you must write the base register |
||||
* first, followed by the option register. |
||||
*/ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
/* the other CS:s are determined by looking at parameters in BCSRx */ |
||||
|
||||
|
||||
#define BCSR_ADDR ((uint) 0xFF010000) |
||||
#define BCSR_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */ |
||||
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ |
||||
#define CFG_BR0_PRELIM (0xFE000000 | BR_V ) |
||||
|
||||
/* BCSRx - Board Control and Status Registers */ |
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4 |
||||
#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V ) |
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
#define CFG_MAMR 0x13821000 |
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/* values according to the manual */ |
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000) |
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00)) |
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04)) |
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08)) |
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c)) |
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10)) |
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description |
||||
* of the following structures |
||||
*/ |
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000) |
||||
#define BCSR0_IP ((uint)0x40000000) |
||||
#define BCSR0_BDIS ((uint)0x10000000) |
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000) |
||||
#define BCSR0_ISB_MASK ((uint)0x01800000) |
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000) |
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000) |
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000) |
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000) |
||||
#define BCSR1_DRAM_EN ((uint)0x40000000) |
||||
#define BCSR1_ETHEN ((uint)0x20000000) |
||||
#define BCSR1_IRDEN ((uint)0x10000000) |
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000) |
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000) |
||||
#define BCSR1_BCSR_EN ((uint)0x02000000) |
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000) |
||||
#define BCSR1_PCCEN ((uint)0x00800000) |
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000) |
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000) |
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000) |
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000) |
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000) |
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000) |
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000) |
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000) |
||||
#define BCSR2_DRAM_PD_SHIFT (23) |
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000) |
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000) |
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800) |
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400) |
||||
#define BCSR3_BREVNR0 ((ushort)0x0080) |
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070) |
||||
#define BCSR3_BREVN1 ((ushort)0x0008) |
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003) |
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000) |
||||
#define BCSR4_TFPLDL ((uint)0x40000000) |
||||
#define BCSR4_TPSQEL ((uint)0x20000000) |
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000) |
||||
#ifdef CONFIG_MPC823 |
||||
#define BCSR4_USB_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC823 */ |
||||
#ifdef CONFIG_MPC860SAR |
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860SAR */ |
||||
#ifdef CONFIG_MPC860T |
||||
#define BCSR4_FETH_EN ((uint)0x08000000) |
||||
#endif /* CONFIG_MPC860T */ |
||||
#define BCSR4_USB_SPEED ((uint)0x04000000) |
||||
#define BCSR4_VCCO ((uint)0x02000000) |
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000) |
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000) |
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000) |
||||
#define BCSR4_MODEM_EN ((uint)0x00100000) |
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000) |
||||
|
||||
#define CONFIG_DRAM_40MHZ 1 |
||||
|
||||
#ifdef CONFIG_MPC860T |
||||
|
||||
/* Interrupt level assignments.
|
||||
*/ |
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ |
||||
|
||||
#endif /* CONFIG_MPC860T */ |
||||
|
||||
/* We don't use the 8259.
|
||||
*/ |
||||
#define NR_8259_INTS 0 |
||||
|
||||
/* Machine type
|
||||
*/ |
||||
#define _MACH_8xx (_MACH_fads) |
||||
|
||||
/*
|
||||
* MPC8xx CPM Options |
||||
*/ |
||||
#define CONFIG_SCC_ENET 1 |
||||
#define CONFIG_SCC1_ENET 1 |
||||
#define CONFIG_FEC_ENET 1 |
||||
#undef CONFIG_CPM_IIC |
||||
#undef CONFIG_UCODE_PATCH |
||||
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000 |
||||
|
||||
|
||||
/* PCMCIA configuration */ |
||||
|
||||
#define PCMCIA_MAX_SLOTS 2 |
||||
|
||||
#ifdef CONFIG_MPC860 |
||||
#define PCMCIA_SLOT_A 1 |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,525 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef CFG_RAMBOOT |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
||||
#define CONFIG_PM826 1 /* ...on a PM8260 module */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
# define CFG_I2C_SPEED 50000 |
||||
# define CFG_I2C_SLAVE 0xFE |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
|
||||
#define CONFIG_RTC_PCF8563 |
||||
#define CFG_I2C_RTC_ADDR 0x51 |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 1) |
||||
/*
|
||||
* - Rx-CLK is CLK11 |
||||
* - Tx-CLK is CLK10 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 64000000 /* in Hz */ |
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
||||
#define CONFIG_BAUDRATE 230400 |
||||
#else |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DOC) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Disk-On-Chip configuration |
||||
*/ |
||||
|
||||
#define CFG_DOC_SHORT_TIMEOUT |
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
|
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#define CFG_DOC_SUPPORT_MILLENNIUM |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash and Boot ROM mapping |
||||
*/ |
||||
|
||||
#define CFG_BOOTROM_BASE 0x60000000 |
||||
#define CFG_BOOTROM_SIZE 0x00080000 |
||||
#define CFG_FLASH0_BASE 0x40000000 |
||||
#define CFG_FLASH0_SIZE 0x02000000 |
||||
#define CFG_DOC_BASE 0x60000000 |
||||
#define CFG_DOC_SIZE 0x00100000 |
||||
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/ |
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#if 0 |
||||
/* Start port with environment in flash; switch to EEPROM later */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
||||
#define CFG_ENV_SIZE 0x40000 |
||||
#define CFG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
/* Final version: environment in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_I2C_EEPROM_ADDR 0x58 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#if defined(CONFIG_BOOT_ROM) |
||||
#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
||||
#else |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
||||
#endif |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM |
||||
* is mapped at SDRAM_BASE2_PRELIM. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if 0 |
||||
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) |
||||
#else |
||||
#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SCCR (SCCR_DFBRG01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 64 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
* 2 Local SDRAM 32 bit SDRAM |
||||
* |
||||
*/ |
||||
|
||||
/* Initialize SDRAM on local bus
|
||||
*/ |
||||
#define CFG_INIT_LOCAL_SDRAM |
||||
|
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2] |
||||
*/ |
||||
#define CFG_MIN_AM_MASK 0xC0000000 |
||||
|
||||
#define CFG_MPTPR 0x1F00 |
||||
|
||||
#define CFG_MRS_OFFS 0x00000000 |
||||
|
||||
|
||||
#if defined(CONFIG_BOOT_ROM) |
||||
/*
|
||||
* Bank 0 - Boot ROM (8 bit wide) |
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
/*
|
||||
* Bank 1 - Flash (64 bit wide) |
||||
*/ |
||||
#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
#else /* ! CONFIG_BOOT_ROM */ |
||||
|
||||
/*
|
||||
* Bank 0 - Flash (64 bit wide) |
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
/*
|
||||
* Bank 1 - Disk-On-Chip |
||||
*/ |
||||
#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
#endif /* CONFIG_BOOT_ROM */ |
||||
|
||||
/* Bank 2 - SDRAM
|
||||
*/ |
||||
#define CFG_PSRT 0x0F |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
||||
PSDMR_BSMA_A14_A16 |\
|
||||
PSDMR_SDA10_PBI0_A10 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A7 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI0_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_1W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_9COL |
||||
#define CFG_PSDMR CFG_PSDMR_9COL |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,711 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
||||
#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ |
||||
#define CONFIG_SCM 1 /* ...on a System Controller Module */ |
||||
|
||||
#if (CONFIG_TQM8260 <= 100) |
||||
# error "TQM8260 module revison not supported" |
||||
#endif |
||||
|
||||
/* We use a TQM8260 module with a 300MHz CPU */ |
||||
#define CONFIG_300MHz |
||||
|
||||
/* Define 60x busmode only if your TQM8260 has L2 cache! */ |
||||
#ifdef CONFIG_L2_CACHE |
||||
# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ |
||||
#else |
||||
# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ |
||||
#endif |
||||
|
||||
/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ |
||||
#ifdef CONFIG_300MHz |
||||
# define CONFIG_BUSMODE_60x |
||||
#endif |
||||
|
||||
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
#define CONFIG_I2C_X |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#ifdef CONFIG_82xx_CONS_SMC1 |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
#endif |
||||
#ifdef CONFIG_82xx_CONS_SMC2 |
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ |
||||
#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ |
||||
#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
* |
||||
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the |
||||
* X.29 connector, and FCC2 is hardwired to the X.1 connector) |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK12 |
||||
* - Tx-CLK is CLK11 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK15 |
||||
* - Tx-CLK is CLK16 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#ifndef CONFIG_300MHz |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#else |
||||
#define CONFIG_8260_CLKIN 83333000 /* in Hz */ |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
||||
#define CONFIG_BAUDRATE 230400 |
||||
#else |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_BSP) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ |
||||
|
||||
#define CONFIG_MISC_INIT_R /* have misc_init_r() function */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk |
||||
* The main FLASH is whichever is connected to *CS0. |
||||
*/ |
||||
#define CFG_FLASH0_BASE 0x40000000 |
||||
#define CFG_FLASH1_BASE 0x60000000 |
||||
#define CFG_FLASH0_SIZE 32 |
||||
#define CFG_FLASH1_SIZE 32 |
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/ |
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#if 0 |
||||
/* Start port with environment in flash; switch to EEPROM later */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
||||
#define CFG_ENV_SIZE 0x40000 |
||||
#define CFG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
/* Final version: environment in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#if defined(CONFIG_266MHz) |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ |
||||
HRCW_MODCK_H0111) |
||||
#elif defined(CONFIG_300MHz) |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ |
||||
HRCW_MODCK_H0110) |
||||
#else |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) |
||||
#endif |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM |
||||
* is mapped at SDRAM_BASE2_PRELIM. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#ifdef CONFIG_BUSMODE_60x |
||||
#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ |
||||
BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ |
||||
#else |
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if 0 |
||||
#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
||||
#else |
||||
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 64 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
* 2 Local SDRAM 32 bit SDRAM |
||||
* |
||||
*/ |
||||
|
||||
/* Initialize SDRAM on local bus
|
||||
*/ |
||||
#define CFG_INIT_LOCAL_SDRAM |
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ |
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2] |
||||
*/ |
||||
#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
||||
#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ |
||||
|
||||
#define CFG_MPTPR 0x4000 |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command |
||||
*----------------------------------------------------------------------------- |
||||
* In fact, the address is rather configuration data presented to the SDRAM on |
||||
* its address lines. Because the address lines may be mux'ed externally either |
||||
* for 8 column or 9 column devices, some bits appear twice in the 8260's |
||||
* address: |
||||
* |
||||
* | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | |
||||
* | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | |
||||
* 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MRS_OFFS 0x00000110 |
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* SDRAM on TQM8260 can have either 8 or 9 columns.
|
||||
* The number affects configuration values. |
||||
*/ |
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
*/ |
||||
#define CFG_PSRT 0x20 |
||||
#define CFG_LSRT 0x20 |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM CFG_OR1_8COL |
||||
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A7 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A5 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A7 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* Bank 2 - Local bus SDRAM
|
||||
*/ |
||||
#ifdef CFG_INIT_LOCAL_SDRAM |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_8COL |
||||
|
||||
#define SDRAM_BASE2_PRELIM 0x80000000 |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A8 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_LSDMR_8COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A6 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_LSDMR_9COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
#endif /* CFG_INIT_LOCAL_SDRAM */ |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
#define CFG_CAN0_BASE 0xc0000000 |
||||
#define CFG_CAN1_BASE 0xc0008000 |
||||
#define CFG_FIOX_BASE 0xc0010000 |
||||
#define CFG_FDOHM_BASE 0xc0018000 |
||||
#define CFG_EXTPROM_BASE 0xc2000000 |
||||
|
||||
#define CFG_CAN_SIZE 0x00000100 |
||||
#define CFG_FIOX_SIZE 0x00000020 |
||||
#define CFG_FDOHM_SIZE 0x00002000 |
||||
#define CFG_EXTPROM_BANK_SIZE 0x01000000 |
||||
|
||||
#define EXT_EEPROM_MAX_FLASH_BANKS 0x02 |
||||
|
||||
/* CS3 - CAN 0
|
||||
*/ |
||||
#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMA |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ |
||||
ORxU_BI |\
|
||||
ORxU_EHTR_4IDLE) |
||||
|
||||
/* CS4 - CAN 1
|
||||
*/ |
||||
#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_8 |\
|
||||
BRx_MS_UPMA |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ |
||||
ORxU_BI |\
|
||||
ORxU_EHTR_4IDLE) |
||||
|
||||
/* CS5 - Extended PROM (16MB optional)
|
||||
*/ |
||||
#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* CS6 - Extended PROM (16MB optional)
|
||||
*/ |
||||
#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ |
||||
CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* CS7 - FPGA FIOX: Glue Logic
|
||||
*/ |
||||
#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ |
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* CS8 - FPGA DOH Master
|
||||
*/ |
||||
#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_16 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ |
||||
ORxG_ACS_DIV4 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_TRLX) |
||||
|
||||
|
||||
/* FPGA configuration */ |
||||
#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */ |
||||
#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */ |
||||
#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */ |
||||
|
||||
#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */ |
||||
#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */ |
||||
#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */ |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
|
@ -0,0 +1,412 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ |
||||
#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
||||
"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
|
||||
"nfsaddrs=10.0.0.99:10.0.0.2" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_COMMANDS \ |
||||
((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ETHADDR 00:D0:93:00:01:CB |
||||
#define CONFIG_IPADDR 10.0.0.98 |
||||
#define CONFIG_SERVERIP 10.0.0.1 |
||||
#undef CONFIG_BOOTCOMMAND |
||||
#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" |
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#ifdef DEBUG |
||||
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
/* 0x00000040 */ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* 0x00b0c0c0 */ |
||||
#define CFG_PLPRCR \ |
||||
( (11 << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
/* 0x01800014 */ |
||||
#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD101 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* 0x00C3 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* TIMEP=2 */ |
||||
#define CFG_RCCR 0x0200 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDSR - SDMA Status Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SDSR ((u_char)0x83) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDMR - SDMA Mask Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SDMR ((u_char)0x00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
* Interrupt Levels |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
||||
#define CONFIG_IDE_LED 1 /* LED for ide supported */ |
||||
#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xFE100000 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#define CFG_ATA_IDE1_OFFSET 0x0C00 |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
/* EPROMs are 512kb */ |
||||
#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \ |
||||
OR_SCY_5_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/*
|
||||
* BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC) |
||||
* |
||||
*/ |
||||
#define SRAM_BASE 0xFE200000 /* SRAM bank */ |
||||
#define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */ |
||||
|
||||
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
||||
|
||||
#define PER8_BASE 0xFE000000 /* PER8 bank */ |
||||
#define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */ |
||||
|
||||
#define SHARC_BASE 0xFE400000 /* SHARC bank */ |
||||
#define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */ |
||||
|
||||
/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
|
||||
#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */ |
||||
#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM ) |
||||
#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */ |
||||
#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) |
||||
|
||||
#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */ |
||||
#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 ) |
||||
#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */ |
||||
#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC ) |
||||
#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) |
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTB 204 |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MBMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \ |
||||
MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \
|
||||
MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,617 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Imported from global configuration: |
||||
* CONFIG_L2_CACHE |
||||
* CONFIG_266MHz |
||||
* CONFIG_300MHz |
||||
*/ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
||||
|
||||
#if 0 |
||||
#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ |
||||
#else |
||||
#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ |
||||
#endif |
||||
|
||||
/* Define 60x busmode only if your TQM8260 has L2 cache! */ |
||||
#ifdef CONFIG_L2_CACHE |
||||
# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */ |
||||
#else |
||||
# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */ |
||||
#endif |
||||
|
||||
/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */ |
||||
#ifdef CONFIG_300MHz |
||||
# define CONFIG_BUSMODE_60x |
||||
#endif |
||||
|
||||
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
|
||||
/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ |
||||
#if (CONFIG_TQM8260 <= 100) |
||||
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00020000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00020000) |
||||
#define I2C_READ ((iop->pdat & 0x00020000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#else |
||||
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
#endif |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
#define CONFIG_I2C_X |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#ifdef CONFIG_82xx_CONS_SMC1 |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
#endif |
||||
#ifdef CONFIG_82xx_CONS_SMC2 |
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
||||
#endif |
||||
|
||||
#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ |
||||
#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ |
||||
#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
* |
||||
* (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the |
||||
* X.29 connector, and FCC2 is hardwired to the X.1 connector) |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
||||
|
||||
#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) |
||||
|
||||
/*
|
||||
* - RX clk is CLK11 |
||||
* - TX clk is CLK12 |
||||
*/ |
||||
# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
||||
* - Enable Full Duplex in FSMR |
||||
*/ |
||||
# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
||||
# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
||||
# define CFG_CPMFCR_RAMTYPE 0 |
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#ifndef CONFIG_300MHz |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#else |
||||
#define CONFIG_8260_CLKIN 83333000 /* in Hz */ |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
||||
#define CONFIG_BAUDRATE 230400 |
||||
#else |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk |
||||
* The main FLASH is whichever is connected to *CS0. |
||||
*/ |
||||
#define CFG_FLASH0_BASE 0x40000000 |
||||
#define CFG_FLASH1_BASE 0x60000000 |
||||
#define CFG_FLASH0_SIZE 32 |
||||
#define CFG_FLASH1_SIZE 32 |
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/ |
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#if 0 |
||||
/* Start port with environment in flash; switch to EEPROM later */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
||||
#define CFG_ENV_SIZE 0x40000 |
||||
#define CFG_ENV_SECT_SIZE 0x40000 |
||||
#else |
||||
/* Final version: environment in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#if defined(CONFIG_266MHz) |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ |
||||
HRCW_MODCK_H0111) |
||||
#elif defined(CONFIG_300MHz) |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ |
||||
HRCW_MODCK_H0110) |
||||
#else |
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) |
||||
#endif |
||||
|
||||
/* no slaves so just fill with zeros */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
* |
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM |
||||
* is mapped at SDRAM_BASE2_PRELIM. |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#ifdef CONFIG_BUSMODE_60x |
||||
#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ |
||||
BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ |
||||
#else |
||||
#define BCR_APD01 0x10000000 |
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#if 0 |
||||
#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
||||
#else |
||||
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 64 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
* 2 Local SDRAM 32 bit SDRAM |
||||
* |
||||
*/ |
||||
|
||||
/* Initialize SDRAM on local bus
|
||||
*/ |
||||
#define CFG_INIT_LOCAL_SDRAM |
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ |
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2] |
||||
*/ |
||||
#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ |
||||
#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ |
||||
|
||||
#define CFG_MPTPR 0x4000 |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command |
||||
*----------------------------------------------------------------------------- |
||||
* In fact, the address is rather configuration data presented to the SDRAM on |
||||
* its address lines. Because the address lines may be mux'ed externally either |
||||
* for 8 column or 9 column devices, some bits appear twice in the 8260's |
||||
* address: |
||||
* |
||||
* | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | |
||||
* | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | |
||||
* 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | |
||||
* Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_MRS_OFFS 0x00000110 |
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/ |
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ |
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_3_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX) |
||||
|
||||
/* SDRAM on TQM8260 can have either 8 or 9 columns.
|
||||
* The number affects configuration values. |
||||
*/ |
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
*/ |
||||
#define CFG_PSRT 0x20 |
||||
#define CFG_LSRT 0x20 |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR1_PRELIM CFG_OR1_8COL |
||||
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A7 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A5 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A12_A14 |\
|
||||
PSDMR_SDA10_PBI1_A7 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_EAMUX |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* Bank 2 - Local bus SDRAM
|
||||
*/ |
||||
#ifdef CFG_INIT_LOCAL_SDRAM |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ |
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_L |\
|
||||
BRx_V) |
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_8COL |
||||
|
||||
#define SDRAM_BASE2_PRELIM 0x80000000 |
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/ |
||||
#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A8 |\
|
||||
ORxS_NUMR_12) |
||||
|
||||
#define CFG_LSDMR_8COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A15_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/ |
||||
#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ |
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI1_A6 |\
|
||||
ORxS_NUMR_13) |
||||
|
||||
#define CFG_LSDMR_9COL (PSDMR_PBI |\ |
||||
PSDMR_SDAM_A16_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI1_A8 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_2C |\
|
||||
PSDMR_CL_2) |
||||
|
||||
#endif /* CFG_INIT_LOCAL_SDRAM */ |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,281 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
#define CONFIG_WALNUT405 1 /* ...on a WALNUT405 board */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */ |
||||
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#else |
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#if 1 |
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ |
||||
#endif |
||||
|
||||
/* Size (bytes) of interrupt driven serial port buffer.
|
||||
* Set to 0 to use polling instead of interrupts. |
||||
* Setting to 0 will also disable RTS/CTS handshaking. |
||||
*/ |
||||
#if 0 |
||||
#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 |
||||
#else |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#endif |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs " \ |
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
|
||||
"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" |
||||
#else |
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " \ |
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
|
||||
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_KGDB | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_ELF ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
/*
|
||||
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
||||
* If CFG_405_UART_ERRATA_59, then UART divisor is 31. |
||||
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. |
||||
* The Linux BASE_BAUD define should match this configuration. |
||||
* baseBaud = cpuClock/(uartDivisor*16) |
||||
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, |
||||
* set Linux BASE_BAUD to 403200. |
||||
*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External peripheral base address |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */ |
||||
|
||||
#define CFG_KEY_REG_BASE_ADDR 0xF0100000 |
||||
#define CFG_IR_REG_BASE_ADDR 0xF0200000 |
||||
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFF80000 |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* BEG ENVIRONNEMENT FLASH */ |
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
||||
#endif |
||||
/* END ENVIRONNEMENT FLASH */ |
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
#define CFG_ENV_ADDR \ |
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
||||
|
||||
|
||||
/* Configuration Port location */ |
||||
#define CONFIG_PORT_ADDR 0xF0000500 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address |
||||
* (to get SDRAM settings) |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,417 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ |
||||
#define CONFIG_C2MON 1 /* ...on a C2MON module */ |
||||
|
||||
#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_STATUS_LED /* Status LED disabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */ |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DATE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#undef CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#if defined(DEBUG) |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
* |
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
||||
*/ |
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
||||
#define CFG_PLPRCR \ |
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
||||
#else /* up to 50 MHz we use a 1:1 clock */ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
#endif /* CONFIG_80MHz */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
||||
#define CFG_SCCR (/* SCCR_TBS | */ \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#else /* up to 50 MHz we use a 1:1 clock */ |
||||
#define CFG_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
#endif /* CONFIG_80MHz */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA Power Switch |
||||
* |
||||
* The C2MON uses a TPS2211A PC-Card Power-Interface Switch to |
||||
* control the voltages on the PCMCIA slot which is connected |
||||
* to Port C (all outputs) and Port B (Over-Current Input) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* Output pins */ |
||||
#define TPS2211_VCCD0 0x0002 /* PC.14 */ |
||||
#define TPS2211_VCCD1 0x0004 /* PC.13 */ |
||||
#define TPS2211_VPPD0 0x0008 /* PC.12 */ |
||||
#define TPS2211_VPPD1 0x0010 /* PC.11 */ |
||||
#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \ |
||||
TPS2211_VPPD0 | TPS2211_VPPD1 ) |
||||
|
||||
/* Input pins */ |
||||
#define TPS2211_OC 0x00000200 /* PB.22: Over-Current */ |
||||
#define TPS2211_INPUTS ( TPS2211_OC ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
||||
OR_SCY_5_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
#ifndef CONFIG_CAN_DRIVER |
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM |
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
||||
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
||||
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
||||
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) |
||||
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ |
||||
BR_PS_8 | BR_MS_UPMB | BR_V ) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,400 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Murray Jensen <Murray.Jensen@cmst.csiro.au> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for Cogent platform using an MPC8xx CPU module |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
||||
#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ |
||||
|
||||
/* Cogent Modular Architecture options */ |
||||
#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ |
||||
#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ |
||||
#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ |
||||
#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ |
||||
|
||||
/*
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
||||
* from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#define CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ |
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
||||
#define CONFIG_BAUDRATE 230400 |
||||
#else |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#endif |
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#ifdef DEBUG |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ |
||||
#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ |
||||
#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ |
||||
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */ |
||||
# else |
||||
#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ |
||||
# endif |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Low Level Cogent settings |
||||
* if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not. |
||||
* also, make sure CONFIG_CONS_INDEX is still defined - the index will be |
||||
* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B |
||||
* (second 2 for CMA120 only) |
||||
*/ |
||||
#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ |
||||
|
||||
#include <configs/cogent_common.h> |
||||
|
||||
#ifdef CONFIG_CONS_NONE |
||||
#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ |
||||
#endif |
||||
#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ |
||||
|
||||
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) |
||||
/*
|
||||
* flash exists on the motherboard |
||||
* set these four according to TOP dipsw: |
||||
* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) |
||||
* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) |
||||
*/ |
||||
#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE |
||||
#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE |
||||
#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE |
||||
#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE |
||||
#endif |
||||
#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE |
||||
#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CFG_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
||||
*/ |
||||
#define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\ |
||||
HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101) |
||||
/* no slaves so just duplicate the master hrcw */ |
||||
#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER |
||||
#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE CMA_MB_RAM_BASE |
||||
#ifdef CONFIG_CMA302 |
||||
#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ |
||||
#else |
||||
#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ |
||||
#ifdef CONFIG_CMA302 |
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ |
||||
#else |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control - initially enable both caches and |
||||
* invalidate contents, then the final state leaves only the instruction |
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches, |
||||
* but Soft reset does not. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
||||
#define CFG_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CFG_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_BCR BCR_EBM |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
*----------------------------------------------------------------------- |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*/ |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CFG_SCCR (SCCR_DFBRG01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0 |
||||
|
||||
#if defined(CONFIG_CMA282) |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM |
||||
* and CS2 for (optional) local bus RAM on the CPU module. |
||||
* |
||||
* Note the motherboard address space (256 Mbyte in size) is connected |
||||
* to the 60x Bus and is located starting at address 0. The Hard Reset |
||||
* Configuration Word should put the 60x Bus into External Bus Mode, since |
||||
* we dont set up any memory controller maps for it (see BCR[EBM], 4-26). |
||||
* |
||||
* (the *_SIZE vars must be a power of 2) |
||||
*/ |
||||
|
||||
#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ |
||||
#define CFG_CMA_CS0_SIZE (1 << 20) |
||||
#if 0 |
||||
#define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */ |
||||
#define CFG_CMA_CS2_SIZE (16 << 20) |
||||
#endif |
||||
|
||||
/*
|
||||
* CS0 maps the EPROM on the cpu module |
||||
* Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M |
||||
* |
||||
* Note: We must have already transferred control to the final location |
||||
* of the EPROM before these are used, because when BR0/OR0 are set, the |
||||
* mirror of the eprom at any other addresses will disappear. |
||||
*/ |
||||
|
||||
/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */ |
||||
#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V) |
||||
/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */ |
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\ |
||||
ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) |
||||
|
||||
/*
|
||||
* CS2 enables the Local Bus SDRAM on the CPU Module |
||||
* |
||||
* Will leave this unset for the moment, because a) my CPU module has no |
||||
* SDRAM installed (it is optional); and b) it will require programming |
||||
* one of the UPMs in SDRAM mode - not a trivial job, and hard to get right |
||||
* if you can't test it. |
||||
*/ |
||||
|
||||
#if 0 |
||||
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */ |
||||
#define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V) |
||||
/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */ |
||||
#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/) |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,357 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Murray Jensen <Murray.Jensen@cmst.csiro.au> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for Cogent platform using an MPC8xx CPU module |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is an MPC860 CPU */ |
||||
#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ |
||||
|
||||
/* Cogent Modular Architecture options */ |
||||
#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ |
||||
#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */ |
||||
#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */ |
||||
|
||||
/* serial console configuration */ |
||||
#undef CONFIG_8xx_CONS_SMC1 |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */ |
||||
|
||||
#if defined(CONFIG_CMA286_60_OLD) |
||||
#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */ |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 230400 |
||||
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#define CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#endif |
||||
|
||||
#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
#define CFG_ALLOC_DPRAM |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Low Level Cogent settings |
||||
* if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not. |
||||
* also, make sure CONFIG_CONS_INDEX is still defined - the index will be |
||||
* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B |
||||
* (second 2 for CMA120 only) |
||||
*/ |
||||
#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */ |
||||
|
||||
#include <configs/cogent_common.h> |
||||
|
||||
#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ |
||||
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) |
||||
/*
|
||||
* flash exists on the motherboard |
||||
* set these four according to TOP dipsw: |
||||
* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) |
||||
* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) |
||||
*/ |
||||
#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE |
||||
#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE |
||||
#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE |
||||
#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE |
||||
#endif |
||||
#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE |
||||
#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE CMA_MB_RAM_BASE |
||||
#ifdef CONFIG_CMA302 |
||||
#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ |
||||
#else |
||||
#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */ |
||||
#ifdef CONFIG_CMA302 |
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ |
||||
#else |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0 |
||||
|
||||
#if defined(CONFIG_CMA286_60_OLD) |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings, |
||||
* they are actually the final settings for this cpu/board, because the |
||||
* flash and RAM are on the motherboard, accessed via the CMAbus, and the |
||||
* mappings are pretty much fixed. |
||||
* |
||||
* (the *_SIZE vars must be a power of 2) |
||||
*/ |
||||
|
||||
#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */ |
||||
#define CFG_CMA_CS0_SIZE (1 << 20) |
||||
#define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */ |
||||
#define CFG_CMA_CS1_SIZE (64 << 20) |
||||
#define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */ |
||||
#define CFG_CMA_CS2_SIZE (64 << 20) |
||||
#define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */ |
||||
#define CFG_CMA_CS3_SIZE (32 << 20) |
||||
|
||||
/*
|
||||
* CS0 maps the EPROM on the cpu module |
||||
* Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M |
||||
* |
||||
* Note: We must have already transferred control to the final location |
||||
* of the EPROM before these are used, because when BR0/OR0 are set, the |
||||
* mirror of the eprom at any other addresses will disappear. |
||||
*/ |
||||
|
||||
/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */ |
||||
#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V) |
||||
/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */ |
||||
#define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK) |
||||
|
||||
/*
|
||||
* CS1 maps motherboard DRAM and motherboard I/O slot 1 |
||||
* (each 32Mbyte in size) |
||||
*/ |
||||
|
||||
/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */ |
||||
#define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V) |
||||
/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */ |
||||
#define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA) |
||||
|
||||
/*
|
||||
* CS2 maps motherboard I/O slots 2 and 3 |
||||
* (each 32Mbyte in size) |
||||
*/ |
||||
|
||||
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */ |
||||
#define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V) |
||||
/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */ |
||||
#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA) |
||||
|
||||
/*
|
||||
* CS3 maps motherboard I/O |
||||
* (32Mbyte in size) |
||||
*/ |
||||
|
||||
/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */ |
||||
#define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V) |
||||
/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */ |
||||
#define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,535 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Workaround for layout bug on prototype board |
||||
*/ |
||||
#define PCU_E_WITH_SWAPPED_CS 1 |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_PCU_E 1 /* ...on a PCU E board */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define CONFIG_SPI /* enable SPI driver */ |
||||
#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ |
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* Offset to initial SPI buffers in DPRAM (used if the environment |
||||
* is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to |
||||
* use at an early stage. It is used between the two initialization |
||||
* calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it |
||||
* far enough from the start of the data area (as well as from the |
||||
* stack pointer). |
||||
* ---------------------------------------------------------------- */ |
||||
#define CFG_SPI_INIT_OFFSET 0xB00 |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_BSP ) |
||||
|
||||
#define CONFIG_BOOTP_MASK \ |
||||
((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
||||
|
||||
/* Ethernet hardware configuration done using port pins */ |
||||
#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */ |
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ |
||||
#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ |
||||
#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ |
||||
#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */ |
||||
#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */ |
||||
#else /* XXX */ |
||||
#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */ |
||||
#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ |
||||
#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */ |
||||
#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */ |
||||
#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */ |
||||
#endif /* XXX */ |
||||
|
||||
/* Ethernet settings:
|
||||
* MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex |
||||
*/ |
||||
#define CFG_ETH_MDDIS_VALUE 0 |
||||
#define CFG_ETH_CFG1_VALUE 1 |
||||
#define CFG_ETH_CFG2_VALUE 1 |
||||
#define CFG_ETH_CFG3_VALUE 1 |
||||
|
||||
/* PUMA configuration */ |
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */ |
||||
#else /* XXX */ |
||||
#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */ |
||||
#endif /* XXX */ |
||||
#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */ |
||||
#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFE000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Address accessed to reset the board - must not be mapped/assigned |
||||
*/ |
||||
#define CFG_RESET_ADDRESS 0xFEFFFFFF |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
/* this is an ugly hack needed because of the silly non-constant address map */ |
||||
#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) |
||||
|
||||
#if defined(DEBUG) |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#else |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#endif |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#if 0 |
||||
/* Start port with environment in flash; switch to SPI EEPROM later */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ |
||||
#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ |
||||
#else |
||||
/* Final version: environment in EEPROM */ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_I2C_EEPROM_ADDR 0 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_ENV_OFFSET 1024 |
||||
#define CFG_ENV_SIZE 1024 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* External Arbitration max. priority (7), |
||||
* Debug pins configuration '11', |
||||
* Asynchronous external master enable. |
||||
*/ |
||||
/* => 0x70600200 */ |
||||
#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit, set PLL multiplication factor ! |
||||
*/ |
||||
/* 0x00004080 */ |
||||
#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ |
||||
#define CFG_PLPRCR \ |
||||
( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
|
||||
) |
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
* |
||||
* Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
/* 0x01800000 */ |
||||
#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ |
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD100 | \
|
||||
SCCR_DFALCD01) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
* Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! |
||||
* |
||||
* Don't expect the "date" command to work without a 32kHz clock input! |
||||
*/ |
||||
/* 0x00C3 => 0x0003 */ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RCCR 0x0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RMDS 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
* Interrupt Levels |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ |
||||
#else /* XXX */ |
||||
#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* used to re-map FLASH: restrict access enough but not too much to |
||||
* meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ |
||||
|
||||
/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) |
||||
|
||||
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ |
||||
CFG_OR_TIMING_FLASH) |
||||
/* 16 bit, bank valid */ |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_OR6_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR6_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
#else /* XXX */ |
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP |
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR2/OR2: SDRAM |
||||
* |
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care) |
||||
*/ |
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#else /* XXX */ |
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ |
||||
#endif /* XXX */ |
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ |
||||
#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ |
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) |
||||
#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#else /* XXX */ |
||||
#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) |
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR3/OR3: CAN Controller |
||||
* BR3: 0x10000401 OR3: 0xffff818a |
||||
*/ |
||||
#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ |
||||
#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ |
||||
#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) |
||||
#else /* XXX */ |
||||
#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR4/OR4: PUMA Config |
||||
* |
||||
* Memory controller will be used in 2 modes: |
||||
* |
||||
* - "read" mode: |
||||
* BR4: 0x10100801 OR4: 0xffff8530 |
||||
* - "load" mode (chip select on UPM B): |
||||
* BR4: 0x101008c1 OR4: 0xffff8630 |
||||
* |
||||
* Default initialization is in "read" mode |
||||
*/ |
||||
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ |
||||
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ |
||||
#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) |
||||
#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) |
||||
|
||||
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ |
||||
BR_PS_16 | BR_MS_UPMB | BR_V) |
||||
#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) |
||||
|
||||
#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_BR3_PRELIM PUMA_CONF_BR_READ |
||||
#define CFG_OR3_PRELIM PUMA_CONF_OR_READ |
||||
#else /* XXX */ |
||||
#define CFG_BR4_PRELIM PUMA_CONF_BR_READ |
||||
#define CFG_OR4_PRELIM PUMA_CONF_OR_READ |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR5/OR5: PUMA: SMA Bus 8 Bit |
||||
* BR5: 0x10200401 OR5: 0xffe0010a |
||||
*/ |
||||
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ |
||||
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ |
||||
#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) |
||||
#else /* XXX */ |
||||
#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
||||
#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR6/OR6: PUMA: SMA Bus 16 Bit |
||||
* BR6: 0x10600801 OR6: 0xffe0010a |
||||
*/ |
||||
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ |
||||
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ |
||||
#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) |
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */ |
||||
#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) |
||||
#else /* XXX */ |
||||
#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) |
||||
#endif /* XXX */ |
||||
|
||||
/*
|
||||
* BR7/OR7: PUMA: external Flash |
||||
* BR7: 0x10a00801 OR7: 0xfe00010a |
||||
*/ |
||||
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ |
||||
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ |
||||
#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) |
||||
|
||||
#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) |
||||
#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MPTPR 0x0200 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
* 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, |
||||
* MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X |
||||
* 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X |
||||
*/ |
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 0x30 /* = 48 */ |
||||
|
||||
#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ |
||||
MAMR_AMB_TYPE_1 | \
|
||||
MAMR_G0CLB_A10 | \
|
||||
MAMR_RLFB_1X | \
|
||||
MAMR_WLFB_1X | \
|
||||
MAMR_TLFB_8X ) |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue