Tom Rini
8 years ago
commit
0fcb9f07a1
@ -0,0 +1,200 @@ |
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/dts-v1/; |
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#include "sama5d2.dtsi" |
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#include "sama5d2-pinfunc.h" |
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|
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/ { |
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model = "Atmel SAMA5D2 Xplained"; |
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compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; |
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|
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chosen { |
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stdout-path = &uart1; |
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}; |
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|
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ahb { |
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usb1: ohci@00400000 { |
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num-ports = <3>; |
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atmel,vbus-gpio = <&pioA 42 0>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb_default>; |
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status = "okay"; |
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}; |
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|
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usb2: ehci@00500000 { |
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status = "okay"; |
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}; |
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|
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sdmmc0: sdio-host@a0000000 { |
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bus-width = <8>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; |
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status = "okay"; |
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}; |
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|
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sdmmc1: sdio-host@b0000000 { |
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bus-width = <4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; |
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status = "okay"; /* conflict with qspi0 */ |
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}; |
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|
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apb { |
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qspi0: spi@f0020000 { |
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status = "okay"; |
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|
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flash@0 { |
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compatible = "atmel,sama5d2-qspi-flash"; |
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reg = <0>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_qspi0_default>; |
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spi-max-frequency = <83000000>; |
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|
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partition@00000000 { |
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label = "boot"; |
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reg = <0x00000000 0x00c00000>; |
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}; |
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|
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partition@00c00000 { |
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label = "rootfs"; |
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reg = <0x00c00000 0x00000000>; |
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}; |
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}; |
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}; |
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|
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spi0: spi@f8000000 { |
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cs-gpios = <&pioA 17 0>, <0>, <0>, <0>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_spi0_default>; |
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status = "okay"; |
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|
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spi_flash@0 { |
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compatible = "spi-flash"; |
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reg = <0>; |
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spi-max-frequency = <50000000>; |
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}; |
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}; |
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|
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macb0: ethernet@f8008000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; |
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phy-mode = "rmii"; |
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status = "okay"; |
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|
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ethernet-phy@1 { |
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reg = <0x1>; |
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}; |
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}; |
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|
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uart1: serial@f8020000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1_default>; |
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status = "okay"; |
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}; |
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|
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i2c1: i2c@fc028000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c1_default>; |
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status = "okay"; |
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}; |
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|
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pioA: gpio@fc038000 { |
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pinctrl { |
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pinctrl_i2c1_default: i2c1_default { |
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pinmux = <PIN_PD4__TWD1>, |
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<PIN_PD5__TWCK1>; |
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bias-disable; |
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}; |
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|
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pinctrl_macb0_phy_irq: macb0_phy_irq { |
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pinmux = <PIN_PC9__GPIO>; |
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bias-disable; |
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}; |
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|
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pinctrl_macb0_rmii: macb0_rmii { |
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pinmux = <PIN_PB14__GTXCK>, |
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<PIN_PB15__GTXEN>, |
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<PIN_PB16__GRXDV>, |
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<PIN_PB17__GRXER>, |
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<PIN_PB18__GRX0>, |
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<PIN_PB19__GRX1>, |
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<PIN_PB20__GTX0>, |
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<PIN_PB21__GTX1>, |
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<PIN_PB22__GMDC>, |
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<PIN_PB23__GMDIO>; |
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bias-disable; |
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}; |
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|
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pinctrl_qspi0_default: qspi0_default { |
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pinmux = <PIN_PA22__QSPI0_SCK>, |
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<PIN_PA23__QSPI0_CS>, |
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<PIN_PA24__QSPI0_IO0>, |
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<PIN_PA25__QSPI0_IO1>, |
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<PIN_PA26__QSPI0_IO2>, |
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<PIN_PA27__QSPI0_IO3>; |
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bias-disable; |
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}; |
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|
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pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { |
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pinmux = <PIN_PA1__SDMMC0_CMD>, |
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<PIN_PA2__SDMMC0_DAT0>, |
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<PIN_PA3__SDMMC0_DAT1>, |
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<PIN_PA4__SDMMC0_DAT2>, |
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<PIN_PA5__SDMMC0_DAT3>, |
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<PIN_PA6__SDMMC0_DAT4>, |
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<PIN_PA7__SDMMC0_DAT5>, |
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<PIN_PA8__SDMMC0_DAT6>, |
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<PIN_PA9__SDMMC0_DAT7>; |
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bias-pull-up; |
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}; |
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|
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pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { |
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pinmux = <PIN_PA0__SDMMC0_CK>, |
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<PIN_PA10__SDMMC0_RSTN>, |
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<PIN_PA11__SDMMC0_VDDSEL>, |
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<PIN_PA13__SDMMC0_CD>; |
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bias-disable; |
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}; |
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pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { |
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pinmux = <PIN_PA28__SDMMC1_CMD>, |
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<PIN_PA18__SDMMC1_DAT0>, |
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<PIN_PA19__SDMMC1_DAT1>, |
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<PIN_PA20__SDMMC1_DAT2>, |
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<PIN_PA21__SDMMC1_DAT3>; |
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bias-pull-up; |
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}; |
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pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { |
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pinmux = <PIN_PA22__SDMMC1_CK>, |
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<PIN_PA30__SDMMC1_CD>; |
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bias-disable; |
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}; |
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pinctrl_spi0_default: spi0_default { |
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pinmux = <PIN_PA14__SPI0_SPCK>, |
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<PIN_PA15__SPI0_MOSI>, |
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<PIN_PA16__SPI0_MISO>; |
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bias-disable; |
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}; |
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pinctrl_uart1_default: uart1_default { |
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pinmux = <PIN_PD2__URXD1>, |
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<PIN_PD3__UTXD1>; |
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bias-disable; |
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}; |
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pinctrl_usb_default: usb_default { |
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pinmux = <PIN_PB10__GPIO>; |
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bias-disable; |
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}; |
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pinctrl_usba_vbus: usba_vbus { |
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pinmux = <PIN_PA31__GPIO>; |
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bias-disable; |
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}; |
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}; |
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}; |
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}; |
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}; |
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}; |
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@ -0,0 +1,880 @@ |
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#define PINMUX_PIN(no, func, ioset) \ |
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(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) |
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|
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#define PIN_PA0 0 |
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#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) |
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#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) |
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#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) |
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#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) |
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#define PIN_PA1 1 |
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#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) |
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#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) |
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#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) |
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#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) |
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#define PIN_PA2 2 |
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#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) |
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#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) |
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#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) |
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#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) |
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#define PIN_PA3 3 |
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#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) |
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#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) |
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#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) |
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#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) |
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#define PIN_PA4 4 |
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#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) |
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#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) |
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#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) |
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#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) |
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#define PIN_PA5 5 |
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#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) |
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#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) |
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#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) |
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#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) |
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#define PIN_PA6 6 |
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#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) |
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#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) |
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#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) |
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#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) |
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#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) |
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#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) |
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#define PIN_PA7 7 |
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#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) |
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#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) |
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#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) |
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#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) |
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#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) |
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#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) |
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#define PIN_PA8 8 |
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#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) |
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#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) |
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#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) |
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#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) |
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#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) |
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#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) |
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#define PIN_PA9 9 |
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#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) |
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#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) |
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#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) |
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#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) |
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#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) |
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#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) |
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#define PIN_PA10 10 |
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#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) |
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#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) |
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#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) |
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#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) |
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#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) |
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#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) |
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#define PIN_PA11 11 |
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#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) |
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#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) |
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#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) |
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#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) |
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#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) |
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#define PIN_PA12 12 |
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#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) |
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#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) |
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#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) |
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#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) |
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#define PIN_PA13 13 |
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#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) |
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#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) |
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#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) |
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#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) |
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#define PIN_PA14 14 |
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#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) |
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#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) |
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#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) |
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#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) |
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#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) |
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#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) |
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#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) |
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#define PIN_PA15 15 |
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#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) |
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#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) |
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#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) |
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#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) |
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#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) |
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#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) |
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#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) |
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#define PIN_PA16 16 |
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#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) |
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#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) |
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#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) |
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#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) |
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#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) |
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#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) |
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#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) |
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#define PIN_PA17 17 |
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#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) |
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#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) |
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#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) |
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#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) |
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#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) |
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#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) |
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#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) |
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#define PIN_PA18 18 |
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#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) |
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#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) |
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#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) |
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#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) |
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#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) |
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#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) |
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#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) |
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#define PIN_PA19 19 |
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#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) |
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#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) |
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#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) |
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#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) |
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#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) |
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#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) |
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#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) |
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#define PIN_PA20 20 |
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#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) |
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#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) |
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#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) |
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#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) |
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#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) |
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#define PIN_PA21 21 |
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#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) |
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#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) |
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#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) |
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#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) |
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#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) |
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#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) |
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#define PIN_PA22 22 |
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#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) |
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#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) |
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#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) |
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#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) |
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#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) |
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#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) |
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#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) |
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#define PIN_PA23 23 |
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#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) |
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#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) |
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#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) |
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#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) |
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#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) |
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#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) |
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#define PIN_PA24 24 |
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#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) |
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#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) |
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#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) |
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#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) |
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#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) |
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#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) |
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#define PIN_PA25 25 |
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#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) |
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#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) |
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#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) |
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#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) |
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#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) |
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#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) |
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#define PIN_PA26 26 |
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#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) |
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#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) |
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#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) |
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#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) |
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#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) |
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#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) |
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#define PIN_PA27 27 |
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#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) |
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#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) |
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#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) |
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#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) |
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#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) |
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#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) |
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#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) |
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#define PIN_PA28 28 |
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#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) |
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#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) |
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#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) |
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#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) |
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#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) |
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#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) |
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#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) |
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#define PIN_PA29 29 |
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#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) |
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#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) |
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#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) |
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#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) |
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#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) |
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#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) |
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#define PIN_PA30 30 |
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#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) |
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#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) |
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#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) |
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#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) |
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#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) |
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#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) |
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#define PIN_PA31 31 |
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#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) |
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#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) |
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#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) |
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#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) |
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#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) |
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#define PIN_PB0 32 |
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#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) |
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#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) |
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#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) |
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#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) |
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#define PIN_PB1 33 |
||||
#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) |
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#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) |
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#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) |
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#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) |
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#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) |
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#define PIN_PB2 34 |
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#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) |
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#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) |
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#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) |
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#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) |
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#define PIN_PB3 35 |
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#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) |
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#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) |
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#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) |
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#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) |
||||
#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) |
||||
#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) |
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#define PIN_PB4 36 |
||||
#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) |
||||
#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) |
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#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) |
||||
#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) |
||||
#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) |
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#define PIN_PB5 37 |
||||
#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) |
||||
#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) |
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#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) |
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#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) |
||||
#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) |
||||
#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) |
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#define PIN_PB6 38 |
||||
#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) |
||||
#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) |
||||
#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) |
||||
#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) |
||||
#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) |
||||
#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) |
||||
#define PIN_PB7 39 |
||||
#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) |
||||
#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) |
||||
#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) |
||||
#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) |
||||
#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) |
||||
#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) |
||||
#define PIN_PB8 40 |
||||
#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) |
||||
#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) |
||||
#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) |
||||
#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) |
||||
#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) |
||||
#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) |
||||
#define PIN_PB9 41 |
||||
#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) |
||||
#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) |
||||
#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) |
||||
#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) |
||||
#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) |
||||
#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) |
||||
#define PIN_PB10 42 |
||||
#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) |
||||
#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) |
||||
#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) |
||||
#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) |
||||
#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) |
||||
#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) |
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#define PIN_PB11 43 |
||||
#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) |
||||
#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) |
||||
#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) |
||||
#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) |
||||
#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) |
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#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) |
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#define PIN_PB12 44 |
||||
#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) |
||||
#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) |
||||
#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) |
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#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) |
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#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) |
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#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) |
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#define PIN_PB13 45 |
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#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) |
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#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) |
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#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) |
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#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) |
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#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) |
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#define PIN_PB14 46 |
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#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) |
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#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) |
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#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) |
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#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) |
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#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) |
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#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) |
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#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) |
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#define PIN_PB15 47 |
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#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) |
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#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) |
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#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) |
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#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) |
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#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) |
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#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) |
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#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) |
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#define PIN_PB16 48 |
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#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) |
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#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) |
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#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) |
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#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) |
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#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) |
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#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) |
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#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) |
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#define PIN_PB17 49 |
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#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) |
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#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) |
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#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) |
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#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) |
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#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) |
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#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) |
||||
#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) |
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#define PIN_PB18 50 |
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#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) |
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#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) |
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#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) |
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#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) |
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#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) |
||||
#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) |
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#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) |
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#define PIN_PB19 51 |
||||
#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) |
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#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) |
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#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) |
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#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) |
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#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) |
||||
#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) |
||||
#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) |
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#define PIN_PB20 52 |
||||
#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) |
||||
#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) |
||||
#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) |
||||
#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) |
||||
#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) |
||||
#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) |
||||
#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) |
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#define PIN_PB21 53 |
||||
#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) |
||||
#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) |
||||
#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) |
||||
#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) |
||||
#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) |
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#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) |
||||
#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) |
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#define PIN_PB22 54 |
||||
#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) |
||||
#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) |
||||
#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) |
||||
#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) |
||||
#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) |
||||
#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) |
||||
#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) |
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#define PIN_PB23 55 |
||||
#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) |
||||
#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) |
||||
#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) |
||||
#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) |
||||
#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) |
||||
#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) |
||||
#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) |
||||
#define PIN_PB24 56 |
||||
#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) |
||||
#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) |
||||
#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) |
||||
#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) |
||||
#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) |
||||
#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) |
||||
#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) |
||||
#define PIN_PB25 57 |
||||
#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) |
||||
#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) |
||||
#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) |
||||
#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) |
||||
#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) |
||||
#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) |
||||
#define PIN_PB26 58 |
||||
#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) |
||||
#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) |
||||
#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) |
||||
#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) |
||||
#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) |
||||
#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) |
||||
#define PIN_PB27 59 |
||||
#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) |
||||
#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) |
||||
#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) |
||||
#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) |
||||
#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) |
||||
#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) |
||||
#define PIN_PB28 60 |
||||
#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) |
||||
#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) |
||||
#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) |
||||
#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) |
||||
#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) |
||||
#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) |
||||
#define PIN_PB29 61 |
||||
#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) |
||||
#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) |
||||
#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) |
||||
#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) |
||||
#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) |
||||
#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) |
||||
#define PIN_PB30 62 |
||||
#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) |
||||
#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) |
||||
#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) |
||||
#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) |
||||
#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) |
||||
#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) |
||||
#define PIN_PB31 63 |
||||
#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) |
||||
#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) |
||||
#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) |
||||
#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) |
||||
#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) |
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#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) |
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#define PIN_PC0 64 |
||||
#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) |
||||
#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) |
||||
#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) |
||||
#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) |
||||
#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) |
||||
#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) |
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#define PIN_PC1 65 |
||||
#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) |
||||
#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) |
||||
#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) |
||||
#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) |
||||
#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) |
||||
#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) |
||||
#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) |
||||
#define PIN_PC2 66 |
||||
#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) |
||||
#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) |
||||
#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) |
||||
#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) |
||||
#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) |
||||
#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) |
||||
#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) |
||||
#define PIN_PC3 67 |
||||
#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) |
||||
#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) |
||||
#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) |
||||
#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) |
||||
#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) |
||||
#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) |
||||
#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) |
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#define PIN_PC4 68 |
||||
#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) |
||||
#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) |
||||
#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) |
||||
#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) |
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#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) |
||||
#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) |
||||
#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) |
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#define PIN_PC5 69 |
||||
#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) |
||||
#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) |
||||
#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) |
||||
#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) |
||||
#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) |
||||
#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) |
||||
#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) |
||||
#define PIN_PC6 70 |
||||
#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) |
||||
#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) |
||||
#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) |
||||
#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) |
||||
#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) |
||||
#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) |
||||
#define PIN_PC7 71 |
||||
#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) |
||||
#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) |
||||
#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) |
||||
#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) |
||||
#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) |
||||
#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) |
||||
#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) |
||||
#define PIN_PC8 72 |
||||
#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) |
||||
#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) |
||||
#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) |
||||
#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) |
||||
#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) |
||||
#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) |
||||
#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) |
||||
#define PIN_PC9 73 |
||||
#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) |
||||
#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) |
||||
#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) |
||||
#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1) |
||||
#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) |
||||
#define PIN_PC10 74 |
||||
#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) |
||||
#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) |
||||
#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) |
||||
#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) |
||||
#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) |
||||
#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) |
||||
#define PIN_PC11 75 |
||||
#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) |
||||
#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) |
||||
#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) |
||||
#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) |
||||
#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) |
||||
#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) |
||||
#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) |
||||
#define PIN_PC12 76 |
||||
#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) |
||||
#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) |
||||
#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) |
||||
#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) |
||||
#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) |
||||
#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) |
||||
#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) |
||||
#define PIN_PC13 77 |
||||
#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) |
||||
#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) |
||||
#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) |
||||
#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) |
||||
#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) |
||||
#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) |
||||
#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) |
||||
#define PIN_PC14 78 |
||||
#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) |
||||
#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) |
||||
#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) |
||||
#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) |
||||
#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) |
||||
#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) |
||||
#define PIN_PC15 79 |
||||
#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) |
||||
#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) |
||||
#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) |
||||
#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) |
||||
#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) |
||||
#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) |
||||
#define PIN_PC16 80 |
||||
#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) |
||||
#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) |
||||
#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) |
||||
#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) |
||||
#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) |
||||
#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) |
||||
#define PIN_PC17 81 |
||||
#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) |
||||
#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) |
||||
#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) |
||||
#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) |
||||
#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) |
||||
#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) |
||||
#define PIN_PC18 82 |
||||
#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) |
||||
#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) |
||||
#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) |
||||
#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) |
||||
#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) |
||||
#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) |
||||
#define PIN_PC19 83 |
||||
#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) |
||||
#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) |
||||
#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) |
||||
#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) |
||||
#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) |
||||
#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) |
||||
#define PIN_PC20 84 |
||||
#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) |
||||
#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) |
||||
#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) |
||||
#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) |
||||
#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) |
||||
#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) |
||||
#define PIN_PC21 85 |
||||
#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) |
||||
#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) |
||||
#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) |
||||
#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) |
||||
#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) |
||||
#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) |
||||
#define PIN_PC22 86 |
||||
#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) |
||||
#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) |
||||
#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) |
||||
#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) |
||||
#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) |
||||
#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) |
||||
#define PIN_PC23 87 |
||||
#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) |
||||
#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) |
||||
#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) |
||||
#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) |
||||
#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) |
||||
#define PIN_PC24 88 |
||||
#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) |
||||
#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) |
||||
#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) |
||||
#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) |
||||
#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) |
||||
#define PIN_PC25 89 |
||||
#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) |
||||
#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) |
||||
#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) |
||||
#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) |
||||
#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) |
||||
#define PIN_PC26 90 |
||||
#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) |
||||
#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) |
||||
#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) |
||||
#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) |
||||
#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) |
||||
#define PIN_PC27 91 |
||||
#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) |
||||
#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) |
||||
#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) |
||||
#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) |
||||
#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) |
||||
#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) |
||||
#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) |
||||
#define PIN_PC28 92 |
||||
#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) |
||||
#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) |
||||
#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) |
||||
#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) |
||||
#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) |
||||
#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) |
||||
#define PIN_PC29 93 |
||||
#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) |
||||
#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) |
||||
#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) |
||||
#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) |
||||
#define PIN_PC30 94 |
||||
#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) |
||||
#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) |
||||
#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) |
||||
#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) |
||||
#define PIN_PC31 95 |
||||
#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) |
||||
#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) |
||||
#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) |
||||
#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) |
||||
#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) |
||||
#define PIN_PD0 96 |
||||
#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) |
||||
#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) |
||||
#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) |
||||
#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) |
||||
#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) |
||||
#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) |
||||
#define PIN_PD1 97 |
||||
#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) |
||||
#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) |
||||
#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) |
||||
#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) |
||||
#define PIN_PD2 98 |
||||
#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) |
||||
#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) |
||||
#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) |
||||
#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) |
||||
#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) |
||||
#define PIN_PD3 99 |
||||
#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) |
||||
#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) |
||||
#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) |
||||
#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) |
||||
#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) |
||||
#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) |
||||
#define PIN_PD4 100 |
||||
#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) |
||||
#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) |
||||
#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) |
||||
#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) |
||||
#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) |
||||
#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) |
||||
#define PIN_PD5 101 |
||||
#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) |
||||
#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) |
||||
#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) |
||||
#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) |
||||
#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) |
||||
#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) |
||||
#define PIN_PD6 102 |
||||
#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) |
||||
#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) |
||||
#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) |
||||
#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) |
||||
#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) |
||||
#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) |
||||
#define PIN_PD7 103 |
||||
#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) |
||||
#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) |
||||
#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) |
||||
#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) |
||||
#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) |
||||
#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) |
||||
#define PIN_PD8 104 |
||||
#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) |
||||
#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) |
||||
#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) |
||||
#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) |
||||
#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) |
||||
#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) |
||||
#define PIN_PD9 105 |
||||
#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) |
||||
#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) |
||||
#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) |
||||
#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) |
||||
#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) |
||||
#define PIN_PD10 106 |
||||
#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) |
||||
#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) |
||||
#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) |
||||
#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) |
||||
#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) |
||||
#define PIN_PD11 107 |
||||
#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) |
||||
#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) |
||||
#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) |
||||
#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) |
||||
#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) |
||||
#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) |
||||
#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) |
||||
#define PIN_PD12 108 |
||||
#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) |
||||
#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) |
||||
#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) |
||||
#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) |
||||
#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) |
||||
#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) |
||||
#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) |
||||
#define PIN_PD13 109 |
||||
#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) |
||||
#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) |
||||
#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) |
||||
#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) |
||||
#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) |
||||
#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) |
||||
#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) |
||||
#define PIN_PD14 110 |
||||
#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) |
||||
#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) |
||||
#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) |
||||
#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) |
||||
#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) |
||||
#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) |
||||
#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) |
||||
#define PIN_PD15 111 |
||||
#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) |
||||
#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) |
||||
#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) |
||||
#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) |
||||
#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) |
||||
#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) |
||||
#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) |
||||
#define PIN_PD16 112 |
||||
#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) |
||||
#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) |
||||
#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) |
||||
#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) |
||||
#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) |
||||
#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) |
||||
#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) |
||||
#define PIN_PD17 113 |
||||
#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) |
||||
#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) |
||||
#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) |
||||
#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) |
||||
#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) |
||||
#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) |
||||
#define PIN_PD18 114 |
||||
#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) |
||||
#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) |
||||
#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) |
||||
#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) |
||||
#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) |
||||
#define PIN_PD19 115 |
||||
#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) |
||||
#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) |
||||
#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) |
||||
#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) |
||||
#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) |
||||
#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) |
||||
#define PIN_PD20 116 |
||||
#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) |
||||
#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) |
||||
#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) |
||||
#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) |
||||
#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) |
||||
#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) |
||||
#define PIN_PD21 117 |
||||
#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) |
||||
#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) |
||||
#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) |
||||
#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) |
||||
#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) |
||||
#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) |
||||
#define PIN_PD22 118 |
||||
#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) |
||||
#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) |
||||
#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) |
||||
#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) |
||||
#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) |
||||
#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) |
||||
#define PIN_PD23 119 |
||||
#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) |
||||
#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) |
||||
#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) |
||||
#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) |
||||
#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) |
||||
#define PIN_PD24 120 |
||||
#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) |
||||
#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD23, 1, 2) |
||||
#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD23, 3, 3) |
||||
#define PIN_PD25 121 |
||||
#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) |
||||
#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) |
||||
#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) |
||||
#define PIN_PD26 122 |
||||
#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) |
||||
#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) |
||||
#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) |
||||
#define PIN_PD27 123 |
||||
#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) |
||||
#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) |
||||
#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) |
||||
#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) |
||||
#define PIN_PD28 124 |
||||
#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) |
||||
#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) |
||||
#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) |
||||
#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) |
||||
#define PIN_PD29 125 |
||||
#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) |
||||
#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) |
||||
#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) |
||||
#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) |
||||
#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) |
||||
#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) |
||||
#define PIN_PD30 126 |
||||
#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) |
||||
#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) |
||||
#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) |
||||
#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) |
||||
#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) |
||||
#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) |
||||
#define PIN_PD31 127 |
||||
#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) |
||||
#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) |
||||
#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) |
||||
#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) |
||||
#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) |
||||
#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) |
||||
@ -0,0 +1,671 @@ |
||||
#include "skeleton.dtsi" |
||||
|
||||
/ { |
||||
model = "Atmel SAMA5D2 family SoC"; |
||||
compatible = "atmel,sama5d2"; |
||||
|
||||
aliases { |
||||
spi0 = &spi0; |
||||
spi1 = &qspi0; |
||||
i2c0 = &i2c0; |
||||
i2c1 = &i2c1; |
||||
}; |
||||
|
||||
clocks { |
||||
slow_xtal: slow_xtal { |
||||
compatible = "fixed-clock"; |
||||
#clock-cells = <0>; |
||||
clock-frequency = <0>; |
||||
}; |
||||
|
||||
main_xtal: main_xtal { |
||||
compatible = "fixed-clock"; |
||||
#clock-cells = <0>; |
||||
clock-frequency = <0>; |
||||
}; |
||||
}; |
||||
|
||||
ahb { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
usb1: ohci@00400000 { |
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
||||
reg = <0x00400000 0x100000>; |
||||
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; |
||||
clock-names = "ohci_clk", "hclk", "uhpck"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usb2: ehci@00500000 { |
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
||||
reg = <0x00500000 0x100000>; |
||||
clocks = <&utmi>, <&uhphs_clk>; |
||||
clock-names = "usb_clk", "ehci_clk"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sdmmc0: sdio-host@a0000000 { |
||||
compatible = "atmel,sama5d2-sdhci"; |
||||
reg = <0xa0000000 0x300>; |
||||
clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; |
||||
clock-names = "hclock", "multclk", "baseclk"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sdmmc1: sdio-host@b0000000 { |
||||
compatible = "atmel,sama5d2-sdhci"; |
||||
reg = <0xb0000000 0x300>; |
||||
clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; |
||||
clock-names = "hclock", "multclk", "baseclk"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
apb { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
pmc: pmc@f0014000 { |
||||
compatible = "atmel,sama5d2-pmc", "syscon"; |
||||
reg = <0xf0014000 0x160>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
#interrupt-cells = <1>; |
||||
|
||||
main: mainck { |
||||
compatible = "atmel,at91sam9x5-clk-main"; |
||||
#clock-cells = <0>; |
||||
}; |
||||
|
||||
plla: pllack { |
||||
compatible = "atmel,sama5d3-clk-pll"; |
||||
#clock-cells = <0>; |
||||
clocks = <&main>; |
||||
reg = <0>; |
||||
atmel,clk-input-range = <12000000 12000000>; |
||||
#atmel,pll-clk-output-range-cells = <4>; |
||||
atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; |
||||
}; |
||||
|
||||
plladiv: plladivck { |
||||
compatible = "atmel,at91sam9x5-clk-plldiv"; |
||||
#clock-cells = <0>; |
||||
clocks = <&plla>; |
||||
}; |
||||
|
||||
audio_pll_frac: audiopll_fracck { |
||||
compatible = "atmel,sama5d2-clk-audio-pll-frac"; |
||||
#clock-cells = <0>; |
||||
clocks = <&main>; |
||||
}; |
||||
|
||||
audio_pll_pad: audiopll_padck { |
||||
compatible = "atmel,sama5d2-clk-audio-pll-pad"; |
||||
#clock-cells = <0>; |
||||
clocks = <&audio_pll_frac>; |
||||
}; |
||||
|
||||
audio_pll_pmc: audiopll_pmcck { |
||||
compatible = "atmel,sama5d2-clk-audio-pll-pmc"; |
||||
#clock-cells = <0>; |
||||
clocks = <&audio_pll_frac>; |
||||
}; |
||||
|
||||
utmi: utmick { |
||||
compatible = "atmel,at91sam9x5-clk-utmi"; |
||||
#clock-cells = <0>; |
||||
clocks = <&main>; |
||||
}; |
||||
|
||||
mck: masterck { |
||||
compatible = "atmel,at91sam9x5-clk-master"; |
||||
#clock-cells = <0>; |
||||
clocks = <&main>, <&plladiv>, <&utmi>; |
||||
atmel,clk-output-range = <124000000 166000000>; |
||||
atmel,clk-divisors = <1 2 4 3>; |
||||
}; |
||||
|
||||
h32ck: h32mxck { |
||||
#clock-cells = <0>; |
||||
compatible = "atmel,sama5d4-clk-h32mx"; |
||||
clocks = <&mck>; |
||||
}; |
||||
|
||||
usb: usbck { |
||||
compatible = "atmel,at91sam9x5-clk-usb"; |
||||
#clock-cells = <0>; |
||||
clocks = <&plladiv>, <&utmi>; |
||||
}; |
||||
|
||||
prog: progck { |
||||
compatible = "atmel,at91sam9x5-clk-programmable"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
interrupt-parent = <&pmc>; |
||||
clocks = <&main>, <&plladiv>, <&utmi>, <&mck>; |
||||
|
||||
prog0: prog0 { |
||||
#clock-cells = <0>; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
prog1: prog1 { |
||||
#clock-cells = <0>; |
||||
reg = <1>; |
||||
}; |
||||
|
||||
prog2: prog2 { |
||||
#clock-cells = <0>; |
||||
reg = <2>; |
||||
}; |
||||
}; |
||||
|
||||
systemck { |
||||
compatible = "atmel,at91rm9200-clk-system"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
ddrck: ddrck { |
||||
#clock-cells = <0>; |
||||
reg = <2>; |
||||
clocks = <&mck>; |
||||
}; |
||||
|
||||
lcdck: lcdck { |
||||
#clock-cells = <0>; |
||||
reg = <3>; |
||||
clocks = <&mck>; |
||||
}; |
||||
|
||||
uhpck: uhpck { |
||||
#clock-cells = <0>; |
||||
reg = <6>; |
||||
clocks = <&usb>; |
||||
}; |
||||
|
||||
udpck: udpck { |
||||
#clock-cells = <0>; |
||||
reg = <7>; |
||||
clocks = <&usb>; |
||||
}; |
||||
|
||||
pck0: pck0 { |
||||
#clock-cells = <0>; |
||||
reg = <8>; |
||||
clocks = <&prog0>; |
||||
}; |
||||
|
||||
pck1: pck1 { |
||||
#clock-cells = <0>; |
||||
reg = <9>; |
||||
clocks = <&prog1>; |
||||
}; |
||||
|
||||
pck2: pck2 { |
||||
#clock-cells = <0>; |
||||
reg = <10>; |
||||
clocks = <&prog2>; |
||||
}; |
||||
|
||||
iscck: iscck { |
||||
#clock-cells = <0>; |
||||
reg = <18>; |
||||
clocks = <&mck>; |
||||
}; |
||||
}; |
||||
|
||||
periph32ck { |
||||
compatible = "atmel,at91sam9x5-clk-peripheral"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&h32ck>; |
||||
|
||||
macb0_clk: macb0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <5>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
tdes_clk: tdes_clk { |
||||
#clock-cells = <0>; |
||||
reg = <11>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
matrix1_clk: matrix1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <14>; |
||||
}; |
||||
|
||||
hsmc_clk: hsmc_clk { |
||||
#clock-cells = <0>; |
||||
reg = <17>; |
||||
}; |
||||
|
||||
pioA_clk: pioA_clk { |
||||
#clock-cells = <0>; |
||||
reg = <18>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
flx0_clk: flx0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <19>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
flx1_clk: flx1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <20>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
flx2_clk: flx2_clk { |
||||
#clock-cells = <0>; |
||||
reg = <21>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
flx3_clk: flx3_clk { |
||||
#clock-cells = <0>; |
||||
reg = <22>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
flx4_clk: flx4_clk { |
||||
#clock-cells = <0>; |
||||
reg = <23>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uart0_clk: uart0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <24>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uart1_clk: uart1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <25>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uart2_clk: uart2_clk { |
||||
#clock-cells = <0>; |
||||
reg = <26>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uart3_clk: uart3_clk { |
||||
#clock-cells = <0>; |
||||
reg = <27>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uart4_clk: uart4_clk { |
||||
#clock-cells = <0>; |
||||
reg = <28>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
twi0_clk: twi0_clk { |
||||
reg = <29>; |
||||
#clock-cells = <0>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
twi1_clk: twi1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <30>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
spi0_clk: spi0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <33>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
spi1_clk: spi1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <34>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
tcb0_clk: tcb0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <35>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
tcb1_clk: tcb1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <36>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
pwm_clk: pwm_clk { |
||||
#clock-cells = <0>; |
||||
reg = <38>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
adc_clk: adc_clk { |
||||
#clock-cells = <0>; |
||||
reg = <40>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
uhphs_clk: uhphs_clk { |
||||
#clock-cells = <0>; |
||||
reg = <41>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
udphs_clk: udphs_clk { |
||||
#clock-cells = <0>; |
||||
reg = <42>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
ssc0_clk: ssc0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <43>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
ssc1_clk: ssc1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <44>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
trng_clk: trng_clk { |
||||
#clock-cells = <0>; |
||||
reg = <47>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
pdmic_clk: pdmic_clk { |
||||
#clock-cells = <0>; |
||||
reg = <48>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
i2s0_clk: i2s0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <54>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
i2s1_clk: i2s1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <55>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
can0_clk: can0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <56>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
can1_clk: can1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <57>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
classd_clk: classd_clk { |
||||
#clock-cells = <0>; |
||||
reg = <59>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
}; |
||||
|
||||
periph64ck { |
||||
compatible = "atmel,at91sam9x5-clk-peripheral"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&mck>; |
||||
|
||||
dma0_clk: dma0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <6>; |
||||
}; |
||||
|
||||
dma1_clk: dma1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <7>; |
||||
}; |
||||
|
||||
aes_clk: aes_clk { |
||||
#clock-cells = <0>; |
||||
reg = <9>; |
||||
}; |
||||
|
||||
aesb_clk: aesb_clk { |
||||
#clock-cells = <0>; |
||||
reg = <10>; |
||||
}; |
||||
|
||||
sha_clk: sha_clk { |
||||
#clock-cells = <0>; |
||||
reg = <12>; |
||||
}; |
||||
|
||||
mpddr_clk: mpddr_clk { |
||||
#clock-cells = <0>; |
||||
reg = <13>; |
||||
}; |
||||
|
||||
matrix0_clk: matrix0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <15>; |
||||
}; |
||||
|
||||
sdmmc0_hclk: sdmmc0_hclk { |
||||
#clock-cells = <0>; |
||||
reg = <31>; |
||||
}; |
||||
|
||||
sdmmc1_hclk: sdmmc1_hclk { |
||||
#clock-cells = <0>; |
||||
reg = <32>; |
||||
}; |
||||
|
||||
lcdc_clk: lcdc_clk { |
||||
#clock-cells = <0>; |
||||
reg = <45>; |
||||
}; |
||||
|
||||
isc_clk: isc_clk { |
||||
#clock-cells = <0>; |
||||
reg = <46>; |
||||
}; |
||||
|
||||
qspi0_clk: qspi0_clk { |
||||
#clock-cells = <0>; |
||||
reg = <52>; |
||||
}; |
||||
|
||||
qspi1_clk: qspi1_clk { |
||||
#clock-cells = <0>; |
||||
reg = <53>; |
||||
}; |
||||
}; |
||||
|
||||
gck { |
||||
compatible = "atmel,sama5d2-clk-generated"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
interrupt-parent = <&pmc>; |
||||
clocks = <&main>, <&plla>, <&utmi>, <&mck>; |
||||
|
||||
sdmmc0_gclk: sdmmc0_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <31>; |
||||
}; |
||||
|
||||
sdmmc1_gclk: sdmmc1_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <32>; |
||||
}; |
||||
|
||||
tcb0_gclk: tcb0_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <35>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
tcb1_gclk: tcb1_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <36>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
pwm_gclk: pwm_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <38>; |
||||
atmel,clk-output-range = <0 83000000>; |
||||
}; |
||||
|
||||
pdmic_gclk: pdmic_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <48>; |
||||
}; |
||||
|
||||
i2s0_gclk: i2s0_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <54>; |
||||
}; |
||||
|
||||
i2s1_gclk: i2s1_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <55>; |
||||
}; |
||||
|
||||
can0_gclk: can0_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <56>; |
||||
atmel,clk-output-range = <0 80000000>; |
||||
}; |
||||
|
||||
can1_gclk: can1_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <57>; |
||||
atmel,clk-output-range = <0 80000000>; |
||||
}; |
||||
|
||||
classd_gclk: classd_gclk { |
||||
#clock-cells = <0>; |
||||
reg = <59>; |
||||
atmel,clk-output-range = <0 100000000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
qspi0: spi@f0020000 { |
||||
compatible = "atmel,sama5d2-qspi"; |
||||
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; |
||||
reg-names = "qspi_base", "qspi_mmap"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&qspi0_clk>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
spi0: spi@f8000000 { |
||||
compatible = "atmel,at91rm9200-spi"; |
||||
reg = <0xf8000000 0x100>; |
||||
clocks = <&spi0_clk>; |
||||
clock-names = "spi_clk"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
macb0: ethernet@f8008000 { |
||||
compatible = "cdns,macb"; |
||||
reg = <0xf8008000 0x1000>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&macb0_clk>, <&macb0_clk>; |
||||
clock-names = "hclk", "pclk"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@f8020000 { |
||||
compatible = "atmel,at91sam9260-usart"; |
||||
reg = <0xf8020000 0x100>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c0: i2c@f8028000 { |
||||
compatible = "atmel,sama5d2-i2c"; |
||||
reg = <0xf8028000 0x100>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&twi0_clk>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sckc@f8048050 { |
||||
compatible = "atmel,at91sam9x5-sckc"; |
||||
reg = <0xf8048050 0x4>; |
||||
|
||||
slow_rc_osc: slow_rc_osc { |
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
||||
#clock-cells = <0>; |
||||
clock-frequency = <32768>; |
||||
clock-accuracy = <250000000>; |
||||
atmel,startup-time-usec = <75>; |
||||
}; |
||||
|
||||
slow_osc: slow_osc { |
||||
compatible = "atmel,at91sam9x5-clk-slow-osc"; |
||||
#clock-cells = <0>; |
||||
clocks = <&slow_xtal>; |
||||
atmel,startup-time-usec = <1200000>; |
||||
}; |
||||
|
||||
clk32k: slowck { |
||||
compatible = "atmel,at91sam9x5-clk-slow"; |
||||
#clock-cells = <0>; |
||||
clocks = <&slow_rc_osc &slow_osc>; |
||||
}; |
||||
}; |
||||
|
||||
spi1: spi@fc000000 { |
||||
compatible = "atmel,at91rm9200-spi"; |
||||
reg = <0xfc000000 0x100>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c1: i2c@fc028000 { |
||||
compatible = "atmel,sama5d2-i2c"; |
||||
reg = <0xfc028000 0x100>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&twi1_clk>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
pioA: gpio@fc038000 { |
||||
compatible = "atmel,sama5d2-gpio"; |
||||
reg = <0xfc038000 0x600>; |
||||
clocks = <&pioA_clk>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
|
||||
pinctrl { |
||||
compatible = "atmel,sama5d2-pinctrl"; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,26 @@ |
||||
I2C for Atmel platforms |
||||
|
||||
Required properties : |
||||
- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", |
||||
"atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", |
||||
"atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c". |
||||
- reg: physical base address of the controller and length of memory mapped |
||||
region. |
||||
- #address-cells = <1>; |
||||
- #size-cells = <0>; |
||||
- clocks: phandles to input clocks. |
||||
|
||||
Optional properties: |
||||
- clock-frequency: Desired I2C bus frequency in Hz, default value is 100000. |
||||
- Child nodes conforming to i2c bus binding. |
||||
|
||||
Examples : |
||||
|
||||
i2c0: i2c@f8028000 { |
||||
compatible = "atmel,sama5d2-i2c"; |
||||
reg = <0xf8028000 0x100>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
clocks = <&twi0_clk>; |
||||
clock-frequency = <100000>; |
||||
}; |
||||
@ -0,0 +1,66 @@ |
||||
* Atmel PIO4 Controller |
||||
|
||||
The Atmel PIO4 controller is used to select the function of a pin and to |
||||
configure it. |
||||
|
||||
Required properties: |
||||
- compatible: "atmel,sama5d2-pinctrl". |
||||
- reg: base address and length of the PIO controller. |
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the |
||||
common pinctrl bindings used by client devices. |
||||
|
||||
Subnode format |
||||
Each node (or subnode) will list the pins it needs and how to configured these |
||||
pins. |
||||
|
||||
node { |
||||
pinmux = <PIN_NUMBER_PINMUX>; |
||||
GENERIC_PINCONFIG; |
||||
}; |
||||
|
||||
Required properties: |
||||
- pinmux: integer array. Each integer represents a pin number plus mux and |
||||
ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the |
||||
right representation of the pin. |
||||
|
||||
Optional properties: |
||||
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable, |
||||
bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable, |
||||
input-debounce. |
||||
|
||||
Example: |
||||
|
||||
#include <sama5d2-pinfunc.h> |
||||
|
||||
... |
||||
{ |
||||
spi0: spi@f8000000 { |
||||
cs-gpios = <&pioA 17 0>, <0>, <0>, <0>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_spi0_default>; |
||||
status = "okay"; |
||||
|
||||
spi_flash@0 { |
||||
compatible = "spi-flash"; |
||||
reg = <0>; |
||||
spi-max-frequency = <50000000>; |
||||
}; |
||||
}; |
||||
|
||||
... |
||||
|
||||
pioA: pinctrl@fc038000 { |
||||
compatible = "atmel,sama5d2-pinctrl"; |
||||
reg = <0xfc038000 0x600>; |
||||
|
||||
pinctrl_spi0_default: spi0_default { |
||||
pinmux = <PIN_PA14__SPI0_SPCK>, |
||||
<PIN_PA15__SPI0_MOSI>, |
||||
<PIN_PA16__SPI0_MISO>; |
||||
bias-disable; |
||||
}; |
||||
... |
||||
}; |
||||
}; |
||||
... |
||||
@ -0,0 +1,43 @@ |
||||
config CLK_AT91 |
||||
bool "AT91 clock drivers" |
||||
depends on CLK |
||||
help |
||||
This option is used to enable the AT91 clock driver. |
||||
The driver supports the AT91 clock generator, including |
||||
the oscillators and PLLs, such as main clock, slow clock, |
||||
PLLA, UTMI PLL. Clocks can also be a source clock of other |
||||
clocks a tree structure, such as master clock, usb device |
||||
clock, matrix clock and generic clock. |
||||
Devices can use a common clock API to request a particular |
||||
clock, enable it and get its rate. |
||||
|
||||
config AT91_UTMI |
||||
bool "Support UTMI PLL Clock" |
||||
depends on CLK_AT91 |
||||
help |
||||
This option is used to enable the AT91 UTMI PLL clock |
||||
driver. It is the clock provider of USB, and UPLLCK is the |
||||
output of 480 MHz UTMI PLL, The souce clock of the UTMI |
||||
PLL is the main clock, so the main clock must select the |
||||
fast crystal oscillator to meet the frequency accuracy |
||||
required by USB. |
||||
|
||||
config AT91_H32MX |
||||
bool "Support H32MX 32-bit Matrix Clock" |
||||
depends on CLK_AT91 |
||||
help |
||||
This option is used to enable the AT91 H32MX matrixes |
||||
clock driver. There are H64MX and H32MX matrixes clocks, |
||||
H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit |
||||
matrix clock is to be configured as MCK if MCK does not |
||||
exceed 83 MHz, else it is to be configured as MCK/2. |
||||
|
||||
config AT91_GENERIC_CLK |
||||
bool "Support Generic Clock" |
||||
depends on CLK_AT91 |
||||
help |
||||
This option is used to enable the AT91 generic clock |
||||
driver. Some peripherals may need a second clock source |
||||
that may be different from the system clock. This second |
||||
clock is the generic clock (GCLK) and is managed by |
||||
the PMC via PMC_PCR register. |
||||
@ -0,0 +1,11 @@ |
||||
#
|
||||
# Makefile for at91 specific clk
|
||||
#
|
||||
|
||||
obj-y += pmc.o sckc.o
|
||||
obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
|
||||
obj-y += clk-system.o clk-peripheral.o
|
||||
|
||||
obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
|
||||
obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
|
||||
obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o
|
||||
@ -0,0 +1,162 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define GENERATED_SOURCE_MAX 6 |
||||
#define GENERATED_MAX_DIV 255 |
||||
|
||||
struct generated_clk_priv { |
||||
u32 num_parents; |
||||
}; |
||||
|
||||
static ulong generated_clk_get_rate(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
struct clk parent; |
||||
u32 tmp, gckdiv; |
||||
u8 parent_id; |
||||
int ret; |
||||
|
||||
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); |
||||
tmp = readl(&pmc->pcr); |
||||
parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & |
||||
AT91_PMC_PCR_GCKCSS_MASK; |
||||
gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK; |
||||
|
||||
ret = clk_get_by_index(clk->dev, parent_id, &parent); |
||||
if (ret) |
||||
return 0; |
||||
|
||||
return clk_get_rate(&parent) / (gckdiv + 1); |
||||
} |
||||
|
||||
static ulong generated_clk_set_rate(struct clk *clk, ulong rate) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
struct generated_clk_priv *priv = dev_get_priv(clk->dev); |
||||
struct clk parent, best_parent; |
||||
ulong tmp_rate, best_rate = rate, parent_rate; |
||||
int tmp_diff, best_diff = -1; |
||||
u32 div, best_div = 0; |
||||
u8 best_parent_id = 0; |
||||
u8 i; |
||||
u32 tmp; |
||||
int ret; |
||||
|
||||
for (i = 0; i < priv->num_parents; i++) { |
||||
ret = clk_get_by_index(clk->dev, i, &parent); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
parent_rate = clk_get_rate(&parent); |
||||
if (IS_ERR_VALUE(parent_rate)) |
||||
return parent_rate; |
||||
|
||||
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { |
||||
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); |
||||
if (rate < tmp_rate) |
||||
continue; |
||||
tmp_diff = rate - tmp_rate; |
||||
|
||||
if (best_diff < 0 || best_diff > tmp_diff) { |
||||
best_rate = tmp_rate; |
||||
best_diff = tmp_diff; |
||||
|
||||
best_div = div - 1; |
||||
best_parent = parent; |
||||
best_parent_id = i; |
||||
} |
||||
|
||||
if (!best_diff || tmp_rate < rate) |
||||
break; |
||||
} |
||||
|
||||
if (!best_diff) |
||||
break; |
||||
} |
||||
|
||||
debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n", |
||||
best_parent.dev->name, best_rate, best_div); |
||||
|
||||
ret = clk_enable(&best_parent); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); |
||||
tmp = readl(&pmc->pcr); |
||||
tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS); |
||||
tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) | |
||||
AT91_PMC_PCR_CMD_WRITE | |
||||
AT91_PMC_PCR_GCKDIV_(best_div) | |
||||
AT91_PMC_PCR_GCKEN; |
||||
writel(tmp, &pmc->pcr); |
||||
|
||||
while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY)) |
||||
; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct clk_ops generated_clk_ops = { |
||||
.get_rate = generated_clk_get_rate, |
||||
.set_rate = generated_clk_set_rate, |
||||
}; |
||||
|
||||
static int generated_clk_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct generated_clk_priv *priv = dev_get_priv(dev); |
||||
u32 cells[GENERATED_SOURCE_MAX]; |
||||
u32 num_parents; |
||||
|
||||
num_parents = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, |
||||
"clocks", cells, |
||||
GENERATED_SOURCE_MAX); |
||||
|
||||
if (!num_parents) |
||||
return -1; |
||||
|
||||
priv->num_parents = num_parents; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int generated_clk_bind(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_clk_node_bind(dev); |
||||
} |
||||
|
||||
static int generated_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id generated_clk_match[] = { |
||||
{ .compatible = "atmel,sama5d2-clk-generated" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(generated_clk) = { |
||||
.name = "generated-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = generated_clk_match, |
||||
.bind = generated_clk_bind, |
||||
.probe = generated_clk_probe, |
||||
.ofdata_to_platdata = generated_clk_ofdata_to_platdata, |
||||
.priv_auto_alloc_size = sizeof(struct generated_clk_priv), |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &generated_clk_ops, |
||||
}; |
||||
@ -0,0 +1,56 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <dm/util.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define H32MX_MAX_FREQ 90000000 |
||||
|
||||
static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
ulong rate = gd->arch.mck_rate_hz; |
||||
|
||||
if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) |
||||
rate /= 2; |
||||
|
||||
if (rate > H32MX_MAX_FREQ) |
||||
dm_warn("H32MX clock is too fast\n"); |
||||
|
||||
return rate; |
||||
} |
||||
|
||||
static struct clk_ops sama5d4_h32mx_clk_ops = { |
||||
.get_rate = sama5d4_h32mx_clk_get_rate, |
||||
}; |
||||
|
||||
static int sama5d4_h32mx_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id sama5d4_h32mx_clk_match[] = { |
||||
{ .compatible = "atmel,sama5d4-clk-h32mx" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sama5d4_h32mx_clk) = { |
||||
.name = "sama5d4-h32mx-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = sama5d4_h32mx_clk_match, |
||||
.probe = sama5d4_h32mx_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &sama5d4_h32mx_clk_ops, |
||||
}; |
||||
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int main_osc_clk_enable(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
|
||||
if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) |
||||
return 0; |
||||
|
||||
return -EINVAL; |
||||
} |
||||
|
||||
static ulong main_osc_clk_get_rate(struct clk *clk) |
||||
{ |
||||
return gd->arch.main_clk_rate_hz; |
||||
} |
||||
|
||||
static struct clk_ops main_osc_clk_ops = { |
||||
.enable = main_osc_clk_enable, |
||||
.get_rate = main_osc_clk_get_rate, |
||||
}; |
||||
|
||||
static int main_osc_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id main_osc_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-clk-main" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = { |
||||
.name = "at91sam9x5-main-osc-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = main_osc_clk_match, |
||||
.probe = main_osc_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &main_osc_clk_ops, |
||||
}; |
||||
@ -0,0 +1,33 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static ulong at91_master_clk_get_rate(struct clk *clk) |
||||
{ |
||||
return gd->arch.mck_rate_hz; |
||||
} |
||||
|
||||
static struct clk_ops at91_master_clk_ops = { |
||||
.get_rate = at91_master_clk_get_rate, |
||||
}; |
||||
|
||||
static const struct udevice_id at91_master_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-clk-master" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_master_clk) = { |
||||
.name = "at91-master-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = at91_master_clk_match, |
||||
.ops = &at91_master_clk_ops, |
||||
}; |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
#define PERIPHERAL_ID_MIN 2 |
||||
#define PERIPHERAL_ID_MAX 31 |
||||
#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) |
||||
|
||||
static int sam9x5_periph_clk_enable(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
|
||||
if (clk->id < PERIPHERAL_ID_MIN) |
||||
return -1; |
||||
|
||||
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); |
||||
setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct clk_ops sam9x5_periph_clk_ops = { |
||||
.enable = sam9x5_periph_clk_enable, |
||||
}; |
||||
|
||||
static int sam9x5_periph_clk_bind(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_clk_node_bind(dev); |
||||
} |
||||
|
||||
static int sam9x5_periph_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id sam9x5_periph_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-clk-peripheral" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sam9x5_periph_clk) = { |
||||
.name = "sam9x5-periph-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = sam9x5_periph_clk_match, |
||||
.bind = sam9x5_periph_clk_bind, |
||||
.probe = sam9x5_periph_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &sam9x5_periph_clk_ops, |
||||
}; |
||||
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int plla_clk_enable(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
|
||||
if (readl(&pmc->sr) & AT91_PMC_LOCKA) |
||||
return 0; |
||||
|
||||
return -EINVAL; |
||||
} |
||||
|
||||
static ulong plla_clk_get_rate(struct clk *clk) |
||||
{ |
||||
return gd->arch.plla_rate_hz; |
||||
} |
||||
|
||||
static struct clk_ops plla_clk_ops = { |
||||
.enable = plla_clk_enable, |
||||
.get_rate = plla_clk_get_rate, |
||||
}; |
||||
|
||||
static int plla_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id plla_clk_match[] = { |
||||
{ .compatible = "atmel,sama5d3-clk-pll" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_plla_clk) = { |
||||
.name = "at91-plla-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = plla_clk_match, |
||||
.probe = plla_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &plla_clk_ops, |
||||
}; |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
|
||||
static int at91_slow_clk_enable(struct clk *clk) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
static ulong at91_slow_clk_get_rate(struct clk *clk) |
||||
{ |
||||
return CONFIG_SYS_AT91_SLOW_CLOCK; |
||||
} |
||||
|
||||
static struct clk_ops at91_slow_clk_ops = { |
||||
.enable = at91_slow_clk_enable, |
||||
.get_rate = at91_slow_clk_get_rate, |
||||
}; |
||||
|
||||
static const struct udevice_id at91_slow_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-clk-slow" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_slow_clk) = { |
||||
.name = "at91-slow-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = at91_slow_clk_match, |
||||
.ops = &at91_slow_clk_ops, |
||||
}; |
||||
@ -0,0 +1,76 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
#define SYSTEM_MAX_ID 31 |
||||
|
||||
static inline int is_pck(int id) |
||||
{ |
||||
return (id >= 8) && (id <= 15); |
||||
} |
||||
|
||||
static int at91_system_clk_enable(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
u32 mask; |
||||
|
||||
if (clk->id > SYSTEM_MAX_ID) |
||||
return -EINVAL; |
||||
|
||||
mask = BIT(clk->id); |
||||
|
||||
writel(mask, &pmc->scer); |
||||
|
||||
/**
|
||||
* For the programmable clocks the Ready status in the PMC |
||||
* status register should be checked after enabling. |
||||
* For other clocks this is unnecessary. |
||||
*/ |
||||
if (!is_pck(clk->id)) |
||||
return 0; |
||||
|
||||
while (!(readl(&pmc->sr) & mask)) |
||||
; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct clk_ops at91_system_clk_ops = { |
||||
.enable = at91_system_clk_enable, |
||||
}; |
||||
|
||||
static int at91_system_clk_bind(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_clk_node_bind(dev); |
||||
} |
||||
|
||||
static int at91_system_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id at91_system_clk_match[] = { |
||||
{ .compatible = "atmel,at91rm9200-clk-system" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_system_clk) = { |
||||
.name = "at91-system-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = at91_system_clk_match, |
||||
.bind = at91_system_clk_bind, |
||||
.probe = at91_system_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &at91_system_clk_ops, |
||||
}; |
||||
@ -0,0 +1,67 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <linux/io.h> |
||||
#include <mach/at91_pmc.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UTMI_FIXED_MUL 40 |
||||
|
||||
static int utmi_clk_enable(struct clk *clk) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(clk->dev); |
||||
struct at91_pmc *pmc = plat->reg_base; |
||||
u32 tmp; |
||||
|
||||
if (readl(&pmc->sr) & AT91_PMC_LOCKU) |
||||
return 0; |
||||
|
||||
tmp = readl(&pmc->uckr); |
||||
tmp |= AT91_PMC_UPLLEN | |
||||
AT91_PMC_UPLLCOUNT | |
||||
AT91_PMC_BIASEN; |
||||
writel(tmp, &pmc->uckr); |
||||
|
||||
while (!(readl(&pmc->sr) & AT91_PMC_LOCKU)) |
||||
; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static ulong utmi_clk_get_rate(struct clk *clk) |
||||
{ |
||||
return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL; |
||||
} |
||||
|
||||
static struct clk_ops utmi_clk_ops = { |
||||
.enable = utmi_clk_enable, |
||||
.get_rate = utmi_clk_get_rate, |
||||
}; |
||||
|
||||
static int utmi_clk_probe(struct udevice *dev) |
||||
{ |
||||
return at91_pmc_core_probe(dev); |
||||
} |
||||
|
||||
static const struct udevice_id utmi_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-clk-utmi" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { |
||||
.name = "at91sam9x5-utmi-clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = utmi_clk_match, |
||||
.probe = utmi_clk_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct pmc_platdata), |
||||
.ops = &utmi_clk_ops, |
||||
}; |
||||
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <dm/lists.h> |
||||
#include <dm/root.h> |
||||
#include "pmc.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int at91_pmc_bind(struct udevice *dev) |
||||
{ |
||||
return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); |
||||
} |
||||
|
||||
static const struct udevice_id at91_pmc_match[] = { |
||||
{ .compatible = "atmel,sama5d2-pmc" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_pmc) = { |
||||
.name = "at91-pmc-core", |
||||
.id = UCLASS_CLK, |
||||
.of_match = at91_pmc_match, |
||||
.bind = at91_pmc_bind, |
||||
}; |
||||
|
||||
int at91_pmc_core_probe(struct udevice *dev) |
||||
{ |
||||
struct pmc_platdata *plat = dev_get_platdata(dev); |
||||
|
||||
dev = dev_get_parent(dev); |
||||
|
||||
plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int at91_pmc_clk_node_bind(struct udevice *dev) |
||||
{ |
||||
const void *fdt = gd->fdt_blob; |
||||
int offset = dev->of_offset; |
||||
const char *name; |
||||
int ret; |
||||
|
||||
for (offset = fdt_first_subnode(fdt, offset); |
||||
offset > 0; |
||||
offset = fdt_next_subnode(fdt, offset)) { |
||||
name = fdt_get_name(fdt, offset, NULL); |
||||
if (!name) |
||||
return -EINVAL; |
||||
|
||||
ret = device_bind_driver_to_node(dev, "clk", name, |
||||
offset, NULL); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_DRIVER(clk_generic) = { |
||||
.id = UCLASS_CLK, |
||||
.name = "clk", |
||||
}; |
||||
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __AT91_PMC_H__ |
||||
#define __AT91_PMC_H__ |
||||
|
||||
struct pmc_platdata { |
||||
struct at91_pmc *reg_base; |
||||
}; |
||||
|
||||
int at91_pmc_core_probe(struct udevice *dev); |
||||
int at91_pmc_clk_node_bind(struct udevice *dev); |
||||
|
||||
#endif |
||||
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm/device.h> |
||||
#include <dm/root.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int at91_sckc_clk_bind(struct udevice *dev) |
||||
{ |
||||
return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); |
||||
} |
||||
|
||||
static const struct udevice_id at91_sckc_clk_match[] = { |
||||
{ .compatible = "atmel,at91sam9x5-sckc" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(at91_sckc_clk) = { |
||||
.name = "at91_sckc_clk", |
||||
.id = UCLASS_CLK, |
||||
.of_match = at91_sckc_clk_match, |
||||
.bind = at91_sckc_clk_bind, |
||||
}; |
||||
@ -0,0 +1,338 @@ |
||||
/*
|
||||
* Atmel I2C driver. |
||||
* |
||||
* (C) Copyright 2016 Songjun Wu <songjun.wu@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <clk_client.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <i2c.h> |
||||
#include <linux/bitops.h> |
||||
#include <mach/clk.h> |
||||
|
||||
#include "at91_i2c.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define I2C_TIMEOUT_MS 100 |
||||
|
||||
static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status) |
||||
{ |
||||
struct at91_i2c_regs *reg = bus->regs; |
||||
ulong start_time = get_timer(0); |
||||
u32 sr; |
||||
|
||||
bus->status = 0; |
||||
|
||||
do { |
||||
sr = readl(®->sr); |
||||
bus->status |= sr; |
||||
|
||||
if (sr & TWI_SR_NACK) |
||||
return -EREMOTEIO; |
||||
else if (sr & status) |
||||
return 0; |
||||
} while (get_timer(start_time) < I2C_TIMEOUT_MS); |
||||
|
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg) |
||||
{ |
||||
struct at91_i2c_regs *reg = bus->regs; |
||||
bool is_read = msg->flags & I2C_M_RD; |
||||
u32 i; |
||||
int ret = 0; |
||||
|
||||
readl(®->sr); |
||||
if (is_read) { |
||||
writel(TWI_CR_START, ®->cr); |
||||
|
||||
for (i = 0; !ret && i < (msg->len - 1); i++) { |
||||
ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); |
||||
msg->buf[i] = readl(®->rhr); |
||||
} |
||||
|
||||
if (ret) |
||||
goto error; |
||||
|
||||
writel(TWI_CR_STOP, ®->cr); |
||||
|
||||
ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); |
||||
if (ret) |
||||
goto error; |
||||
|
||||
msg->buf[i] = readl(®->rhr); |
||||
|
||||
} else { |
||||
writel(msg->buf[0], ®->thr); |
||||
for (i = 1; !ret && (i < msg->len); i++) { |
||||
writel(msg->buf[i], ®->thr); |
||||
ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY); |
||||
} |
||||
|
||||
if (ret) |
||||
goto error; |
||||
|
||||
writel(TWI_CR_STOP, ®->cr); |
||||
} |
||||
|
||||
if (!ret) |
||||
ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP); |
||||
|
||||
if (ret) |
||||
goto error; |
||||
|
||||
if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) { |
||||
ret = -EIO; |
||||
goto error; |
||||
} |
||||
|
||||
return 0; |
||||
|
||||
error: |
||||
if (bus->status & TWI_SR_LOCK) |
||||
writel(TWI_CR_LOCKCLR, ®->cr); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
struct at91_i2c_regs *reg = bus->regs; |
||||
struct i2c_msg *m_start = msg; |
||||
bool is_read; |
||||
u32 int_addr_flag = 0; |
||||
int ret = 0; |
||||
|
||||
if (nmsgs == 2) { |
||||
int internal_address = 0; |
||||
int i; |
||||
|
||||
/* 1st msg is put into the internal address, start with 2nd */ |
||||
m_start = &msg[1]; |
||||
|
||||
/* the max length of internal address is 3 bytes */ |
||||
if (msg->len > 3) |
||||
return -EFAULT; |
||||
|
||||
for (i = 0; i < msg->len; ++i) { |
||||
const unsigned addr = msg->buf[msg->len - 1 - i]; |
||||
|
||||
internal_address |= addr << (8 * i); |
||||
int_addr_flag += TWI_MMR_IADRSZ_1; |
||||
} |
||||
|
||||
writel(internal_address, ®->iadr); |
||||
} |
||||
|
||||
is_read = m_start->flags & I2C_M_RD; |
||||
|
||||
writel((m_start->addr << 16) | int_addr_flag | |
||||
(is_read ? TWI_MMR_MREAD : 0), ®->mmr); |
||||
|
||||
ret = at91_i2c_xfer_msg(bus, m_start); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/*
|
||||
* Calculate symmetric clock as stated in datasheet: |
||||
* twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) |
||||
*/ |
||||
static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
const struct at91_i2c_pdata *pdata = bus->pdata; |
||||
int offset = pdata->clk_offset; |
||||
int max_ckdiv = pdata->clk_max_div; |
||||
int ckdiv, cdiv, div; |
||||
unsigned long src_rate; |
||||
|
||||
src_rate = bus->bus_clk_rate; |
||||
|
||||
div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset); |
||||
ckdiv = fls(div >> 8); |
||||
cdiv = div >> ckdiv; |
||||
|
||||
if (ckdiv > max_ckdiv) { |
||||
ckdiv = max_ckdiv; |
||||
cdiv = 255; |
||||
} |
||||
|
||||
bus->speed = DIV_ROUND_UP(src_rate, |
||||
(cdiv * (1 << ckdiv) + offset) * 2); |
||||
|
||||
bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv; |
||||
} |
||||
|
||||
static int at91_i2c_enable_clk(struct udevice *dev) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
struct udevice *dev_clk; |
||||
struct clk clk; |
||||
ulong clk_rate; |
||||
int periph; |
||||
int ret; |
||||
|
||||
ret = clk_get_by_index(dev, 0, &clk); |
||||
if (ret) |
||||
return -EINVAL; |
||||
|
||||
periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); |
||||
if (periph < 0) |
||||
return -EINVAL; |
||||
|
||||
dev_clk = dev_get_parent(clk.dev); |
||||
ret = clk_request(dev_clk, &clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
clk.id = periph; |
||||
ret = clk_enable(&clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = clk_get_by_index(dev_clk, 0, &clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
clk_rate = clk_get_rate(&clk); |
||||
if (!clk_rate) |
||||
return -ENODEV; |
||||
|
||||
bus->bus_clk_rate = clk_rate; |
||||
|
||||
clk_free(&clk); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int at91_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
struct at91_i2c_regs *reg = bus->regs; |
||||
int ret; |
||||
|
||||
ret = at91_i2c_enable_clk(dev); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
writel(TWI_CR_SWRST, ®->cr); |
||||
|
||||
at91_calc_i2c_clock(dev, bus->clock_frequency); |
||||
|
||||
writel(bus->cwgr_val, ®->cwgr); |
||||
writel(TWI_CR_MSEN, ®->cr); |
||||
writel(TWI_CR_SVDIS, ®->cr); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
|
||||
at91_calc_i2c_clock(dev, speed); |
||||
|
||||
writel(bus->cwgr_val, &bus->regs->cwgr); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int at91_i2c_get_bus_speed(struct udevice *dev) |
||||
{ |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
|
||||
return bus->speed; |
||||
} |
||||
|
||||
static int at91_i2c_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
const void *blob = gd->fdt_blob; |
||||
struct at91_i2c_bus *bus = dev_get_priv(dev); |
||||
int node = dev->of_offset; |
||||
|
||||
bus->regs = (struct at91_i2c_regs *)dev_get_addr(dev); |
||||
bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev); |
||||
bus->clock_frequency = fdtdec_get_int(blob, node, |
||||
"clock-frequency", 100000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_i2c_ops at91_i2c_ops = { |
||||
.xfer = at91_i2c_xfer, |
||||
.probe_chip = at91_i2c_probe, |
||||
.set_bus_speed = at91_i2c_set_bus_speed, |
||||
.get_bus_speed = at91_i2c_get_bus_speed, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91rm9200_config = { |
||||
.clk_max_div = 5, |
||||
.clk_offset = 3, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91sam9261_config = { |
||||
.clk_max_div = 5, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91sam9260_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91sam9g20_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91sam9g10_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata at91sam9x5_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata sama5d4_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 4, |
||||
}; |
||||
|
||||
static const struct at91_i2c_pdata sama5d2_config = { |
||||
.clk_max_div = 7, |
||||
.clk_offset = 3, |
||||
}; |
||||
|
||||
static const struct udevice_id at91_i2c_ids[] = { |
||||
{ .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config }, |
||||
{ .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config }, |
||||
{ .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config }, |
||||
{ .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config }, |
||||
{ .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config }, |
||||
{ .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config }, |
||||
{ .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config }, |
||||
{ .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(i2c_at91) = { |
||||
.name = "i2c_at91", |
||||
.id = UCLASS_I2C, |
||||
.of_match = at91_i2c_ids, |
||||
.ofdata_to_platdata = at91_i2c_ofdata_to_platdata, |
||||
.per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), |
||||
.priv_auto_alloc_size = sizeof(struct at91_i2c_bus), |
||||
.ops = &at91_i2c_ops, |
||||
}; |
||||
@ -0,0 +1,77 @@ |
||||
#ifndef _AT91_I2C_H |
||||
#define _AT91_I2C_H |
||||
|
||||
#define TWI_CR_START BIT(0) /* Send a Start Condition */ |
||||
#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ |
||||
#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ |
||||
#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ |
||||
#define TWI_CR_SWRST BIT(7) /* Software Reset */ |
||||
#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ |
||||
#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ |
||||
#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ |
||||
|
||||
#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ |
||||
#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ |
||||
|
||||
#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ |
||||
#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ |
||||
#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ |
||||
#define TWI_SR_OVRE BIT(6) /* Overrun Error */ |
||||
#define TWI_SR_UNRE BIT(7) /* Underrun Error */ |
||||
#define TWI_SR_NACK BIT(8) /* Not Acknowledged */ |
||||
#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ |
||||
|
||||
#define TWI_ACR_DATAL(len) ((len) & 0xff) |
||||
#define TWI_ACR_DIR_READ BIT(8) |
||||
|
||||
#define TWI_CWGR_HOLD_MAX 0x1f |
||||
#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) |
||||
|
||||
struct at91_i2c_regs { |
||||
u32 cr; |
||||
u32 mmr; |
||||
u32 smr; |
||||
u32 iadr; |
||||
u32 cwgr; |
||||
u32 rev_0[3]; |
||||
u32 sr; |
||||
u32 ier; |
||||
u32 idr; |
||||
u32 imr; |
||||
u32 rhr; |
||||
u32 thr; |
||||
u32 smbtr; |
||||
u32 rev_1; |
||||
u32 acr; |
||||
u32 filtr; |
||||
u32 rev_2; |
||||
u32 swmr; |
||||
u32 fmr; |
||||
u32 flr; |
||||
u32 rev_3; |
||||
u32 fsr; |
||||
u32 fier; |
||||
u32 fidr; |
||||
u32 fimr; |
||||
u32 rev_4[29]; |
||||
u32 wpmr; |
||||
u32 wpsr; |
||||
u32 rev_5[6]; |
||||
}; |
||||
|
||||
struct at91_i2c_pdata { |
||||
unsigned clk_max_div; |
||||
unsigned clk_offset; |
||||
}; |
||||
|
||||
struct at91_i2c_bus { |
||||
struct at91_i2c_regs *regs; |
||||
u32 status; |
||||
ulong bus_clk_rate; |
||||
u32 clock_frequency; |
||||
u32 speed; |
||||
u32 cwgr_val; |
||||
const struct at91_i2c_pdata *pdata; |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,182 @@ |
||||
/*
|
||||
* Atmel PIO4 pinctrl driver |
||||
* |
||||
* Copyright (C) 2016 Atmel Corporation |
||||
* Wenyou.Yang <wenyou.yang@atmel.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm/device.h> |
||||
#include <dm/pinctrl.h> |
||||
#include <linux/io.h> |
||||
#include <linux/err.h> |
||||
#include <mach/atmel_pio4.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Warning: |
||||
* In order to not introduce confusion between Atmel PIO groups and pinctrl |
||||
* framework groups, Atmel PIO groups will be called banks. |
||||
*/ |
||||
|
||||
struct atmel_pio4_platdata { |
||||
struct atmel_pio4_port *reg_base; |
||||
}; |
||||
|
||||
static const struct pinconf_param conf_params[] = { |
||||
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, |
||||
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, |
||||
{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, |
||||
{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, |
||||
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, |
||||
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, |
||||
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, |
||||
}; |
||||
|
||||
static u32 atmel_pinctrl_get_pinconf(const void *blob, int node) |
||||
{ |
||||
const struct pinconf_param *params; |
||||
u32 param, arg, conf = 0; |
||||
u32 i; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(conf_params); i++) { |
||||
params = &conf_params[i]; |
||||
if (!fdt_get_property(blob, node, params->property, NULL)) |
||||
continue; |
||||
|
||||
param = params->param; |
||||
arg = params->default_value; |
||||
|
||||
switch (param) { |
||||
case PIN_CONFIG_BIAS_DISABLE: |
||||
conf &= (~ATMEL_PIO_PUEN_MASK); |
||||
conf &= (~ATMEL_PIO_PDEN_MASK); |
||||
break; |
||||
case PIN_CONFIG_BIAS_PULL_UP: |
||||
conf |= ATMEL_PIO_PUEN_MASK; |
||||
break; |
||||
case PIN_CONFIG_BIAS_PULL_DOWN: |
||||
conf |= ATMEL_PIO_PDEN_MASK; |
||||
break; |
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
||||
if (arg == 0) |
||||
conf &= (~ATMEL_PIO_OPD_MASK); |
||||
else |
||||
conf |= ATMEL_PIO_OPD_MASK; |
||||
break; |
||||
case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
||||
if (arg == 0) |
||||
conf |= ATMEL_PIO_SCHMITT_MASK; |
||||
else |
||||
conf &= (~ATMEL_PIO_SCHMITT_MASK); |
||||
break; |
||||
case PIN_CONFIG_INPUT_DEBOUNCE: |
||||
if (arg == 0) { |
||||
conf &= (~ATMEL_PIO_IFEN_MASK); |
||||
conf &= (~ATMEL_PIO_IFSCEN_MASK); |
||||
} else { |
||||
conf |= ATMEL_PIO_IFEN_MASK; |
||||
conf |= ATMEL_PIO_IFSCEN_MASK; |
||||
} |
||||
break; |
||||
default: |
||||
printf("%s: Unsupported configuration parameter: %u\n", |
||||
__func__, param); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return conf; |
||||
} |
||||
|
||||
static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, |
||||
u32 bank) |
||||
{ |
||||
struct atmel_pio4_platdata *plat = dev_get_platdata(dev); |
||||
struct atmel_pio4_port *bank_base = |
||||
(struct atmel_pio4_port *)((u32)plat->reg_base + |
||||
ATMEL_PIO_BANK_OFFSET * bank); |
||||
|
||||
return bank_base; |
||||
} |
||||
|
||||
#define MAX_PINMUX_ENTRIES 40 |
||||
|
||||
static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) |
||||
{ |
||||
struct atmel_pio4_port *bank_base; |
||||
const void *blob = gd->fdt_blob; |
||||
int node = config->of_offset; |
||||
u32 offset, func, bank, line; |
||||
u32 cells[MAX_PINMUX_ENTRIES]; |
||||
u32 i, conf; |
||||
int count; |
||||
|
||||
conf = atmel_pinctrl_get_pinconf(blob, node); |
||||
|
||||
count = fdtdec_get_int_array_count(blob, node, "pinmux", |
||||
cells, ARRAY_SIZE(cells)); |
||||
if (count < 0) { |
||||
printf("%s: bad pinmux array %d\n", __func__, count); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
if (count > MAX_PINMUX_ENTRIES) { |
||||
printf("%s: unsupported pinmux array count %d\n", |
||||
__func__, count); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
for (i = 0 ; i < count; i++) { |
||||
offset = ATMEL_GET_PIN_NO(cells[i]); |
||||
func = ATMEL_GET_PIN_FUNC(cells[i]); |
||||
|
||||
bank = ATMEL_PIO_BANK(offset); |
||||
line = ATMEL_PIO_LINE(offset); |
||||
|
||||
bank_base = atmel_pio4_bank_base(dev, bank); |
||||
|
||||
writel(BIT(line), &bank_base->mskr); |
||||
conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); |
||||
conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK); |
||||
writel(conf, &bank_base->cfgr); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
const struct pinctrl_ops atmel_pinctrl_ops = { |
||||
.set_state = atmel_pinctrl_set_state, |
||||
}; |
||||
|
||||
static int atmel_pinctrl_probe(struct udevice *dev) |
||||
{ |
||||
struct atmel_pio4_platdata *plat = dev_get_platdata(dev); |
||||
fdt_addr_t addr_base; |
||||
|
||||
dev = dev_get_parent(dev); |
||||
addr_base = dev_get_addr(dev); |
||||
if (addr_base == FDT_ADDR_T_NONE) |
||||
return -EINVAL; |
||||
|
||||
plat->reg_base = (struct atmel_pio4_port *)addr_base; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id atmel_pinctrl_match[] = { |
||||
{ .compatible = "atmel,sama5d2-pinctrl" }, |
||||
{} |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(atmel_pinctrl) = { |
||||
.name = "pinctrl_atmel_pio4", |
||||
.id = UCLASS_PINCTRL, |
||||
.of_match = atmel_pinctrl_match, |
||||
.probe = atmel_pinctrl_probe, |
||||
.platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata), |
||||
.ops = &atmel_pinctrl_ops, |
||||
}; |
||||
Loading…
Reference in new issue