This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/*
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* Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <mapmem.h> |
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#include <asm/arch/timer.h> |
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#include <dt-structs.h> |
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#include <timer.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct rockchip_timer_plat { |
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struct dtd_rockchip_rk3368_timer dtd; |
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}; |
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#endif |
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/* Driver private data. Contains timer id. Could be either 0 or 1. */ |
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struct rockchip_timer_priv { |
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struct rk_timer *timer; |
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}; |
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static int rockchip_timer_get_count(struct udevice *dev, u64 *count) |
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{ |
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struct rockchip_timer_priv *priv = dev_get_priv(dev); |
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uint64_t timebase_h, timebase_l; |
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uint64_t cntr; |
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timebase_l = readl(&priv->timer->timer_curr_value0); |
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timebase_h = readl(&priv->timer->timer_curr_value1); |
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/* timers are down-counting */ |
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cntr = timebase_h << 32 | timebase_l; |
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*count = ~0ull - cntr; |
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return 0; |
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} |
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static int rockchip_clk_ofdata_to_platdata(struct udevice *dev) |
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{ |
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#if !CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct rockchip_timer_priv *priv = dev_get_priv(dev); |
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priv->timer = (struct rk_timer *)devfdt_get_addr(dev); |
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#endif |
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return 0; |
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} |
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static int rockchip_timer_start(struct udevice *dev) |
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{ |
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struct rockchip_timer_priv *priv = dev_get_priv(dev); |
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const uint64_t reload_val = ~0uLL; |
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const uint32_t reload_val_l = reload_val & 0xffffffff; |
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const uint32_t reload_val_h = reload_val >> 32; |
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/* disable timer and reset all control */ |
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writel(0, &priv->timer->timer_ctrl_reg); |
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/* write reload value */ |
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writel(reload_val_l, &priv->timer->timer_load_count0); |
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writel(reload_val_h, &priv->timer->timer_load_count1); |
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/* enable timer */ |
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writel(1, &priv->timer->timer_ctrl_reg); |
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return 0; |
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} |
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static int rockchip_timer_probe(struct udevice *dev) |
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{ |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct rockchip_timer_priv *priv = dev_get_priv(dev); |
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struct rockchip_timer_plat *plat = dev_get_platdata(dev); |
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priv->timer = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]); |
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uc_priv->clock_rate = plat->dtd.clock_frequency; |
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#endif |
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return rockchip_timer_start(dev); |
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} |
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static const struct timer_ops rockchip_timer_ops = { |
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.get_count = rockchip_timer_get_count, |
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}; |
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static const struct udevice_id rockchip_timer_ids[] = { |
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{ .compatible = "rockchip,rk3368-timer" }, |
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{} |
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}; |
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U_BOOT_DRIVER(arc_timer) = { |
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.name = "rockchip_rk3368_timer", |
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.id = UCLASS_TIMER, |
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.of_match = rockchip_timer_ids, |
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.probe = rockchip_timer_probe, |
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.ops = &rockchip_timer_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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.priv_auto_alloc_size = sizeof(struct rockchip_timer_priv), |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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.platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat), |
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#endif |
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.ofdata_to_platdata = rockchip_clk_ofdata_to_platdata, |
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}; |
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