board: ti: amx3xx: Remove multiple EEPROM reads

Detect the board very early and avoid reading eeprom multiple times.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
master
Lokesh Vutla 8 years ago committed by Tom Rini
parent b64a7cb92d
commit 140d76a9ee
  1. 3
      arch/arm/cpu/armv7/am33xx/board.c
  2. 1
      arch/arm/include/asm/arch-am33xx/sys_proto.h
  3. 32
      board/ti/am335x/board.c
  4. 15
      board/ti/am43xx/board.c

@ -288,6 +288,9 @@ void early_system_init(void)
set_uart_mux_conf();
setup_early_clocks();
uart_soft_reset();
#ifdef CONFIG_TI_I2C_BOARD_DETECT
do_board_detect();
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();

@ -45,3 +45,4 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
void do_board_detect(void);

@ -64,10 +64,16 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/*
* Read header information from EEPROM into global structure.
*/
static inline int __maybe_unused read_eeprom(void)
#ifdef CONFIG_TI_I2C_BOARD_DETECT
void do_board_detect(void)
{
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
printf("ti_i2c_eeprom_init failed\n");
}
#endif
#ifndef CONFIG_DM_SERIAL
struct serial_device *default_serial_console(void)
@ -248,9 +254,6 @@ void am33xx_spl_board_init(void)
{
int mpu_vdd;
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
@ -388,11 +391,6 @@ void am33xx_spl_board_init(void)
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk())
return &dpll_ddr_evm_sk;
else if (board_is_bone_lt() || board_is_icev2())
@ -422,9 +420,6 @@ void set_uart_mux_conf(void)
void set_mux_conf_regs(void)
{
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux();
}
@ -462,9 +457,6 @@ const struct ctrl_ioregs ioregs = {
void sdram_init(void)
{
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@ -642,13 +634,8 @@ int board_late_init(void)
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
int rc;
char *name = NULL;
rc = read_eeprom();
if (rc)
puts("Could not get board ID.\n");
if (board_is_bbg1())
name = "BBG1";
set_board_info_env(name);
@ -779,9 +766,6 @@ int board_eth_init(bd_t *bis)
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
#ifdef CONFIG_DRIVER_TI_CPSW
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
if (board_is_bone() || board_is_bone_lt() ||
board_is_idk()) {
writel(MII_MODE_ENABLE, &cdev->miisel);

@ -39,10 +39,13 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/*
* Read header information from EEPROM into global structure.
*/
static inline int __maybe_unused read_eeprom(void)
#ifdef CONFIG_TI_I2C_BOARD_DETECT
void do_board_detect(void)
{
return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
printf("ti_i2c_eeprom_init failed\n");
}
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
@ -337,9 +340,6 @@ const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();
if (read_eeprom() < 0)
return NULL;
if (board_is_eposevm())
return &epos_evm_dpll_ddr[ind];
else if (board_is_evm() || board_is_sk())
@ -495,9 +495,6 @@ void scale_vcores(void)
{
const struct dpll_params *mpu_params;
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
/* Ensure I2C is initialized for PMIC configuration */
gpi2c_init();
@ -537,8 +534,6 @@ static void enable_vtt_regulator(void)
void sdram_init(void)
{
if (read_eeprom() < 0)
return;
/*
* EPOS EVM has 1GB LPDDR2 connected to EMIF.
* GP EMV has 1GB DDR3 connected to EMIF

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