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@ -158,6 +158,293 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, |
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serdes_prtcl_map[NONE] = 1; |
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} |
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__weak int get_serdes_volt(void) |
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{ |
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return -1; |
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} |
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__weak int set_serdes_volt(int svdd) |
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{ |
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return -1; |
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} |
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#define LNAGCR0_RT_RSTB 0x00600000 |
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#define RSTCTL_RESET_MASK 0x000000E0 |
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#define RSTCTL_RSTREQ 0x80000000 |
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#define RSTCTL_RST_DONE 0x40000000 |
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#define RSTCTL_RSTERR 0x20000000 |
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#define RSTCTL_SDEN 0x00000020 |
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#define RSTCTL_SDRST_B 0x00000040 |
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#define RSTCTL_PLLRST_B 0x00000080 |
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#define TCALCR_CALRST_B 0x08000000 |
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struct serdes_prctl_info { |
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u32 id; |
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u32 mask; |
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u32 shift; |
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}; |
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struct serdes_prctl_info srds_prctl_info[] = { |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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{.id = 1, |
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.mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK, |
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.shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT |
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}, |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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{.id = 2, |
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.mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK, |
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.shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT |
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}, |
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#endif |
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{} /* NULL ENTRY */ |
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}; |
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static int get_serdes_prctl_info_idx(u32 serdes_id) |
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{ |
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int pos = 0; |
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struct serdes_prctl_info *srds_info; |
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/* loop until NULL ENTRY defined by .id=0 */ |
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for (srds_info = srds_prctl_info; srds_info->id != 0; |
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srds_info++, pos++) { |
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if (srds_info->id == serdes_id) |
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return pos; |
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} |
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return -1; |
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} |
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static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg, |
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struct ccsr_serdes __iomem *serdes_base, |
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bool cmplt) |
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{ |
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int i, pos; |
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u32 cfg_tmp; |
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pos = get_serdes_prctl_info_idx(serdes_id); |
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if (pos == -1) { |
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printf("invalid serdes_id %d\n", serdes_id); |
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return; |
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} |
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cfg_tmp = cfg & srds_prctl_info[pos].mask; |
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cfg_tmp >>= srds_prctl_info[pos].shift; |
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for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { |
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if (cmplt) |
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setbits_le32(&serdes_base->lane[i].gcr0, |
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LNAGCR0_RT_RSTB); |
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else |
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clrbits_le32(&serdes_base->lane[i].gcr0, |
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LNAGCR0_RT_RSTB); |
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} |
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} |
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static void do_pll_reset(u32 cfg, |
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struct ccsr_serdes __iomem *serdes_base) |
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{ |
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int i; |
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for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { |
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clrbits_le32(&serdes_base->bank[i].rstctl, |
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RSTCTL_RESET_MASK); |
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udelay(1); |
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setbits_le32(&serdes_base->bank[i].rstctl, |
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RSTCTL_RSTREQ); |
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} |
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udelay(1); |
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} |
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static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base) |
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{ |
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clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); |
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clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); |
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} |
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static void do_rx_tx_cal_reset_comp(u32 cfg, int i, |
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struct ccsr_serdes __iomem *serdes_base) |
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{ |
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if (!(cfg == 0x3 && i == 1)) { |
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udelay(1); |
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setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); |
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setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); |
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} |
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udelay(1); |
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} |
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static void do_pll_reset_done(u32 cfg, |
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struct ccsr_serdes __iomem *serdes_base) |
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{ |
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int i; |
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u32 reg = 0; |
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for (i = 0; i < 2; i++) { |
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reg = in_le32(&serdes_base->bank[i].pllcr0); |
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if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { |
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setbits_le32(&serdes_base->bank[i].rstctl, |
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RSTCTL_RST_DONE); |
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} |
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} |
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} |
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static void do_serdes_enable(u32 cfg, |
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struct ccsr_serdes __iomem *serdes_base) |
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{ |
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int i; |
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for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { |
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setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN); |
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udelay(1); |
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setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B); |
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udelay(1); |
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/* Take the Rx/Tx calibration out of reset */ |
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do_rx_tx_cal_reset_comp(cfg, i, serdes_base); |
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} |
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} |
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static void do_pll_lock(u32 cfg, |
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struct ccsr_serdes __iomem *serdes_base) |
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{ |
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int i; |
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u32 reg = 0; |
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for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { |
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/* if the PLL is not locked, set RST_ERR */ |
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reg = in_le32(&serdes_base->bank[i].pllcr0); |
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if (!((reg >> 23) & 0x1)) { |
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setbits_le32(&serdes_base->bank[i].rstctl, |
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RSTCTL_RSTERR); |
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} else { |
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udelay(1); |
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setbits_le32(&serdes_base->bank[i].rstctl, |
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RSTCTL_SDRST_B); |
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udelay(1); |
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} |
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} |
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} |
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int setup_serdes_volt(u32 svdd) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
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struct ccsr_serdes __iomem *serdes1_base = |
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(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR; |
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u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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struct ccsr_serdes __iomem *serdes2_base = |
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(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); |
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u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); |
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#endif |
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u32 cfg_tmp; |
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int svdd_cur, svdd_tar; |
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int ret = 1; |
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/* Only support switch SVDD to 900mV */ |
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if (svdd != 900) |
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return -EINVAL; |
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/* Scale up to the LTC resolution is 1/4096V */ |
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svdd = (svdd * 4096) / 1000; |
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svdd_tar = svdd; |
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svdd_cur = get_serdes_volt(); |
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if (svdd_cur < 0) |
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return -EINVAL; |
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debug("%s: current SVDD: %x; target SVDD: %x\n", |
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__func__, svdd_cur, svdd_tar); |
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if (svdd_cur == svdd_tar) |
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return 0; |
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/* Put the all enabled lanes in reset */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); |
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#endif |
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/* Put the all enabled PLL in reset */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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cfg_tmp = cfg_rcwsrds1 & 0x3; |
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do_pll_reset(cfg_tmp, serdes1_base); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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cfg_tmp = cfg_rcwsrds1 & 0xC; |
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cfg_tmp >>= 2; |
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do_pll_reset(cfg_tmp, serdes2_base); |
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#endif |
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/* Put the Rx/Tx calibration into reset */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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do_rx_tx_cal_reset(serdes1_base); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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do_rx_tx_cal_reset(serdes2_base); |
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#endif |
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ret = set_serdes_volt(svdd); |
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if (ret < 0) { |
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printf("could not change SVDD\n"); |
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ret = -1; |
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} |
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/* For each PLL that’s not disabled via RCW enable the SERDES */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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cfg_tmp = cfg_rcwsrds1 & 0x3; |
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do_serdes_enable(cfg_tmp, serdes1_base); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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cfg_tmp = cfg_rcwsrds1 & 0xC; |
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cfg_tmp >>= 2; |
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do_serdes_enable(cfg_tmp, serdes2_base); |
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#endif |
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/* Wait for at at least 625us, ensure the PLLs being reset are locked */ |
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udelay(800); |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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cfg_tmp = cfg_rcwsrds1 & 0x3; |
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do_pll_lock(cfg_tmp, serdes1_base); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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cfg_tmp = cfg_rcwsrds1 & 0xC; |
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cfg_tmp >>= 2; |
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do_pll_lock(cfg_tmp, serdes2_base); |
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#endif |
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/* Take the all enabled lanes out of reset */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); |
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#endif |
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/* For each PLL being reset, and achieved PLL lock set RST_DONE */ |
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#ifdef CONFIG_SYS_FSL_SRDS_1 |
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cfg_tmp = cfg_rcwsrds1 & 0x3; |
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do_pll_reset_done(cfg_tmp, serdes1_base); |
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#endif |
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#ifdef CONFIG_SYS_FSL_SRDS_2 |
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cfg_tmp = cfg_rcwsrds1 & 0xC; |
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cfg_tmp >>= 2; |
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do_pll_reset_done(cfg_tmp, serdes2_base); |
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#endif |
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return ret; |
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} |
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void fsl_serdes_init(void) |
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{ |
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
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Tom Rini
6 years ago