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ppc: Zap MHPC board

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This board uses eeprom accessors in an incorrect way. The board
is old and unsupported, just zap it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
master
Marek Vasut 10 years ago committed by Wolfgang Denk
parent 4af5f0f3b4
commit 1655f9f6c7
12 changed files with 1 additions and 1425 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/mpc8xx/Kconfig
  2. 1
      arch/powerpc/cpu/mpc8xx/cpu_init.c
  3. 12
      board/eltec/mhpc/Kconfig
  4. 6
      board/eltec/mhpc/MAINTAINERS
  5. 8
      board/eltec/mhpc/Makefile
  6. 414
      board/eltec/mhpc/flash.c
  7. 465
      board/eltec/mhpc/mhpc.c
  8. 121
      board/eltec/mhpc/u-boot.lds.debug
  9. 3
      configs/MHPC_defconfig
  10. 1
      doc/README.scrapyard
  11. 22
      include/commproc.h
  12. 369
      include/configs/MHPC.h

4
arch/powerpc/cpu/mpc8xx/Kconfig
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@ -40,9 +40,6 @@ config TARGET_RRVISION
config TARGET_SPD823TS
bool "Support SPD823TS"
config TARGET_MHPC
bool "Support MHPC"
config TARGET_TOP860
bool "Support TOP860"
@ -117,7 +114,6 @@ endchoice
source "board/LEOX/elpt860/Kconfig"
source "board/RRvision/Kconfig"
source "board/cogent/Kconfig"
source "board/eltec/mhpc/Kconfig"
source "board/emk/top860/Kconfig"
source "board/esteem192e/Kconfig"
source "board/hermes/Kconfig"

1
arch/powerpc/cpu/mpc8xx/cpu_init.c
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@ -130,7 +130,6 @@ void cpu_init_f (volatile immap_t * immr)
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
defined(CONFIG_SPD823TS)

12
board/eltec/mhpc/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MHPC
config SYS_BOARD
default "mhpc"
config SYS_VENDOR
default "eltec"
config SYS_CONFIG_NAME
default "MHPC"
endif

6
board/eltec/mhpc/MAINTAINERS
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@ -1,6 +0,0 @@
MHPC BOARD
M: Frank Gottschling <fgottschling@eltec.de>
S: Maintained
F: board/eltec/mhpc/
F: include/configs/MHPC.h
F: configs/MHPC_defconfig

8
board/eltec/mhpc/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = mhpc.o flash.o

414
board/eltec/mhpc/flash.c
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@ -1,414 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
#include <linux/byteorder/swab.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info);
static int write_data (flash_info_t *info, ulong dest, FPW data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000);
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F640J5 :
printf ("28F640J5 \n"); break;
default: printf ("Unknown Chip Type=0x%lXh\n",
info->flash_id & FLASH_TYPEMASK); break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (FPW *addr, flash_info_t *info)
{
FPW value;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW)0xAA00AA00;
addr[0x2AAA] = (FPW)0x55005500;
addr[0x5555] = (FPW)0x90009000;
value = SWAP(addr[0]);
switch (value) {
case (FPW)INTEL_MANUFACT:
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW)0xFF00FF00; /* restore read mode */
return (0); /* no or unknown flash */
}
value = SWAP(addr[1]); /* device ID no swap !*/
switch (value) {
case (FPW)INTEL_ID_28F640J5 :
info->flash_id += FLASH_28F640J5 ;
info->sector_count = 64;
info->size = 0x00800000;
break; /* => 8 MB */
default:
info->flash_id = FLASH_UNKNOWN;
break;
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = (FPW)0xFF00FF00; /* restore read mode */
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, now, last;
int rc = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
type = (info->flash_id & FLASH_VENDMASK);
if ((type != FLASH_MAN_INTEL)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
start = get_timer (0);
last = start;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
FPWV *addr = (FPWV *)(info->start[sect]);
FPW status;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*addr = (FPW)0x50005000; /* clear status register */
*addr = (FPW)0x20002000; /* erase setup */
*addr = (FPW)0xD000D000; /* erase confirm */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = (FPW)0xB000B000; /* suspend erase */
*addr = (FPW)0xFF00FF00; /* reset to read mode */
rc = 1;
break;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
*addr = (FPW)0xFF00FF00; /* reset to read mode */
printf (" done\n");
}
}
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp;
FPW data;
int i, l, rc, port_width;
if (info->flash_id == FLASH_UNKNOWN) {
return 4;
}
/* get lower word aligned address */
#ifdef FLASH_PORT_WIDTH16
wp = (addr & ~1);
port_width = 2;
#else
wp = (addr & ~3);
port_width = 4;
#endif
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
for (; i<port_width && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
}
/*
* handle word aligned part
*/
while (cnt >= port_width) {
data = 0;
for (i=0; i<port_width; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_data(info, wp, data)) != 0) {
return (rc);
}
wp += port_width;
cnt -= port_width;
if ((wp & 0xfff) == 0)
{
printf("%08lX",wp);
printf("\x1b[8D");
}
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<port_width; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_data(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word or halfword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_data (flash_info_t *info, ulong dest, FPW data)
{
FPWV *addr = (FPWV *)dest;
ulong status;
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*addr = (FPW)0x40004000; /* write setup */
*addr = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW)0xFF00FF00; /* restore read mode */
return (1);
}
}
*addr = (FPW)0xFF00FF00; /* restore read mode */
return (0);
}

465
board/eltec/mhpc/mhpc.c
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@ -1,465 +0,0 @@
/*
* (C) Copyright 2001
* ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* Board specific routines for the miniHiPerCam
*
* - initialisation (eeprom)
* - memory controller
* - serial io initialisation
* - ethernet io initialisation
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <cli.h>
#include <linux/ctype.h>
#include <commproc.h>
#include "mpc8xx.h"
#include <video_fb.h>
extern void eeprom_init (void);
extern int eeprom_read (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
extern int eeprom_write (unsigned dev_addr, unsigned offset,
unsigned char *buffer, unsigned cnt);
/* globals */
void *video_hw_init (void);
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
GraphicDevice gdev;
/* locals */
static void video_circle (char *center, int radius, int color, int pitch);
static void video_test_image (void);
static void video_default_lut (unsigned int clut_type);
/* revision info foer MHPC EEPROM offset 480 */
typedef struct {
char board[12]; /* 000 - Board Revision information */
char sensor; /* 012 - Sensor Type information */
char serial[8]; /* 013 - Board serial number */
char etheraddr[6]; /* 021 - Ethernet node addresse */
char revision[2]; /* 027 - Revision code */
char option[3]; /* 029 - resevered for options */
} revinfo;
/* ------------------------------------------------------------------------- */
static const unsigned int sdram_table[] = {
/* read single beat cycle */
0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
/* read burst cycle */
0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write single beat cycle */
0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* write burst cycle */
0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* periodic timer expired */
0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* exception */
0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
};
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
/* reset the port A s.a. cpm-routines */
ip->iop_padat = 0x0000;
ip->iop_papar = 0x0000;
ip->iop_padir = 0x0800;
ip->iop_paodr = 0x0000;
/* reset the port B for digital and LCD output */
cp->cp_pbdat = 0x0300;
cp->cp_pbpar = 0x5001;
cp->cp_pbdir = 0x5301;
cp->cp_pbodr = 0x0000;
/* reset the port C configured for SMC1 serial port and aqc. control */
ip->iop_pcdat = 0x0800;
ip->iop_pcpar = 0x0000;
ip->iop_pcdir = 0x0e30;
ip->iop_pcso = 0x0000;
/* Config port D for LCD output */
ip->iop_pdpar = 0x1fff;
ip->iop_pddir = 0x1fff;
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity
*/
int checkboard (void)
{
puts ("Board: ELTEC miniHiperCam\n");
return (0);
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
revinfo mhpcRevInfo;
char nid[32];
char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
"OMNIVISON OV7110 b&w", NULL
};
char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
0, 0, 0, 0, 10, 11, 12, 13, 14, 15
};
int i;
/* check revision data */
eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
mhpcRevInfo.revision[0]);
if (0 != cli_readline(NULL)) {
mhpcRevInfo.revision[0] =
(char) toupper (console_buffer[0]);
}
printf ("Enter revision character (A-Z): %c ",
mhpcRevInfo.revision[1]);
if (1 == cli_readline(NULL)) {
mhpcRevInfo.revision[1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &mhpcRevInfo.board);
if (11 == cli_readline(NULL)) {
for (i = 0; i < 11; i++) {
mhpcRevInfo.board[i] =
(char) toupper (console_buffer[i]);
mhpcRevInfo.board[11] = '\0';
}
}
printf ("Supported sensor types:\n");
i = 0;
do {
printf ("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
} while (mhpcSensorTypes[++i] != NULL);
do {
printf ("\nEnter sensor number (0-255): %d ",
(int) mhpcRevInfo.sensor);
if (0 != cli_readline(NULL)) {
mhpcRevInfo.sensor =
(unsigned char)
simple_strtoul (console_buffer, NULL,
10);
}
} while (mhpcRevInfo.sensor >= i);
printf ("Enter serial number: %s ",
(char *) &mhpcRevInfo.serial);
if (6 == cli_readline(NULL)) {
for (i = 0; i < 6; i++) {
mhpcRevInfo.serial[i] = console_buffer[i];
}
mhpcRevInfo.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
if (12 == cli_readline(NULL)) {
for (i = 0; i < 12; i += 2) {
mhpcRevInfo.etheraddr[i >> 1] =
(char) (16 *
hex[toupper
(console_buffer[i]) -
'0'] +
hex[toupper
(console_buffer[i + 1]) -
'0']);
}
}
/* setup new revision data */
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
32);
}
/* set environment */
sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
setenv ("ethaddr", nid);
/* print actual board identification */
printf ("Ident: %s %s Ser %s Rev %c%c\n",
mhpcRevInfo.board,
(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
mhpcRevInfo.revision[1]);
return (0);
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
udelay (200);
/*
* Map controller SDRAM bank 1
*/
memctl->memc_or2 = CONFIG_SYS_OR2;
memctl->memc_br2 = CONFIG_SYS_BR2;
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (10000);
/* leave place for framebuffers */
return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
}
/* ------------------------------------------------------------------------- */
static void video_circle (char *center, int radius, int color, int pitch)
{
int x, y, d, dE, dSE;
x = 0;
y = radius;
d = 1 - radius;
dE = 3;
dSE = -2 * radius + 5;
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
while (y > x) {
if (d < 0) {
d += dE;
dE += 2;
dSE += 2;
x++;
} else {
d += dSE;
dE += 2;
dSE += 4;
x++;
y--;
}
*(center + x + y * pitch) = color;
*(center + y + x * pitch) = color;
*(center + y - x * pitch) = color;
*(center + x - y * pitch) = color;
*(center - x - y * pitch) = color;
*(center - y - x * pitch) = color;
*(center - y + x * pitch) = color;
*(center - x + y * pitch) = color;
}
}
/* ------------------------------------------------------------------------- */
static void video_test_image (void)
{
char *di;
int i, n;
/* draw raster */
for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
LCD_VIDEO_FG, LCD_VIDEO_COLS);
for (n = i + 1; n < i + 32; n++)
memset ((char *) (LCD_VIDEO_ADDR +
n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
LCD_VIDEO_COLS);
}
for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
for (n = 0; n < LCD_VIDEO_ROWS; n++)
*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
LCD_VIDEO_FG;
}
/* draw gray bar */
di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
97 * LCD_VIDEO_COLS);
for (n = 0; n < 63; n++) {
for (i = 0; i < 256; i++) {
*di++ = (char) i;
*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
}
di += LCD_VIDEO_COLS - 256;
}
video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
LCD_VIDEO_FG, LCD_VIDEO_COLS);
}
/* ------------------------------------------------------------------------- */
static void video_default_lut (unsigned int clut_type)
{
unsigned int i;
unsigned char RGB[] = {
0x00, 0x00, 0x00, /* black */
0x80, 0x80, 0x80, /* gray */
0xff, 0x00, 0x00, /* red */
0x00, 0xff, 0x00, /* green */
0x00, 0x00, 0xff, /* blue */
0x00, 0xff, 0xff, /* cyan */
0xff, 0x00, 0xff, /* magenta */
0xff, 0xff, 0x00, /* yellow */
0x80, 0x00, 0x00, /* dark red */
0x00, 0x80, 0x00, /* dark green */
0x00, 0x00, 0x80, /* dark blue */
0x00, 0x80, 0x80, /* dark cyan */
0x80, 0x00, 0x80, /* dark magenta */
0x80, 0x80, 0x00, /* dark yellow */
0xc0, 0xc0, 0xc0, /* light gray */
0xff, 0xff, 0xff, /* white */
};
switch (clut_type) {
case 1:
for (i = 0; i < 240; i++)
video_set_lut (i, i, i, i);
for (i = 0; i < 16; i++)
video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
RGB[i * 3 + 2]);
break;
default:
for (i = 0; i < 256; i++)
video_set_lut (i, i, i, i);
}
}
/* ------------------------------------------------------------------------- */
void *video_hw_init (void)
{
unsigned int clut = 0;
unsigned char *penv;
immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* enable video only on CLUT value */
if ((penv = (uchar *)getenv ("clut")) != NULL)
clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
else
return NULL;
/* disable graphic before write LCD regs. */
immr->im_lcd.lcd_lccr = 0x96000866;
/* config LCD regs. */
immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
immr->im_lcd.lcd_lchcr = 0x010a0093;
immr->im_lcd.lcd_lcvcr = 0x900f0024;
printf ("Video: 640x480 8Bit Index Lut %s\n",
(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
video_default_lut (clut);
/* clear framebuffer */
memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
/* enable graphic */
immr->im_lcd.lcd_lccr = 0x96000867;
/* fill in Graphic Device */
gdev.frameAdrs = LCD_VIDEO_ADDR;
gdev.winSizeX = LCD_VIDEO_COLS;
gdev.winSizeY = LCD_VIDEO_ROWS;
gdev.gdfBytesPP = 1;
gdev.gdfIndex = GDF__8BIT_INDEX;
if (clut > 1)
/* return Graphic Device for console */
return (void *) &gdev;
else
/* just graphic enabled - draw something beautiful */
video_test_image ();
return NULL; /* this disabels cfb - console */
}
/* ------------------------------------------------------------------------- */
void video_set_lut (unsigned int index,
unsigned char r, unsigned char g, unsigned char b)
{
unsigned int lum;
unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
/* y = 0.299*R + 0.587*G + 0.114*B */
lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
pLut[index] =
((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
0x3f);
}
/* ------------------------------------------------------------------------- */

121
board/eltec/mhpc/u-boot.lds.debug
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@ -1,121 +0,0 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

3
configs/MHPC_defconfig
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CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_MHPC=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
MHPC powerpc mpc8xx - - Frank Gottschling <fgottschling@eltec.de>
ICU862 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
CPCI750 powerpc 74xx_7xx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
DB64360 powerpc 74xx_7xx - -

22
include/commproc.h
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@ -703,28 +703,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00250000)
#endif /* CONFIG_KM8XX */
/*** MHPC ********************************************************/
#if defined(CONFIG_MHPC)
/* This ENET stuff is for the MHPC with ethernet on SCC2.
* Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
#endif /* CONFIG_MHPC */
/*** NETVIA *******************************************************/
#if defined(CONFIG_NETVIA)

369
include/configs/MHPC.h
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@ -1,369 +0,0 @@
/*
* (C) Copyright 2001
* Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Configuation settings for the miniHiPerCam.
*
* -----------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_MHPC 1 /* on a miniHiPerCam */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
#define CONFIG_MISC_INIT_R 1
#define CONFIG_SYS_TEXT_BASE 0xfe000000
#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#undef CONFIG_UCODE_PATCH
/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
/*
* Software (bit-bang) I2C driver configuration
*/
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
#define LCD_VIDEO_COLS 640
#define LCD_VIDEO_ROWS 480
#define LCD_VIDEO_FG 255
#define LCD_VIDEO_BG 0
#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
#define CONFIG_VIDEO_LOGO
#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
#define VIDEO_TSTC_FCT serial_stub_tstc
#define VIDEO_GETC_FCT serial_stub_getc
#define CONFIG_BR0_WORKAROUND 1
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Physical memory map
*/
#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xfe000000
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=mhpc-0"
#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
*/
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 12-18
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit - leave PLL multiplication factor unchanged !
*/
#define MPC8XX_SPEED 50000000L
#define MPC8XX_XIN 5000000L /* ref clk */
#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
/*-----------------------------------------------------------------------
* MAMR settings for SDRAM - 16-14
* => 0xC080200F
*-----------------------------------------------------------------------
* periodic timer for refresh
*/
#define CONFIG_SYS_MAMR_PTA 0xC0
#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
/*
* BR0 and OR0 (FLASH) used to re-map FLASH
*/
/* allow for max 8 MB of Flash */
#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
/*
* BR1 and OR1 (SDRAM)
*/
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
/* SDRAM timing: drive GPL5 high on first cycle */
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
/*
* BR2/OR2 - DIMM
*/
#define CONFIG_SYS_OR2 (OR_ACS_DIV4)
#define CONFIG_SYS_BR2 (BR_MS_UPMA)
/*
* BR3/OR3 - DIMM
*/
#define CONFIG_SYS_OR3 (OR_ACS_DIV4)
#define CONFIG_SYS_BR3 (BR_MS_UPMA)
/*
* BR4/OR4
*/
#define CONFIG_SYS_OR4 0
#define CONFIG_SYS_BR4 0
/*
* BR5/OR5
*/
#define CONFIG_SYS_OR5 0
#define CONFIG_SYS_BR5 0
/*
* BR6/OR6
*/
#define CONFIG_SYS_OR6 0
#define CONFIG_SYS_BR6 0
/*
* BR7/OR7
*/
#define CONFIG_SYS_OR7 0
#define CONFIG_SYS_BR7 0
/*-----------------------------------------------------------------------
* Debug Entry Mode
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_DER 0
#endif /* __CONFIG_H */
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