Tom Rini
7 years ago
commit
16d4ff76c5
@ -0,0 +1,581 @@ |
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_SDRAM_RK322X_H |
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#define _ASM_ARCH_SDRAM_RK322X_H |
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#include <common.h> |
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enum { |
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DDR3 = 3, |
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LPDDR2 = 5, |
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LPDDR3 = 6, |
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UNUSED = 0xFF, |
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}; |
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struct rk322x_sdram_channel { |
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/*
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* bit width in address, eg: |
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* 8 banks using 3 bit to address, |
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* 2 cs using 1 bit to address. |
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*/ |
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u8 rank; |
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u8 col; |
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u8 bk; |
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u8 bw; |
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u8 dbw; |
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u8 row_3_4; |
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u8 cs0_row; |
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u8 cs1_row; |
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#if CONFIG_IS_ENABLED(OF_PLATDATA) |
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/*
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* For of-platdata, which would otherwise convert this into two |
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* byte-swapped integers. With a size of 9 bytes, this struct will |
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* appear in of-platdata as a byte array. |
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* |
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* If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) |
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*/ |
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u8 dummy; |
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#endif |
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}; |
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struct rk322x_ddr_pctl { |
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u32 scfg; |
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u32 sctl; |
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u32 stat; |
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u32 intrstat; |
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u32 reserved0[(0x40 - 0x10) / 4]; |
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u32 mcmd; |
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u32 powctl; |
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u32 powstat; |
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u32 cmdtstat; |
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u32 cmdtstaten; |
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u32 reserved1[(0x60 - 0x54) / 4]; |
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u32 mrrcfg0; |
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u32 mrrstat0; |
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u32 mrrstat1; |
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u32 reserved2[(0x7c - 0x6c) / 4]; |
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|
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u32 mcfg1; |
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u32 mcfg; |
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u32 ppcfg; |
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u32 mstat; |
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u32 lpddr2zqcfg; |
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u32 reserved3; |
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u32 dtupdes; |
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u32 dtuna; |
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u32 dtune; |
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u32 dtuprd0; |
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u32 dtuprd1; |
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u32 dtuprd2; |
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u32 dtuprd3; |
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u32 dtuawdt; |
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u32 reserved4[(0xc0 - 0xb4) / 4]; |
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u32 togcnt1u; |
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u32 tinit; |
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u32 trsth; |
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u32 togcnt100n; |
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u32 trefi; |
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u32 tmrd; |
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u32 trfc; |
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u32 trp; |
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u32 trtw; |
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u32 tal; |
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u32 tcl; |
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u32 tcwl; |
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u32 tras; |
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u32 trc; |
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u32 trcd; |
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u32 trrd; |
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u32 trtp; |
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u32 twr; |
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u32 twtr; |
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u32 texsr; |
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u32 txp; |
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u32 txpdll; |
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u32 tzqcs; |
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u32 tzqcsi; |
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u32 tdqs; |
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u32 tcksre; |
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u32 tcksrx; |
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u32 tcke; |
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u32 tmod; |
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u32 trstl; |
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u32 tzqcl; |
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u32 tmrr; |
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u32 tckesr; |
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u32 tdpd; |
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u32 tref_mem_ddr3; |
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u32 reserved5[(0x180 - 0x14c) / 4]; |
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u32 ecccfg; |
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u32 ecctst; |
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u32 eccclr; |
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u32 ecclog; |
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u32 reserved6[(0x200 - 0x190) / 4]; |
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u32 dtuwactl; |
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u32 dturactl; |
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u32 dtucfg; |
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u32 dtuectl; |
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u32 dtuwd0; |
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u32 dtuwd1; |
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u32 dtuwd2; |
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u32 dtuwd3; |
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u32 dtuwdm; |
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u32 dturd0; |
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u32 dturd1; |
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u32 dturd2; |
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u32 dturd3; |
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u32 dtulfsrwd; |
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u32 dtulfsrrd; |
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u32 dtueaf; |
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/* dfi control registers */ |
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u32 dfitctrldelay; |
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u32 dfiodtcfg; |
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u32 dfiodtcfg1; |
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u32 dfiodtrankmap; |
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/* dfi write data registers */ |
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u32 dfitphywrdata; |
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u32 dfitphywrlat; |
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u32 reserved7[(0x260 - 0x258) / 4]; |
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u32 dfitrddataen; |
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u32 dfitphyrdlat; |
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u32 reserved8[(0x270 - 0x268) / 4]; |
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u32 dfitphyupdtype0; |
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u32 dfitphyupdtype1; |
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u32 dfitphyupdtype2; |
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u32 dfitphyupdtype3; |
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u32 dfitctrlupdmin; |
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u32 dfitctrlupdmax; |
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u32 dfitctrlupddly; |
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u32 reserved9; |
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u32 dfiupdcfg; |
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u32 dfitrefmski; |
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u32 dfitctrlupdi; |
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u32 reserved10[(0x2ac - 0x29c) / 4]; |
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u32 dfitrcfg0; |
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u32 dfitrstat0; |
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u32 dfitrwrlvlen; |
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u32 dfitrrdlvlen; |
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u32 dfitrrdlvlgateen; |
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u32 dfiststat0; |
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u32 dfistcfg0; |
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u32 dfistcfg1; |
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u32 reserved11; |
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u32 dfitdramclken; |
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u32 dfitdramclkdis; |
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u32 dfistcfg2; |
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u32 dfistparclr; |
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u32 dfistparlog; |
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u32 reserved12[(0x2f0 - 0x2e4) / 4]; |
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u32 dfilpcfg0; |
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u32 reserved13[(0x300 - 0x2f4) / 4]; |
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u32 dfitrwrlvlresp0; |
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u32 dfitrwrlvlresp1; |
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u32 dfitrwrlvlresp2; |
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u32 dfitrrdlvlresp0; |
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u32 dfitrrdlvlresp1; |
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u32 dfitrrdlvlresp2; |
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u32 dfitrwrlvldelay0; |
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u32 dfitrwrlvldelay1; |
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u32 dfitrwrlvldelay2; |
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u32 dfitrrdlvldelay0; |
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u32 dfitrrdlvldelay1; |
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u32 dfitrrdlvldelay2; |
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u32 dfitrrdlvlgatedelay0; |
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u32 dfitrrdlvlgatedelay1; |
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u32 dfitrrdlvlgatedelay2; |
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u32 dfitrcmd; |
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u32 reserved14[(0x3f8 - 0x340) / 4]; |
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u32 ipvr; |
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u32 iptr; |
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}; |
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check_member(rk322x_ddr_pctl, iptr, 0x03fc); |
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struct rk322x_ddr_phy { |
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u32 ddrphy_reg[0x100]; |
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}; |
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struct rk322x_pctl_timing { |
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u32 togcnt1u; |
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u32 tinit; |
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u32 trsth; |
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u32 togcnt100n; |
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u32 trefi; |
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u32 tmrd; |
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u32 trfc; |
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u32 trp; |
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u32 trtw; |
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u32 tal; |
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u32 tcl; |
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u32 tcwl; |
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u32 tras; |
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u32 trc; |
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u32 trcd; |
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u32 trrd; |
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u32 trtp; |
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u32 twr; |
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u32 twtr; |
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u32 texsr; |
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u32 txp; |
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u32 txpdll; |
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u32 tzqcs; |
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u32 tzqcsi; |
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u32 tdqs; |
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u32 tcksre; |
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u32 tcksrx; |
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u32 tcke; |
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u32 tmod; |
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u32 trstl; |
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u32 tzqcl; |
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u32 tmrr; |
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u32 tckesr; |
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u32 tdpd; |
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u32 trefi_mem_ddr3; |
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}; |
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struct rk322x_phy_timing { |
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u32 mr[4]; |
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u32 mr11; |
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u32 bl; |
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u32 cl_al; |
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}; |
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struct rk322x_msch_timings { |
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u32 ddrtiming; |
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u32 ddrmode; |
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u32 readlatency; |
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u32 activate; |
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u32 devtodev; |
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}; |
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struct rk322x_service_sys { |
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u32 id_coreid; |
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u32 id_revisionid; |
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u32 ddrconf; |
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u32 ddrtiming; |
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u32 ddrmode; |
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u32 readlatency; |
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u32 activate; |
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u32 devtodev; |
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}; |
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struct rk322x_base_params { |
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struct rk322x_msch_timings noc_timing; |
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u32 ddrconfig; |
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u32 ddr_freq; |
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u32 dramtype; |
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/*
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* unused for rk322x |
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*/ |
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u32 stride; |
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u32 odt; |
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}; |
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/* PCT_DFISTCFG0 */ |
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#define DFI_INIT_START BIT(0) |
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#define DFI_DATA_BYTE_DISABLE_EN BIT(2) |
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/* PCT_DFISTCFG1 */ |
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#define DFI_DRAM_CLK_SR_EN BIT(0) |
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#define DFI_DRAM_CLK_DPD_EN BIT(1) |
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/* PCT_DFISTCFG2 */ |
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#define DFI_PARITY_INTR_EN BIT(0) |
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#define DFI_PARITY_EN BIT(1) |
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/* PCT_DFILPCFG0 */ |
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#define TLP_RESP_TIME_SHIFT 16 |
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#define LP_SR_EN BIT(8) |
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#define LP_PD_EN BIT(0) |
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/* PCT_DFITCTRLDELAY */ |
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#define TCTRL_DELAY_TIME_SHIFT 0 |
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/* PCT_DFITPHYWRDATA */ |
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#define TPHY_WRDATA_TIME_SHIFT 0 |
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/* PCT_DFITPHYRDLAT */ |
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#define TPHY_RDLAT_TIME_SHIFT 0 |
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/* PCT_DFITDRAMCLKDIS */ |
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#define TDRAM_CLK_DIS_TIME_SHIFT 0 |
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/* PCT_DFITDRAMCLKEN */ |
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#define TDRAM_CLK_EN_TIME_SHIFT 0 |
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/* PCTL_DFIODTCFG */ |
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#define RANK0_ODT_WRITE_SEL BIT(3) |
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#define RANK1_ODT_WRITE_SEL BIT(11) |
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/* PCTL_DFIODTCFG1 */ |
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#define ODT_LEN_BL8_W_SHIFT 16 |
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/* PUBL_ACDLLCR */ |
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#define ACDLLCR_DLLDIS BIT(31) |
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#define ACDLLCR_DLLSRST BIT(30) |
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/* PUBL_DXDLLCR */ |
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#define DXDLLCR_DLLDIS BIT(31) |
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#define DXDLLCR_DLLSRST BIT(30) |
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/* PUBL_DLLGCR */ |
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#define DLLGCR_SBIAS BIT(30) |
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/* PUBL_DXGCR */ |
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#define DQSRTT BIT(9) |
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#define DQRTT BIT(10) |
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/* PIR */ |
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#define PIR_INIT BIT(0) |
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#define PIR_DLLSRST BIT(1) |
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#define PIR_DLLLOCK BIT(2) |
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#define PIR_ZCAL BIT(3) |
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#define PIR_ITMSRST BIT(4) |
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#define PIR_DRAMRST BIT(5) |
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#define PIR_DRAMINIT BIT(6) |
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#define PIR_QSTRN BIT(7) |
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#define PIR_RVTRN BIT(8) |
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#define PIR_ICPC BIT(16) |
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#define PIR_DLLBYP BIT(17) |
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#define PIR_CTLDINIT BIT(18) |
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#define PIR_CLRSR BIT(28) |
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#define PIR_LOCKBYP BIT(29) |
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#define PIR_ZCALBYP BIT(30) |
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#define PIR_INITBYP BIT(31) |
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/* PGCR */ |
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#define PGCR_DFTLMT_SHIFT 3 |
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#define PGCR_DFTCMP_SHIFT 2 |
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#define PGCR_DQSCFG_SHIFT 1 |
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#define PGCR_ITMDMD_SHIFT 0 |
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/* PGSR */ |
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#define PGSR_IDONE BIT(0) |
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#define PGSR_DLDONE BIT(1) |
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#define PGSR_ZCDONE BIT(2) |
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#define PGSR_DIDONE BIT(3) |
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#define PGSR_DTDONE BIT(4) |
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#define PGSR_DTERR BIT(5) |
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#define PGSR_DTIERR BIT(6) |
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#define PGSR_DFTERR BIT(7) |
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#define PGSR_RVERR BIT(8) |
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#define PGSR_RVEIRR BIT(9) |
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/* PTR0 */ |
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#define PRT_ITMSRST_SHIFT 18 |
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#define PRT_DLLLOCK_SHIFT 6 |
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#define PRT_DLLSRST_SHIFT 0 |
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/* PTR1 */ |
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#define PRT_DINIT0_SHIFT 0 |
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#define PRT_DINIT1_SHIFT 19 |
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/* PTR2 */ |
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#define PRT_DINIT2_SHIFT 0 |
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#define PRT_DINIT3_SHIFT 17 |
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/* DCR */ |
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#define DDRMD_LPDDR 0 |
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#define DDRMD_DDR 1 |
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#define DDRMD_DDR2 2 |
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#define DDRMD_DDR3 3 |
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#define DDRMD_LPDDR2_LPDDR3 4 |
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#define DDRMD_MASK 7 |
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#define DDRMD_SHIFT 0 |
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#define PDQ_MASK 7 |
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#define PDQ_SHIFT 4 |
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/* DXCCR */ |
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#define DQSNRES_MASK 0xf |
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#define DQSNRES_SHIFT 8 |
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#define DQSRES_MASK 0xf |
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#define DQSRES_SHIFT 4 |
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/* DTPR */ |
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#define TDQSCKMAX_SHIFT 27 |
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#define TDQSCKMAX_MASK 7 |
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#define TDQSCK_SHIFT 24 |
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#define TDQSCK_MASK 7 |
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/* DSGCR */ |
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#define DQSGX_SHIFT 5 |
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#define DQSGX_MASK 7 |
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#define DQSGE_SHIFT 8 |
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#define DQSGE_MASK 7 |
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/* SCTL */ |
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#define INIT_STATE 0 |
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#define CFG_STATE 1 |
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#define GO_STATE 2 |
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#define SLEEP_STATE 3 |
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#define WAKEUP_STATE 4 |
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/* STAT */ |
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#define LP_TRIG_SHIFT 4 |
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#define LP_TRIG_MASK 7 |
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#define PCTL_STAT_MASK 7 |
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#define INIT_MEM 0 |
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#define CONFIG 1 |
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#define CONFIG_REQ 2 |
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#define ACCESS 3 |
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#define ACCESS_REQ 4 |
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#define LOW_POWER 5 |
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#define LOW_POWER_ENTRY_REQ 6 |
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#define LOW_POWER_EXIT_REQ 7 |
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/* ZQCR*/ |
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#define PD_OUTPUT_SHIFT 0 |
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#define PU_OUTPUT_SHIFT 5 |
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#define PD_ONDIE_SHIFT 10 |
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#define PU_ONDIE_SHIFT 15 |
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#define ZDEN_SHIFT 28 |
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|
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/* DDLGCR */ |
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#define SBIAS_BYPASS BIT(23) |
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|
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/* MCFG */ |
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#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 |
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#define PD_IDLE_SHIFT 8 |
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#define MDDR_EN (2 << 22) |
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#define LPDDR2_EN (3 << 22) |
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#define LPDDR3_EN (1 << 22) |
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#define DDR2_EN (0 << 5) |
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#define DDR3_EN (1 << 5) |
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#define LPDDR2_S2 (0 << 6) |
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#define LPDDR2_S4 (1 << 6) |
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#define MDDR_LPDDR2_BL_2 (0 << 20) |
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#define MDDR_LPDDR2_BL_4 (1 << 20) |
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#define MDDR_LPDDR2_BL_8 (2 << 20) |
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#define MDDR_LPDDR2_BL_16 (3 << 20) |
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#define DDR2_DDR3_BL_4 0 |
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#define DDR2_DDR3_BL_8 1 |
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#define TFAW_SHIFT 18 |
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#define PD_EXIT_SLOW (0 << 17) |
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#define PD_EXIT_FAST (1 << 17) |
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#define PD_TYPE_SHIFT 16 |
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#define BURSTLENGTH_SHIFT 20 |
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|
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/* POWCTL */ |
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#define POWER_UP_START BIT(0) |
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|
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/* POWSTAT */ |
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#define POWER_UP_DONE BIT(0) |
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|
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/* MCMD */ |
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enum { |
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DESELECT_CMD = 0, |
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PREA_CMD, |
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REF_CMD, |
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MRS_CMD, |
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ZQCS_CMD, |
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ZQCL_CMD, |
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RSTL_CMD, |
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MRR_CMD = 8, |
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DPDE_CMD, |
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}; |
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#define BANK_ADDR_MASK 7 |
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#define BANK_ADDR_SHIFT 17 |
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#define CMD_ADDR_MASK 0x1fff |
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#define CMD_ADDR_SHIFT 4 |
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|
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#define LPDDR23_MA_SHIFT 4 |
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#define LPDDR23_MA_MASK 0xff |
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#define LPDDR23_OP_SHIFT 12 |
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#define LPDDR23_OP_MASK 0xff |
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|
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#define START_CMD (1u << 31) |
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|
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/* DDRPHY REG */ |
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enum { |
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/* DDRPHY_REG0 */ |
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SOFT_RESET_MASK = 3, |
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SOFT_DERESET_ANALOG = 1 << 2, |
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SOFT_DERESET_DIGITAL = 1 << 3, |
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SOFT_RESET_SHIFT = 2, |
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|
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/* DDRPHY REG1 */ |
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PHY_DDR3 = 0, |
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PHY_DDR2 = 1, |
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PHY_LPDDR3 = 2, |
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PHY_LPDDR2 = 3, |
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|
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PHT_BL_8 = 1 << 2, |
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PHY_BL_4 = 0 << 2, |
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|
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/* DDRPHY_REG2 */ |
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MEMORY_SELECT_DDR3 = 0 << 0, |
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MEMORY_SELECT_LPDDR3 = 2 << 0, |
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MEMORY_SELECT_LPDDR2 = 3 << 0, |
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DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, |
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DQS_SQU_CAL_SEL_CS1 = 1 << 4, |
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DQS_SQU_CAL_SEL_CS0 = 2 << 4, |
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DQS_SQU_CAL_NORMAL_MODE = 0 << 1, |
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DQS_SQU_CAL_BYPASS_MODE = 1 << 1, |
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DQS_SQU_CAL_START = 1 << 0, |
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DQS_SQU_NO_CAL = 0 << 0, |
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}; |
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|
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/* CK pull up/down driver strength control */ |
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enum { |
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PHY_RON_RTT_DISABLE = 0, |
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PHY_RON_RTT_451OHM = 1, |
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PHY_RON_RTT_225OHM, |
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PHY_RON_RTT_150OHM, |
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PHY_RON_RTT_112OHM, |
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PHY_RON_RTT_90OHM, |
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PHY_RON_RTT_75OHM, |
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PHY_RON_RTT_64OHM = 7, |
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|
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PHY_RON_RTT_56OHM = 16, |
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PHY_RON_RTT_50OHM, |
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PHY_RON_RTT_45OHM, |
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PHY_RON_RTT_41OHM, |
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PHY_RON_RTT_37OHM, |
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PHY_RON_RTT_34OHM, |
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PHY_RON_RTT_33OHM, |
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PHY_RON_RTT_30OHM = 23, |
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|
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PHY_RON_RTT_28OHM = 24, |
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PHY_RON_RTT_26OHM, |
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PHY_RON_RTT_25OHM, |
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PHY_RON_RTT_23OHM, |
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PHY_RON_RTT_22OHM, |
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PHY_RON_RTT_21OHM, |
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PHY_RON_RTT_20OHM, |
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PHY_RON_RTT_19OHM = 31, |
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}; |
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|
||||
/* DQS squelch DLL delay */ |
||||
enum { |
||||
DQS_DLL_NO_DELAY = 0, |
||||
DQS_DLL_22P5_DELAY, |
||||
DQS_DLL_45_DELAY, |
||||
DQS_DLL_67P5_DELAY, |
||||
DQS_DLL_90_DELAY, |
||||
DQS_DLL_112P5_DELAY, |
||||
DQS_DLL_135_DELAY, |
||||
DQS_DLL_157P5_DELAY, |
||||
}; |
||||
|
||||
/* GRF_SOC_CON0 */ |
||||
#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) |
||||
#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) |
||||
#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7)) |
||||
#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7)) |
||||
|
||||
#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) |
||||
#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) |
||||
|
||||
#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) |
||||
#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6)) |
||||
|
||||
#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) |
||||
#define DDR3_DLL_RESET (1 << 8) |
||||
|
||||
#endif /* _ASM_ARCH_SDRAM_RK322X_H */ |
||||
@ -0,0 +1,84 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Amarula Solutions |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <debug_uart.h> |
||||
#include <dm.h> |
||||
#include <ram.h> |
||||
#include <spl.h> |
||||
#include <version.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/bootrom.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/grf_rk3288.h> |
||||
#include <asm/arch/periph.h> |
||||
#include <asm/arch/pmu_rk3288.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/timer.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define GRF_BASE 0xff770000 |
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
/* Example code showing how to enable the debug UART on RK3288 */ |
||||
/* Enable early UART on the RK3288 */ |
||||
struct rk3288_grf * const grf = (void *)GRF_BASE; |
||||
|
||||
rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | |
||||
GPIO7C6_MASK << GPIO7C6_SHIFT, |
||||
GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | |
||||
GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); |
||||
/*
|
||||
* Debug UART can be used from here if required: |
||||
* |
||||
* debug_uart_init(); |
||||
* printch('a'); |
||||
* printhex8(0x1234); |
||||
* printascii("string"); |
||||
*/ |
||||
debug_uart_init(); |
||||
|
||||
ret = spl_early_init(); |
||||
if (ret) { |
||||
debug("spl_early_init() failed: %d\n", ret); |
||||
hang(); |
||||
} |
||||
|
||||
rockchip_timer_init(); |
||||
configure_l2ctlr(); |
||||
|
||||
ret = rockchip_get_clk(&dev); |
||||
if (ret) { |
||||
debug("CLK init failed: %d\n", ret); |
||||
return; |
||||
} |
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
||||
if (ret) { |
||||
debug("DRAM init failed: %d\n", ret); |
||||
return; |
||||
} |
||||
} |
||||
|
||||
void board_return_to_bootrom(void) |
||||
{ |
||||
back_to_bootrom(); |
||||
} |
||||
|
||||
u32 spl_boot_device(void) |
||||
{ |
||||
return BOOT_DEVICE_BOOTROM; |
||||
} |
||||
|
||||
void spl_board_init(void) |
||||
{ |
||||
puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
|
||||
U_BOOT_TIME ")\n"); |
||||
} |
||||
@ -0,0 +1,183 @@ |
||||
/*
|
||||
* (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Rockchip SARADC driver for U-Boot |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <adc.h> |
||||
#include <clk.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define SARADC_CTRL_CHN_MASK GENMASK(2, 0) |
||||
#define SARADC_CTRL_POWER_CTRL BIT(3) |
||||
#define SARADC_CTRL_IRQ_ENABLE BIT(5) |
||||
#define SARADC_CTRL_IRQ_STATUS BIT(6) |
||||
|
||||
#define SARADC_TIMEOUT (100 * 1000) |
||||
|
||||
struct rockchip_saradc_regs { |
||||
unsigned int data; |
||||
unsigned int stas; |
||||
unsigned int ctrl; |
||||
unsigned int dly_pu_soc; |
||||
}; |
||||
|
||||
struct rockchip_saradc_data { |
||||
int num_bits; |
||||
int num_channels; |
||||
unsigned long clk_rate; |
||||
}; |
||||
|
||||
struct rockchip_saradc_priv { |
||||
struct rockchip_saradc_regs *regs; |
||||
int active_channel; |
||||
const struct rockchip_saradc_data *data; |
||||
}; |
||||
|
||||
int rockchip_saradc_channel_data(struct udevice *dev, int channel, |
||||
unsigned int *data) |
||||
{ |
||||
struct rockchip_saradc_priv *priv = dev_get_priv(dev); |
||||
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); |
||||
|
||||
if (channel != priv->active_channel) { |
||||
error("Requested channel is not active!"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != |
||||
SARADC_CTRL_IRQ_STATUS) |
||||
return -EBUSY; |
||||
|
||||
/* Read value */ |
||||
*data = readl(&priv->regs->data); |
||||
*data &= uc_pdata->data_mask; |
||||
|
||||
/* Power down adc */ |
||||
writel(0, &priv->regs->ctrl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rockchip_saradc_start_channel(struct udevice *dev, int channel) |
||||
{ |
||||
struct rockchip_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
if (channel < 0 || channel >= priv->data->num_channels) { |
||||
error("Requested channel is invalid!"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* 8 clock periods as delay between power up and start cmd */ |
||||
writel(8, &priv->regs->dly_pu_soc); |
||||
|
||||
/* Select the channel to be used and trigger conversion */ |
||||
writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | |
||||
SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl); |
||||
|
||||
priv->active_channel = channel; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rockchip_saradc_stop(struct udevice *dev) |
||||
{ |
||||
struct rockchip_saradc_priv *priv = dev_get_priv(dev); |
||||
|
||||
/* Power down adc */ |
||||
writel(0, &priv->regs->ctrl); |
||||
|
||||
priv->active_channel = -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rockchip_saradc_probe(struct udevice *dev) |
||||
{ |
||||
struct rockchip_saradc_priv *priv = dev_get_priv(dev); |
||||
struct clk clk; |
||||
int ret; |
||||
|
||||
ret = clk_get_by_index(dev, 0, &clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = clk_set_rate(&clk, priv->data->clk_rate); |
||||
if (IS_ERR_VALUE(ret)) |
||||
return ret; |
||||
|
||||
priv->active_channel = -1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); |
||||
struct rockchip_saradc_priv *priv = dev_get_priv(dev); |
||||
struct rockchip_saradc_data *data; |
||||
|
||||
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); |
||||
priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev); |
||||
if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) { |
||||
error("Dev: %s - can't get address!", dev->name); |
||||
return -ENODATA; |
||||
} |
||||
|
||||
priv->data = data; |
||||
uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;; |
||||
uc_pdata->data_format = ADC_DATA_FORMAT_BIN; |
||||
uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; |
||||
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct adc_ops rockchip_saradc_ops = { |
||||
.start_channel = rockchip_saradc_start_channel, |
||||
.channel_data = rockchip_saradc_channel_data, |
||||
.stop = rockchip_saradc_stop, |
||||
}; |
||||
|
||||
static const struct rockchip_saradc_data saradc_data = { |
||||
.num_bits = 10, |
||||
.num_channels = 3, |
||||
.clk_rate = 1000000, |
||||
}; |
||||
|
||||
static const struct rockchip_saradc_data rk3066_tsadc_data = { |
||||
.num_bits = 12, |
||||
.num_channels = 2, |
||||
.clk_rate = 50000, |
||||
}; |
||||
|
||||
static const struct rockchip_saradc_data rk3399_saradc_data = { |
||||
.num_bits = 10, |
||||
.num_channels = 6, |
||||
.clk_rate = 1000000, |
||||
}; |
||||
|
||||
static const struct udevice_id rockchip_saradc_ids[] = { |
||||
{ .compatible = "rockchip,saradc", |
||||
.data = (ulong)&saradc_data }, |
||||
{ .compatible = "rockchip,rk3066-tsadc", |
||||
.data = (ulong)&rk3066_tsadc_data }, |
||||
{ .compatible = "rockchip,rk3399-saradc", |
||||
.data = (ulong)&rk3399_saradc_data }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(rockchip_saradc) = { |
||||
.name = "rockchip_saradc", |
||||
.id = UCLASS_ADC, |
||||
.of_match = rockchip_saradc_ids, |
||||
.ops = &rockchip_saradc_ops, |
||||
.probe = rockchip_saradc_probe, |
||||
.ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, |
||||
.priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), |
||||
}; |
||||
@ -0,0 +1,855 @@ |
||||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
#include <common.h> |
||||
#include <clk.h> |
||||
#include <dm.h> |
||||
#include <dt-structs.h> |
||||
#include <errno.h> |
||||
#include <ram.h> |
||||
#include <regmap.h> |
||||
#include <syscon.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rk322x.h> |
||||
#include <asm/arch/grf_rk322x.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/sdram_rk322x.h> |
||||
#include <asm/arch/timer.h> |
||||
#include <asm/arch/uart.h> |
||||
#include <asm/arch/sdram_common.h> |
||||
#include <asm/types.h> |
||||
#include <linux/err.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
struct chan_info { |
||||
struct rk322x_ddr_pctl *pctl; |
||||
struct rk322x_ddr_phy *phy; |
||||
struct rk322x_service_sys *msch; |
||||
}; |
||||
|
||||
struct dram_info { |
||||
struct chan_info chan[1]; |
||||
struct ram_info info; |
||||
struct clk ddr_clk; |
||||
struct rk322x_cru *cru; |
||||
struct rk322x_grf *grf; |
||||
}; |
||||
|
||||
struct rk322x_sdram_params { |
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA) |
||||
struct dtd_rockchip_rk3228_dmc of_plat; |
||||
#endif |
||||
struct rk322x_sdram_channel ch[1]; |
||||
struct rk322x_pctl_timing pctl_timing; |
||||
struct rk322x_phy_timing phy_timing; |
||||
struct rk322x_base_params base; |
||||
int num_channels; |
||||
struct regmap *map; |
||||
}; |
||||
|
||||
#ifdef CONFIG_TPL_BUILD |
||||
/*
|
||||
* [7:6] bank(n:n bit bank) |
||||
* [5:4] row(13+n) |
||||
* [3] cs(0:1 cs, 1:2 cs) |
||||
* [2:1] bank(n:n bit bank) |
||||
* [0] col(10+n) |
||||
*/ |
||||
const char ddr_cfg_2_rbc[] = { |
||||
((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1), |
||||
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1), |
||||
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1), |
||||
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1), |
||||
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2), |
||||
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2), |
||||
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2), |
||||
((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0), |
||||
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0), |
||||
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0), |
||||
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0), |
||||
((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1), |
||||
((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2), |
||||
((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1), |
||||
((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1), |
||||
((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0), |
||||
}; |
||||
|
||||
static void copy_to_reg(u32 *dest, const u32 *src, u32 n) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < n / sizeof(u32); i++) { |
||||
writel(*src, dest); |
||||
src++; |
||||
dest++; |
||||
} |
||||
} |
||||
|
||||
void phy_pctrl_reset(struct rk322x_cru *cru, |
||||
struct rk322x_ddr_phy *ddr_phy) |
||||
{ |
||||
rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | |
||||
1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | |
||||
1 << DDRPHY_SRST_SHIFT, |
||||
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | |
||||
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); |
||||
|
||||
rockchip_udelay(10); |
||||
|
||||
rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | |
||||
1 << DDRPHY_SRST_SHIFT); |
||||
rockchip_udelay(10); |
||||
|
||||
rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | |
||||
1 << DDRCTRL_SRST_SHIFT); |
||||
rockchip_udelay(10); |
||||
|
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0], |
||||
SOFT_RESET_MASK << SOFT_RESET_SHIFT); |
||||
rockchip_udelay(10); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0], |
||||
SOFT_DERESET_ANALOG); |
||||
rockchip_udelay(5); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0], |
||||
SOFT_DERESET_DIGITAL); |
||||
|
||||
rockchip_udelay(1); |
||||
} |
||||
|
||||
void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); |
||||
|
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8); |
||||
|
||||
if (freq <= 400) |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); |
||||
else |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); |
||||
|
||||
if (freq <= 680) |
||||
tmp = 3; |
||||
else |
||||
tmp = 2; |
||||
|
||||
writel(tmp, &ddr_phy->ddrphy_reg[0x28]); |
||||
writel(tmp, &ddr_phy->ddrphy_reg[0x38]); |
||||
writel(tmp, &ddr_phy->ddrphy_reg[0x48]); |
||||
writel(tmp, &ddr_phy->ddrphy_reg[0x58]); |
||||
} |
||||
|
||||
static void send_command(struct rk322x_ddr_pctl *pctl, |
||||
u32 rank, u32 cmd, u32 arg) |
||||
{ |
||||
writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); |
||||
rockchip_udelay(1); |
||||
while (readl(&pctl->mcmd) & START_CMD) |
||||
; |
||||
} |
||||
|
||||
static void memory_init(struct chan_info *chan, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
struct rk322x_ddr_pctl *pctl = chan->pctl; |
||||
u32 dramtype = sdram_params->base.dramtype; |
||||
|
||||
if (dramtype == DDR3) { |
||||
send_command(pctl, 3, DESELECT_CMD, 0); |
||||
rockchip_udelay(1); |
||||
send_command(pctl, 3, PREA_CMD, 0); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | |
||||
(sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << |
||||
CMD_ADDR_SHIFT); |
||||
|
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | |
||||
(sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << |
||||
CMD_ADDR_SHIFT); |
||||
|
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | |
||||
(sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << |
||||
CMD_ADDR_SHIFT); |
||||
|
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | |
||||
((sdram_params->phy_timing.mr[0] | |
||||
DDR3_DLL_RESET) & |
||||
CMD_ADDR_MASK) << CMD_ADDR_SHIFT); |
||||
|
||||
send_command(pctl, 3, ZQCL_CMD, 0); |
||||
} else { |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(0 & LPDDR23_OP_MASK) << |
||||
LPDDR23_OP_SHIFT); |
||||
rockchip_udelay(10); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(0xff & LPDDR23_OP_MASK) << |
||||
LPDDR23_OP_SHIFT); |
||||
rockchip_udelay(1); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(0xff & LPDDR23_OP_MASK) << |
||||
LPDDR23_OP_SHIFT); |
||||
rockchip_udelay(1); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(sdram_params->phy_timing.mr[1] & |
||||
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(sdram_params->phy_timing.mr[2] & |
||||
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); |
||||
send_command(pctl, 3, MRS_CMD, |
||||
(3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | |
||||
(sdram_params->phy_timing.mr[3] & |
||||
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); |
||||
if (dramtype == LPDDR3) |
||||
send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) << |
||||
LPDDR23_MA_SHIFT | |
||||
(sdram_params->phy_timing.mr11 & |
||||
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); |
||||
} |
||||
} |
||||
|
||||
static u32 data_training(struct chan_info *chan) |
||||
{ |
||||
struct rk322x_ddr_phy *ddr_phy = chan->phy; |
||||
struct rk322x_ddr_pctl *pctl = chan->pctl; |
||||
u32 value; |
||||
u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; |
||||
u32 ret; |
||||
|
||||
/* disable auto refresh */ |
||||
value = readl(&pctl->trefi) | (1 << 31); |
||||
writel(1 << 31, &pctl->trefi); |
||||
|
||||
clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30, |
||||
DQS_SQU_CAL_SEL_CS0); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); |
||||
|
||||
rockchip_udelay(30); |
||||
ret = readl(&ddr_phy->ddrphy_reg[0xff]); |
||||
|
||||
clrbits_le32(&ddr_phy->ddrphy_reg[2], |
||||
DQS_SQU_CAL_START); |
||||
|
||||
/*
|
||||
* since data training will take about 20us, so send some auto |
||||
* refresh(about 7.8us) to complement the lost time |
||||
*/ |
||||
send_command(pctl, 3, PREA_CMD, 0); |
||||
send_command(pctl, 3, REF_CMD, 0); |
||||
|
||||
writel(value, &pctl->trefi); |
||||
|
||||
if (ret & 0x10) { |
||||
ret = -1; |
||||
} else { |
||||
ret = (ret & 0xf) ^ bw; |
||||
ret = (ret == 0) ? 0 : -1; |
||||
} |
||||
return ret; |
||||
} |
||||
|
||||
static void move_to_config_state(struct rk322x_ddr_pctl *pctl) |
||||
{ |
||||
unsigned int state; |
||||
|
||||
while (1) { |
||||
state = readl(&pctl->stat) & PCTL_STAT_MASK; |
||||
switch (state) { |
||||
case LOW_POWER: |
||||
writel(WAKEUP_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) |
||||
!= ACCESS) |
||||
; |
||||
/*
|
||||
* If at low power state, need wakeup first, and then |
||||
* enter the config, so fallthrough |
||||
*/ |
||||
case ACCESS: |
||||
/* fallthrough */ |
||||
case INIT_MEM: |
||||
writel(CFG_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) |
||||
; |
||||
break; |
||||
case CONFIG: |
||||
return; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static void move_to_access_state(struct rk322x_ddr_pctl *pctl) |
||||
{ |
||||
unsigned int state; |
||||
|
||||
while (1) { |
||||
state = readl(&pctl->stat) & PCTL_STAT_MASK; |
||||
switch (state) { |
||||
case LOW_POWER: |
||||
writel(WAKEUP_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) |
||||
; |
||||
break; |
||||
case INIT_MEM: |
||||
writel(CFG_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) |
||||
; |
||||
/* fallthrough */ |
||||
case CONFIG: |
||||
writel(GO_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) |
||||
; |
||||
break; |
||||
case ACCESS: |
||||
return; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl) |
||||
{ |
||||
unsigned int state; |
||||
|
||||
while (1) { |
||||
state = readl(&pctl->stat) & PCTL_STAT_MASK; |
||||
switch (state) { |
||||
case INIT_MEM: |
||||
writel(CFG_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) |
||||
; |
||||
/* fallthrough */ |
||||
case CONFIG: |
||||
writel(GO_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) |
||||
; |
||||
break; |
||||
case ACCESS: |
||||
writel(SLEEP_STATE, &pctl->sctl); |
||||
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != |
||||
LOW_POWER) |
||||
; |
||||
break; |
||||
case LOW_POWER: |
||||
return; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* pctl should in low power mode when call this function */ |
||||
static void phy_softreset(struct dram_info *dram) |
||||
{ |
||||
struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; |
||||
struct rk322x_grf *grf = dram->grf; |
||||
|
||||
writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); |
||||
rockchip_udelay(1); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); |
||||
rockchip_udelay(5); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); |
||||
writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); |
||||
} |
||||
|
||||
/* bw: 2: 32bit, 1:16bit */ |
||||
static void set_bw(struct dram_info *dram, u32 bw) |
||||
{ |
||||
struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; |
||||
struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; |
||||
struct rk322x_grf *grf = dram->grf; |
||||
|
||||
if (bw == 1) { |
||||
setbits_le32(&pctl->ppcfg, 1); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4); |
||||
writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); |
||||
clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); |
||||
} else { |
||||
clrbits_le32(&pctl->ppcfg, 1); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4); |
||||
writel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN, |
||||
&grf->soc_con[0]); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); |
||||
setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); |
||||
} |
||||
} |
||||
|
||||
static void pctl_cfg(struct rk322x_ddr_pctl *pctl, |
||||
struct rk322x_sdram_params *sdram_params, |
||||
struct rk322x_grf *grf) |
||||
{ |
||||
u32 burst_len; |
||||
u32 bw; |
||||
u32 dramtype = sdram_params->base.dramtype; |
||||
|
||||
if (sdram_params->ch[0].bw == 2) |
||||
bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN; |
||||
else |
||||
bw = GRF_MSCH_NOC_16BIT_EN; |
||||
|
||||
writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); |
||||
writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); |
||||
writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); |
||||
writel(0x51010, &pctl->dfilpcfg0); |
||||
|
||||
writel(1, &pctl->dfitphyupdtype0); |
||||
writel(0x0d, &pctl->dfitphyrdlat); |
||||
writel(0, &pctl->dfitphywrdata); |
||||
|
||||
writel(0, &pctl->dfiupdcfg); |
||||
copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, |
||||
sizeof(struct rk322x_pctl_timing)); |
||||
if (dramtype == DDR3) { |
||||
writel((1 << 3) | (1 << 11), |
||||
&pctl->dfiodtcfg); |
||||
writel(7 << 16, &pctl->dfiodtcfg1); |
||||
writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); |
||||
writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat); |
||||
writel(500, &pctl->trsth); |
||||
writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | |
||||
DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | |
||||
1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, |
||||
&pctl->mcfg); |
||||
writel(bw | GRF_DDR3_EN, &grf->soc_con[0]); |
||||
} else { |
||||
if (sdram_params->phy_timing.bl & PHT_BL_8) |
||||
burst_len = MDDR_LPDDR2_BL_8; |
||||
else |
||||
burst_len = MDDR_LPDDR2_BL_4; |
||||
|
||||
writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); |
||||
writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat); |
||||
writel(0, &pctl->trsth); |
||||
if (dramtype == LPDDR2) { |
||||
writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | |
||||
LPDDR2_S4 | LPDDR2_EN | burst_len | |
||||
(6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | |
||||
1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, |
||||
&pctl->mcfg); |
||||
writel(0, &pctl->dfiodtcfg); |
||||
writel(0, &pctl->dfiodtcfg1); |
||||
} else { |
||||
writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | |
||||
LPDDR2_S4 | LPDDR3_EN | burst_len | |
||||
(6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | |
||||
1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, |
||||
&pctl->mcfg); |
||||
writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg); |
||||
writel((7 << 16) | 4, &pctl->dfiodtcfg1); |
||||
} |
||||
writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]); |
||||
} |
||||
setbits_le32(&pctl->scfg, 1); |
||||
} |
||||
|
||||
static void phy_cfg(struct chan_info *chan, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
struct rk322x_ddr_phy *ddr_phy = chan->phy; |
||||
struct rk322x_service_sys *axi_bus = chan->msch; |
||||
struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing; |
||||
struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing; |
||||
struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing; |
||||
u32 cmd_drv, clk_drv, dqs_drv, dqs_odt; |
||||
|
||||
writel(noc_timing->ddrtiming, &axi_bus->ddrtiming); |
||||
writel(noc_timing->ddrmode, &axi_bus->ddrmode); |
||||
writel(noc_timing->readlatency, &axi_bus->readlatency); |
||||
writel(noc_timing->activate, &axi_bus->activate); |
||||
writel(noc_timing->devtodev, &axi_bus->devtodev); |
||||
|
||||
switch (sdram_params->base.dramtype) { |
||||
case DDR3: |
||||
writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); |
||||
break; |
||||
case LPDDR2: |
||||
writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); |
||||
break; |
||||
default: |
||||
writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); |
||||
break; |
||||
} |
||||
|
||||
writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]); |
||||
writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); |
||||
|
||||
cmd_drv = PHY_RON_RTT_34OHM; |
||||
clk_drv = PHY_RON_RTT_45OHM; |
||||
dqs_drv = PHY_RON_RTT_34OHM; |
||||
if (sdram_params->base.dramtype == LPDDR2) |
||||
dqs_odt = PHY_RON_RTT_DISABLE; |
||||
else |
||||
dqs_odt = PHY_RON_RTT_225OHM; |
||||
|
||||
writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]); |
||||
clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3); |
||||
writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]); |
||||
writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]); |
||||
|
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]); |
||||
writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]); |
||||
|
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]); |
||||
writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]); |
||||
} |
||||
|
||||
void dram_cfg_rbc(struct chan_info *chan, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
char noc_config; |
||||
int i = 0; |
||||
struct rk322x_sdram_channel *config = &sdram_params->ch[0]; |
||||
struct rk322x_service_sys *axi_bus = chan->msch; |
||||
|
||||
move_to_config_state(chan->pctl); |
||||
|
||||
if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) { |
||||
if ((config->col + config->bw) == 12) { |
||||
i = 14; |
||||
goto finish; |
||||
} else if ((config->col + config->bw) == 11) { |
||||
i = 15; |
||||
goto finish; |
||||
} |
||||
} |
||||
noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) | |
||||
(config->col + config->bw - 11); |
||||
for (i = 0; i < 11; i++) { |
||||
if (noc_config == ddr_cfg_2_rbc[i]) |
||||
break; |
||||
} |
||||
|
||||
if (i < 11) |
||||
goto finish; |
||||
|
||||
noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) | |
||||
(config->col + config->bw - 11); |
||||
|
||||
for (i = 11; i < 14; i++) { |
||||
if (noc_config == ddr_cfg_2_rbc[i]) |
||||
break; |
||||
} |
||||
if (i < 14) |
||||
goto finish; |
||||
else |
||||
i = 0; |
||||
|
||||
finish: |
||||
writel(i, &axi_bus->ddrconf); |
||||
move_to_access_state(chan->pctl); |
||||
} |
||||
|
||||
static void dram_all_config(const struct dram_info *dram, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
struct rk322x_sdram_channel *info = &sdram_params->ch[0]; |
||||
u32 sys_reg = 0; |
||||
|
||||
sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; |
||||
sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT; |
||||
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0); |
||||
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0); |
||||
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0); |
||||
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0); |
||||
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0); |
||||
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0); |
||||
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0); |
||||
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0); |
||||
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0); |
||||
|
||||
writel(sys_reg, &dram->grf->os_reg[2]); |
||||
} |
||||
|
||||
#define TEST_PATTEN 0x5aa5f00f |
||||
|
||||
static int dram_cap_detect(struct dram_info *dram, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
u32 bw, row, col, addr; |
||||
u32 ret = 0; |
||||
struct rk322x_service_sys *axi_bus = dram->chan[0].msch; |
||||
|
||||
if (sdram_params->base.dramtype == DDR3) |
||||
sdram_params->ch[0].dbw = 1; |
||||
else |
||||
sdram_params->ch[0].dbw = 2; |
||||
|
||||
move_to_config_state(dram->chan[0].pctl); |
||||
/* bw detect */ |
||||
set_bw(dram, 2); |
||||
if (data_training(&dram->chan[0]) == 0) { |
||||
bw = 2; |
||||
} else { |
||||
bw = 1; |
||||
set_bw(dram, 1); |
||||
move_to_lowpower_state(dram->chan[0].pctl); |
||||
phy_softreset(dram); |
||||
move_to_config_state(dram->chan[0].pctl); |
||||
if (data_training(&dram->chan[0])) { |
||||
printf("BW detect error\n"); |
||||
ret = -EINVAL; |
||||
} |
||||
} |
||||
sdram_params->ch[0].bw = bw; |
||||
sdram_params->ch[0].bk = 3; |
||||
|
||||
if (bw == 2) |
||||
writel(6, &axi_bus->ddrconf); |
||||
else |
||||
writel(3, &axi_bus->ddrconf); |
||||
move_to_access_state(dram->chan[0].pctl); |
||||
for (col = 11; col >= 9; col--) { |
||||
writel(0, CONFIG_SYS_SDRAM_BASE); |
||||
addr = CONFIG_SYS_SDRAM_BASE + |
||||
(1 << (col + bw - 1)); |
||||
writel(TEST_PATTEN, addr); |
||||
if ((readl(addr) == TEST_PATTEN) && |
||||
(readl(CONFIG_SYS_SDRAM_BASE) == 0)) |
||||
break; |
||||
} |
||||
if (col == 8) { |
||||
printf("Col detect error\n"); |
||||
ret = -EINVAL; |
||||
goto out; |
||||
} else { |
||||
sdram_params->ch[0].col = col; |
||||
} |
||||
|
||||
writel(10, &axi_bus->ddrconf); |
||||
|
||||
/* Detect row*/ |
||||
for (row = 16; row >= 12; row--) { |
||||
writel(0, CONFIG_SYS_SDRAM_BASE); |
||||
addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); |
||||
writel(TEST_PATTEN, addr); |
||||
if ((readl(addr) == TEST_PATTEN) && |
||||
(readl(CONFIG_SYS_SDRAM_BASE) == 0)) |
||||
break; |
||||
} |
||||
if (row == 11) { |
||||
printf("Row detect error\n"); |
||||
ret = -EINVAL; |
||||
} else { |
||||
sdram_params->ch[0].cs1_row = row; |
||||
sdram_params->ch[0].row_3_4 = 0; |
||||
sdram_params->ch[0].cs0_row = row; |
||||
} |
||||
/* cs detect */ |
||||
writel(0, CONFIG_SYS_SDRAM_BASE); |
||||
writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); |
||||
writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); |
||||
if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && |
||||
(readl(CONFIG_SYS_SDRAM_BASE) == 0)) |
||||
sdram_params->ch[0].rank = 2; |
||||
else |
||||
sdram_params->ch[0].rank = 1; |
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
static int sdram_init(struct dram_info *dram, |
||||
struct rk322x_sdram_params *sdram_params) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = clk_set_rate(&dram->ddr_clk, |
||||
sdram_params->base.ddr_freq * MHz * 2); |
||||
if (ret < 0) { |
||||
printf("Could not set DDR clock\n"); |
||||
return ret; |
||||
} |
||||
|
||||
phy_pctrl_reset(dram->cru, dram->chan[0].phy); |
||||
phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq); |
||||
pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); |
||||
phy_cfg(&dram->chan[0], sdram_params); |
||||
writel(POWER_UP_START, &dram->chan[0].pctl->powctl); |
||||
while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE)) |
||||
; |
||||
memory_init(&dram->chan[0], sdram_params); |
||||
move_to_access_state(dram->chan[0].pctl); |
||||
ret = dram_cap_detect(dram, sdram_params); |
||||
if (ret) |
||||
goto out; |
||||
dram_cfg_rbc(&dram->chan[0], sdram_params); |
||||
dram_all_config(dram, sdram_params); |
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
#if !CONFIG_IS_ENABLED(OF_PLATDATA) |
||||
struct rk322x_sdram_params *params = dev_get_platdata(dev); |
||||
const void *blob = gd->fdt_blob; |
||||
int node = dev_of_offset(dev); |
||||
int ret; |
||||
|
||||
params->num_channels = 1; |
||||
|
||||
ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", |
||||
(u32 *)¶ms->pctl_timing, |
||||
sizeof(params->pctl_timing) / sizeof(u32)); |
||||
if (ret) { |
||||
printf("%s: Cannot read rockchip,pctl-timing\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", |
||||
(u32 *)¶ms->phy_timing, |
||||
sizeof(params->phy_timing) / sizeof(u32)); |
||||
if (ret) { |
||||
printf("%s: Cannot read rockchip,phy-timing\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", |
||||
(u32 *)¶ms->base, |
||||
sizeof(params->base) / sizeof(u32)); |
||||
if (ret) { |
||||
printf("%s: Cannot read rockchip,sdram-params\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
ret = regmap_init_mem(dev, ¶ms->map); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_TPL_BUILD */ |
||||
|
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA) |
||||
static int conv_of_platdata(struct udevice *dev) |
||||
{ |
||||
struct rk322x_sdram_params *plat = dev_get_platdata(dev); |
||||
struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat; |
||||
int ret; |
||||
|
||||
memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, |
||||
sizeof(plat->pctl_timing)); |
||||
memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, |
||||
sizeof(plat->phy_timing)); |
||||
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); |
||||
|
||||
plat->num_channels = 1; |
||||
ret = regmap_init_mem_platdata(dev, of_plat->reg, |
||||
ARRAY_SIZE(of_plat->reg) / 2, |
||||
&plat->map); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
static int rk322x_dmc_probe(struct udevice *dev) |
||||
{ |
||||
#ifdef CONFIG_TPL_BUILD |
||||
struct rk322x_sdram_params *plat = dev_get_platdata(dev); |
||||
int ret; |
||||
struct udevice *dev_clk; |
||||
#endif |
||||
struct dram_info *priv = dev_get_priv(dev); |
||||
|
||||
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
||||
#ifdef CONFIG_TPL_BUILD |
||||
#if CONFIG_IS_ENABLED(OF_PLATDATA) |
||||
ret = conv_of_platdata(dev); |
||||
if (ret) |
||||
return ret; |
||||
#endif |
||||
|
||||
priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH); |
||||
priv->chan[0].pctl = regmap_get_range(plat->map, 0); |
||||
priv->chan[0].phy = regmap_get_range(plat->map, 1); |
||||
ret = rockchip_get_clk(&dev_clk); |
||||
if (ret) |
||||
return ret; |
||||
priv->ddr_clk.id = CLK_DDR; |
||||
ret = clk_request(dev_clk, &priv->ddr_clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
priv->cru = rockchip_get_cru(); |
||||
if (IS_ERR(priv->cru)) |
||||
return PTR_ERR(priv->cru); |
||||
ret = sdram_init(priv, plat); |
||||
if (ret) |
||||
return ret; |
||||
#else |
||||
priv->info.base = CONFIG_SYS_SDRAM_BASE; |
||||
priv->info.size = rockchip_sdram_size( |
||||
(phys_addr_t)&priv->grf->os_reg[2]); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info) |
||||
{ |
||||
struct dram_info *priv = dev_get_priv(dev); |
||||
|
||||
*info = priv->info; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct ram_ops rk322x_dmc_ops = { |
||||
.get_info = rk322x_dmc_get_info, |
||||
}; |
||||
|
||||
static const struct udevice_id rk322x_dmc_ids[] = { |
||||
{ .compatible = "rockchip,rk3228-dmc" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(dmc_rk322x) = { |
||||
.name = "rockchip_rk322x_dmc", |
||||
.id = UCLASS_RAM, |
||||
.of_match = rk322x_dmc_ids, |
||||
.ops = &rk322x_dmc_ops, |
||||
#ifdef CONFIG_TPL_BUILD |
||||
.ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata, |
||||
#endif |
||||
.probe = rk322x_dmc_probe, |
||||
.priv_auto_alloc_size = sizeof(struct dram_info), |
||||
#ifdef CONFIG_TPL_BUILD |
||||
.platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params), |
||||
#endif |
||||
}; |
||||
|
||||
Loading…
Reference in new issue