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@ -1,6 +1,6 @@ |
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/* |
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* This device tree is copied from |
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* https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/ |
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* https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi |
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*/ |
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#include "skeleton.dtsi" |
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@ -36,6 +36,22 @@ |
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reg = <0x1e6c0080 0x80>; |
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}; |
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mac0: ethernet@1e660000 { |
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compatible = "faraday,ftgmac100"; |
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reg = <0x1e660000 0x180>; |
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interrupts = <2>; |
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no-hw-checksum; |
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status = "disabled"; |
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}; |
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mac1: ethernet@1e680000 { |
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compatible = "faraday,ftgmac100"; |
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reg = <0x1e680000 0x180>; |
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interrupts = <3>; |
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no-hw-checksum; |
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status = "disabled"; |
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}; |
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apb { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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@ -48,6 +64,822 @@ |
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reg = <0x1e6e2070 0x04>; |
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}; |
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syscon: syscon@1e6e2000 { |
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compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; |
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reg = <0x1e6e2000 0x1a8>; |
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pinctrl: pinctrl { |
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compatible = "aspeed,g5-pinctrl"; |
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aspeed,external-nodes = <&gfx &lhc>; |
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pinctrl_acpi_default: acpi_default { |
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function = "ACPI"; |
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groups = "ACPI"; |
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}; |
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pinctrl_adc0_default: adc0_default { |
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function = "ADC0"; |
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groups = "ADC0"; |
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}; |
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pinctrl_adc1_default: adc1_default { |
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function = "ADC1"; |
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groups = "ADC1"; |
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}; |
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pinctrl_adc10_default: adc10_default { |
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function = "ADC10"; |
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groups = "ADC10"; |
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}; |
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pinctrl_adc11_default: adc11_default { |
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function = "ADC11"; |
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groups = "ADC11"; |
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}; |
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pinctrl_adc12_default: adc12_default { |
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function = "ADC12"; |
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groups = "ADC12"; |
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}; |
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pinctrl_adc13_default: adc13_default { |
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function = "ADC13"; |
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groups = "ADC13"; |
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}; |
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pinctrl_adc14_default: adc14_default { |
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function = "ADC14"; |
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groups = "ADC14"; |
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}; |
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pinctrl_adc15_default: adc15_default { |
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function = "ADC15"; |
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groups = "ADC15"; |
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}; |
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pinctrl_adc2_default: adc2_default { |
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function = "ADC2"; |
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groups = "ADC2"; |
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}; |
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pinctrl_adc3_default: adc3_default { |
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function = "ADC3"; |
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groups = "ADC3"; |
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}; |
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pinctrl_adc4_default: adc4_default { |
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function = "ADC4"; |
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groups = "ADC4"; |
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}; |
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pinctrl_adc5_default: adc5_default { |
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function = "ADC5"; |
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groups = "ADC5"; |
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}; |
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pinctrl_adc6_default: adc6_default { |
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function = "ADC6"; |
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groups = "ADC6"; |
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}; |
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pinctrl_adc7_default: adc7_default { |
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function = "ADC7"; |
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groups = "ADC7"; |
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}; |
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pinctrl_adc8_default: adc8_default { |
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function = "ADC8"; |
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groups = "ADC8"; |
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}; |
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pinctrl_adc9_default: adc9_default { |
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function = "ADC9"; |
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groups = "ADC9"; |
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}; |
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pinctrl_bmcint_default: bmcint_default { |
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function = "BMCINT"; |
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groups = "BMCINT"; |
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}; |
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pinctrl_ddcclk_default: ddcclk_default { |
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function = "DDCCLK"; |
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groups = "DDCCLK"; |
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}; |
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pinctrl_ddcdat_default: ddcdat_default { |
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function = "DDCDAT"; |
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groups = "DDCDAT"; |
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}; |
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pinctrl_espi_default: espi_default { |
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function = "ESPI"; |
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groups = "ESPI"; |
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}; |
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pinctrl_fwspics1_default: fwspics1_default { |
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function = "FWSPICS1"; |
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groups = "FWSPICS1"; |
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}; |
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pinctrl_fwspics2_default: fwspics2_default { |
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function = "FWSPICS2"; |
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groups = "FWSPICS2"; |
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}; |
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pinctrl_gpid0_default: gpid0_default { |
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function = "GPID0"; |
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groups = "GPID0"; |
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}; |
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pinctrl_gpid2_default: gpid2_default { |
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function = "GPID2"; |
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groups = "GPID2"; |
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}; |
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pinctrl_gpid4_default: gpid4_default { |
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function = "GPID4"; |
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groups = "GPID4"; |
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}; |
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pinctrl_gpid6_default: gpid6_default { |
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function = "GPID6"; |
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groups = "GPID6"; |
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}; |
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pinctrl_gpie0_default: gpie0_default { |
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function = "GPIE0"; |
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groups = "GPIE0"; |
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}; |
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pinctrl_gpie2_default: gpie2_default { |
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function = "GPIE2"; |
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groups = "GPIE2"; |
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}; |
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pinctrl_gpie4_default: gpie4_default { |
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function = "GPIE4"; |
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groups = "GPIE4"; |
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}; |
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pinctrl_gpie6_default: gpie6_default { |
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function = "GPIE6"; |
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groups = "GPIE6"; |
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}; |
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pinctrl_i2c10_default: i2c10_default { |
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function = "I2C10"; |
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groups = "I2C10"; |
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}; |
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pinctrl_i2c11_default: i2c11_default { |
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function = "I2C11"; |
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groups = "I2C11"; |
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}; |
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pinctrl_i2c12_default: i2c12_default { |
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function = "I2C12"; |
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groups = "I2C12"; |
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}; |
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pinctrl_i2c13_default: i2c13_default { |
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function = "I2C13"; |
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groups = "I2C13"; |
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}; |
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pinctrl_i2c14_default: i2c14_default { |
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function = "I2C14"; |
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groups = "I2C14"; |
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}; |
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pinctrl_i2c3_default: i2c3_default { |
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function = "I2C3"; |
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groups = "I2C3"; |
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}; |
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pinctrl_i2c4_default: i2c4_default { |
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function = "I2C4"; |
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groups = "I2C4"; |
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}; |
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pinctrl_i2c5_default: i2c5_default { |
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function = "I2C5"; |
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groups = "I2C5"; |
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}; |
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pinctrl_i2c6_default: i2c6_default { |
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function = "I2C6"; |
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groups = "I2C6"; |
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}; |
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pinctrl_i2c7_default: i2c7_default { |
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function = "I2C7"; |
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groups = "I2C7"; |
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}; |
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pinctrl_i2c8_default: i2c8_default { |
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function = "I2C8"; |
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groups = "I2C8"; |
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}; |
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pinctrl_i2c9_default: i2c9_default { |
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function = "I2C9"; |
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groups = "I2C9"; |
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}; |
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pinctrl_lad0_default: lad0_default { |
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function = "LAD0"; |
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groups = "LAD0"; |
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}; |
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pinctrl_lad1_default: lad1_default { |
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function = "LAD1"; |
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groups = "LAD1"; |
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}; |
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pinctrl_lad2_default: lad2_default { |
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function = "LAD2"; |
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groups = "LAD2"; |
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}; |
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pinctrl_lad3_default: lad3_default { |
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function = "LAD3"; |
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groups = "LAD3"; |
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}; |
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pinctrl_lclk_default: lclk_default { |
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function = "LCLK"; |
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groups = "LCLK"; |
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}; |
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pinctrl_lframe_default: lframe_default { |
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function = "LFRAME"; |
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groups = "LFRAME"; |
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}; |
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pinctrl_lpchc_default: lpchc_default { |
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function = "LPCHC"; |
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groups = "LPCHC"; |
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}; |
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pinctrl_lpcpd_default: lpcpd_default { |
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function = "LPCPD"; |
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groups = "LPCPD"; |
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}; |
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pinctrl_lpcplus_default: lpcplus_default { |
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function = "LPCPLUS"; |
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groups = "LPCPLUS"; |
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}; |
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pinctrl_lpcpme_default: lpcpme_default { |
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function = "LPCPME"; |
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groups = "LPCPME"; |
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}; |
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pinctrl_lpcrst_default: lpcrst_default { |
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function = "LPCRST"; |
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groups = "LPCRST"; |
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}; |
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pinctrl_lpcsmi_default: lpcsmi_default { |
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function = "LPCSMI"; |
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groups = "LPCSMI"; |
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}; |
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pinctrl_lsirq_default: lsirq_default { |
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function = "LSIRQ"; |
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groups = "LSIRQ"; |
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}; |
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pinctrl_mac1link_default: mac1link_default { |
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function = "MAC1LINK"; |
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groups = "MAC1LINK"; |
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}; |
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pinctrl_mac2link_default: mac2link_default { |
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function = "MAC2LINK"; |
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groups = "MAC2LINK"; |
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}; |
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pinctrl_mdio1_default: mdio1_default { |
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function = "MDIO1"; |
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groups = "MDIO1"; |
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}; |
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pinctrl_mdio2_default: mdio2_default { |
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function = "MDIO2"; |
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groups = "MDIO2"; |
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}; |
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pinctrl_ncts1_default: ncts1_default { |
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function = "NCTS1"; |
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groups = "NCTS1"; |
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}; |
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pinctrl_ncts2_default: ncts2_default { |
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function = "NCTS2"; |
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groups = "NCTS2"; |
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}; |
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pinctrl_ncts3_default: ncts3_default { |
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function = "NCTS3"; |
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groups = "NCTS3"; |
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}; |
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pinctrl_ncts4_default: ncts4_default { |
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function = "NCTS4"; |
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groups = "NCTS4"; |
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}; |
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pinctrl_ndcd1_default: ndcd1_default { |
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function = "NDCD1"; |
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groups = "NDCD1"; |
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}; |
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pinctrl_ndcd2_default: ndcd2_default { |
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function = "NDCD2"; |
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groups = "NDCD2"; |
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}; |
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pinctrl_ndcd3_default: ndcd3_default { |
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function = "NDCD3"; |
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groups = "NDCD3"; |
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}; |
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pinctrl_ndcd4_default: ndcd4_default { |
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function = "NDCD4"; |
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|
|
|
groups = "NDCD4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndsr1_default: ndsr1_default { |
|
|
|
|
function = "NDSR1"; |
|
|
|
|
groups = "NDSR1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndsr2_default: ndsr2_default { |
|
|
|
|
function = "NDSR2"; |
|
|
|
|
groups = "NDSR2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndsr3_default: ndsr3_default { |
|
|
|
|
function = "NDSR3"; |
|
|
|
|
groups = "NDSR3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndsr4_default: ndsr4_default { |
|
|
|
|
function = "NDSR4"; |
|
|
|
|
groups = "NDSR4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndtr1_default: ndtr1_default { |
|
|
|
|
function = "NDTR1"; |
|
|
|
|
groups = "NDTR1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndtr2_default: ndtr2_default { |
|
|
|
|
function = "NDTR2"; |
|
|
|
|
groups = "NDTR2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndtr3_default: ndtr3_default { |
|
|
|
|
function = "NDTR3"; |
|
|
|
|
groups = "NDTR3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_ndtr4_default: ndtr4_default { |
|
|
|
|
function = "NDTR4"; |
|
|
|
|
groups = "NDTR4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nri1_default: nri1_default { |
|
|
|
|
function = "NRI1"; |
|
|
|
|
groups = "NRI1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nri2_default: nri2_default { |
|
|
|
|
function = "NRI2"; |
|
|
|
|
groups = "NRI2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nri3_default: nri3_default { |
|
|
|
|
function = "NRI3"; |
|
|
|
|
groups = "NRI3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nri4_default: nri4_default { |
|
|
|
|
function = "NRI4"; |
|
|
|
|
groups = "NRI4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nrts1_default: nrts1_default { |
|
|
|
|
function = "NRTS1"; |
|
|
|
|
groups = "NRTS1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nrts2_default: nrts2_default { |
|
|
|
|
function = "NRTS2"; |
|
|
|
|
groups = "NRTS2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nrts3_default: nrts3_default { |
|
|
|
|
function = "NRTS3"; |
|
|
|
|
groups = "NRTS3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_nrts4_default: nrts4_default { |
|
|
|
|
function = "NRTS4"; |
|
|
|
|
groups = "NRTS4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_oscclk_default: oscclk_default { |
|
|
|
|
function = "OSCCLK"; |
|
|
|
|
groups = "OSCCLK"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pewake_default: pewake_default { |
|
|
|
|
function = "PEWAKE"; |
|
|
|
|
groups = "PEWAKE"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pnor_default: pnor_default { |
|
|
|
|
function = "PNOR"; |
|
|
|
|
groups = "PNOR"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm0_default: pwm0_default { |
|
|
|
|
function = "PWM0"; |
|
|
|
|
groups = "PWM0"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm1_default: pwm1_default { |
|
|
|
|
function = "PWM1"; |
|
|
|
|
groups = "PWM1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm2_default: pwm2_default { |
|
|
|
|
function = "PWM2"; |
|
|
|
|
groups = "PWM2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm3_default: pwm3_default { |
|
|
|
|
function = "PWM3"; |
|
|
|
|
groups = "PWM3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm4_default: pwm4_default { |
|
|
|
|
function = "PWM4"; |
|
|
|
|
groups = "PWM4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm5_default: pwm5_default { |
|
|
|
|
function = "PWM5"; |
|
|
|
|
groups = "PWM5"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm6_default: pwm6_default { |
|
|
|
|
function = "PWM6"; |
|
|
|
|
groups = "PWM6"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_pwm7_default: pwm7_default { |
|
|
|
|
function = "PWM7"; |
|
|
|
|
groups = "PWM7"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rgmii1_default: rgmii1_default { |
|
|
|
|
function = "RGMII1"; |
|
|
|
|
groups = "RGMII1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rgmii2_default: rgmii2_default { |
|
|
|
|
function = "RGMII2"; |
|
|
|
|
groups = "RGMII2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rmii1_default: rmii1_default { |
|
|
|
|
function = "RMII1"; |
|
|
|
|
groups = "RMII1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rmii2_default: rmii2_default { |
|
|
|
|
function = "RMII2"; |
|
|
|
|
groups = "RMII2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rxd1_default: rxd1_default { |
|
|
|
|
function = "RXD1"; |
|
|
|
|
groups = "RXD1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rxd2_default: rxd2_default { |
|
|
|
|
function = "RXD2"; |
|
|
|
|
groups = "RXD2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rxd3_default: rxd3_default { |
|
|
|
|
function = "RXD3"; |
|
|
|
|
groups = "RXD3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_rxd4_default: rxd4_default { |
|
|
|
|
function = "RXD4"; |
|
|
|
|
groups = "RXD4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt1_default: salt1_default { |
|
|
|
|
function = "SALT1"; |
|
|
|
|
groups = "SALT1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt10_default: salt10_default { |
|
|
|
|
function = "SALT10"; |
|
|
|
|
groups = "SALT10"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt11_default: salt11_default { |
|
|
|
|
function = "SALT11"; |
|
|
|
|
groups = "SALT11"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt12_default: salt12_default { |
|
|
|
|
function = "SALT12"; |
|
|
|
|
groups = "SALT12"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt13_default: salt13_default { |
|
|
|
|
function = "SALT13"; |
|
|
|
|
groups = "SALT13"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt14_default: salt14_default { |
|
|
|
|
function = "SALT14"; |
|
|
|
|
groups = "SALT14"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt2_default: salt2_default { |
|
|
|
|
function = "SALT2"; |
|
|
|
|
groups = "SALT2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt3_default: salt3_default { |
|
|
|
|
function = "SALT3"; |
|
|
|
|
groups = "SALT3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt4_default: salt4_default { |
|
|
|
|
function = "SALT4"; |
|
|
|
|
groups = "SALT4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt5_default: salt5_default { |
|
|
|
|
function = "SALT5"; |
|
|
|
|
groups = "SALT5"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt6_default: salt6_default { |
|
|
|
|
function = "SALT6"; |
|
|
|
|
groups = "SALT6"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt7_default: salt7_default { |
|
|
|
|
function = "SALT7"; |
|
|
|
|
groups = "SALT7"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt8_default: salt8_default { |
|
|
|
|
function = "SALT8"; |
|
|
|
|
groups = "SALT8"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_salt9_default: salt9_default { |
|
|
|
|
function = "SALT9"; |
|
|
|
|
groups = "SALT9"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_scl1_default: scl1_default { |
|
|
|
|
function = "SCL1"; |
|
|
|
|
groups = "SCL1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_scl2_default: scl2_default { |
|
|
|
|
function = "SCL2"; |
|
|
|
|
groups = "SCL2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sd1_default: sd1_default { |
|
|
|
|
function = "SD1"; |
|
|
|
|
groups = "SD1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sd2_default: sd2_default { |
|
|
|
|
function = "SD2"; |
|
|
|
|
groups = "SD2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sda1_default: sda1_default { |
|
|
|
|
function = "SDA1"; |
|
|
|
|
groups = "SDA1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sda2_default: sda2_default { |
|
|
|
|
function = "SDA2"; |
|
|
|
|
groups = "SDA2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sgps1_default: sgps1_default { |
|
|
|
|
function = "SGPS1"; |
|
|
|
|
groups = "SGPS1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sgps2_default: sgps2_default { |
|
|
|
|
function = "SGPS2"; |
|
|
|
|
groups = "SGPS2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sioonctrl_default: sioonctrl_default { |
|
|
|
|
function = "SIOONCTRL"; |
|
|
|
|
groups = "SIOONCTRL"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_siopbi_default: siopbi_default { |
|
|
|
|
function = "SIOPBI"; |
|
|
|
|
groups = "SIOPBI"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_siopbo_default: siopbo_default { |
|
|
|
|
function = "SIOPBO"; |
|
|
|
|
groups = "SIOPBO"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_siopwreq_default: siopwreq_default { |
|
|
|
|
function = "SIOPWREQ"; |
|
|
|
|
groups = "SIOPWREQ"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_siopwrgd_default: siopwrgd_default { |
|
|
|
|
function = "SIOPWRGD"; |
|
|
|
|
groups = "SIOPWRGD"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sios3_default: sios3_default { |
|
|
|
|
function = "SIOS3"; |
|
|
|
|
groups = "SIOS3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_sios5_default: sios5_default { |
|
|
|
|
function = "SIOS5"; |
|
|
|
|
groups = "SIOS5"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_siosci_default: siosci_default { |
|
|
|
|
function = "SIOSCI"; |
|
|
|
|
groups = "SIOSCI"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi1_default: spi1_default { |
|
|
|
|
function = "SPI1"; |
|
|
|
|
groups = "SPI1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi1cs1_default: spi1cs1_default { |
|
|
|
|
function = "SPI1CS1"; |
|
|
|
|
groups = "SPI1CS1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi1debug_default: spi1debug_default { |
|
|
|
|
function = "SPI1DEBUG"; |
|
|
|
|
groups = "SPI1DEBUG"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi1passthru_default: spi1passthru_default { |
|
|
|
|
function = "SPI1PASSTHRU"; |
|
|
|
|
groups = "SPI1PASSTHRU"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi2ck_default: spi2ck_default { |
|
|
|
|
function = "SPI2CK"; |
|
|
|
|
groups = "SPI2CK"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi2cs0_default: spi2cs0_default { |
|
|
|
|
function = "SPI2CS0"; |
|
|
|
|
groups = "SPI2CS0"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi2cs1_default: spi2cs1_default { |
|
|
|
|
function = "SPI2CS1"; |
|
|
|
|
groups = "SPI2CS1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi2miso_default: spi2miso_default { |
|
|
|
|
function = "SPI2MISO"; |
|
|
|
|
groups = "SPI2MISO"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_spi2mosi_default: spi2mosi_default { |
|
|
|
|
function = "SPI2MOSI"; |
|
|
|
|
groups = "SPI2MOSI"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_timer3_default: timer3_default { |
|
|
|
|
function = "TIMER3"; |
|
|
|
|
groups = "TIMER3"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_timer4_default: timer4_default { |
|
|
|
|
function = "TIMER4"; |
|
|
|
|
groups = "TIMER4"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_timer5_default: timer5_default { |
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function = "TIMER5"; |
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groups = "TIMER5"; |
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}; |
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|
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pinctrl_timer6_default: timer6_default { |
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function = "TIMER6"; |
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groups = "TIMER6"; |
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}; |
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|
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pinctrl_timer7_default: timer7_default { |
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function = "TIMER7"; |
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groups = "TIMER7"; |
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}; |
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pinctrl_timer8_default: timer8_default { |
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function = "TIMER8"; |
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groups = "TIMER8"; |
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}; |
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pinctrl_txd1_default: txd1_default { |
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function = "TXD1"; |
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groups = "TXD1"; |
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}; |
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pinctrl_txd2_default: txd2_default { |
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function = "TXD2"; |
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groups = "TXD2"; |
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}; |
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pinctrl_txd3_default: txd3_default { |
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function = "TXD3"; |
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groups = "TXD3"; |
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}; |
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pinctrl_txd4_default: txd4_default { |
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function = "TXD4"; |
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groups = "TXD4"; |
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}; |
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|
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|
pinctrl_uart6_default: uart6_default { |
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|
function = "UART6"; |
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|
groups = "UART6"; |
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|
}; |
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|
|
|
pinctrl_usbcki_default: usbcki_default { |
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|
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|
function = "USBCKI"; |
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|
groups = "USBCKI"; |
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|
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|
}; |
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|
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|
|
|
pinctrl_vgabiosrom_default: vgabiosrom_default { |
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|
|
|
function = "VGABIOSROM"; |
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|
groups = "VGABIOSROM"; |
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|
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|
}; |
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|
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|
|
pinctrl_vgahs_default: vgahs_default { |
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|
|
|
function = "VGAHS"; |
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|
|
groups = "VGAHS"; |
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|
|
|
}; |
|
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|
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|
|
|
|
pinctrl_vgavs_default: vgavs_default { |
|
|
|
|
function = "VGAVS"; |
|
|
|
|
groups = "VGAVS"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_vpi24_default: vpi24_default { |
|
|
|
|
function = "VPI24"; |
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|
|
|
groups = "VPI24"; |
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|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_vpo_default: vpo_default { |
|
|
|
|
function = "VPO"; |
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|
|
|
groups = "VPO"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_wdtrst1_default: wdtrst1_default { |
|
|
|
|
function = "WDTRST1"; |
|
|
|
|
groups = "WDTRST1"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
pinctrl_wdtrst2_default: wdtrst2_default { |
|
|
|
|
function = "WDTRST2"; |
|
|
|
|
groups = "WDTRST2"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
clk_hpll: clk_hpll@1e6e2024 { |
|
|
|
|
#clock-cells = <0>; |
|
|
|
|
compatible = "aspeed,g5-hpll-clock"; |
|
|
|
@ -75,11 +907,27 @@ |
|
|
|
|
reg = <0x1e6e202c 0x4>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
gfx: display@1e6e6000 { |
|
|
|
|
compatible = "aspeed,ast2500-gfx", "syscon"; |
|
|
|
|
reg = <0x1e6e6000 0x1000>; |
|
|
|
|
reg-io-width = <4>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
sram@1e720000 { |
|
|
|
|
compatible = "mmio-sram"; |
|
|
|
|
reg = <0x1e720000 0x9000>; // 36K |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
gpio: gpio@1e780000 { |
|
|
|
|
#gpio-cells = <2>; |
|
|
|
|
gpio-controller; |
|
|
|
|
compatible = "aspeed,ast2500-gpio"; |
|
|
|
|
reg = <0x1e780000 0x1000>; |
|
|
|
|
interrupts = <20>; |
|
|
|
|
gpio-ranges = <&pinctrl 0 0 220>; |
|
|
|
|
interrupt-controller; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
timer: timer@1e782000 { |
|
|
|
|
compatible = "aspeed,ast2400-timer"; |
|
|
|
|
reg = <0x1e782000 0x90>; |
|
|
|
@ -90,6 +938,7 @@ |
|
|
|
|
clocks = <&clk_apb>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
wdt1: wdt@1e785000 { |
|
|
|
|
compatible = "aspeed,wdt"; |
|
|
|
|
reg = <0x1e785000 0x1c>; |
|
|
|
@ -119,6 +968,36 @@ |
|
|
|
|
status = "disabled"; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
lpc: lpc@1e789000 { |
|
|
|
|
compatible = "aspeed,ast2500-lpc", "simple-mfd"; |
|
|
|
|
reg = <0x1e789000 0x1000>; |
|
|
|
|
|
|
|
|
|
#address-cells = <1>; |
|
|
|
|
#size-cells = <1>; |
|
|
|
|
ranges = <0 0x1e789000 0x1000>; |
|
|
|
|
|
|
|
|
|
lpc_bmc: lpc-bmc@0 { |
|
|
|
|
compatible = "aspeed,ast2500-lpc-bmc"; |
|
|
|
|
reg = <0x0 0x80>; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
lpc_host: lpc-host@80 { |
|
|
|
|
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; |
|
|
|
|
reg = <0x80 0x1e0>; |
|
|
|
|
|
|
|
|
|
#address-cells = <1>; |
|
|
|
|
#size-cells = <1>; |
|
|
|
|
ranges = <0 0x80 0x1e0>; |
|
|
|
|
|
|
|
|
|
reg-io-width = <4>; |
|
|
|
|
|
|
|
|
|
lhc: lhc@20 { |
|
|
|
|
compatible = "aspeed,ast2500-lhc"; |
|
|
|
|
reg = <0x20 0x24 0x48 0x8>; |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
uart2: serial@1e78d000 { |
|
|
|
|
compatible = "ns16550a"; |
|
|
|
|
reg = <0x1e78d000 0x1000>; |
|
|
|
|