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@ -29,6 +29,9 @@ |
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#define I2C_TIMEOUT (CFG_HZ / 4) |
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#define I2C_READ_BIT 1 |
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#define I2C_WRITE_BIT 0 |
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization |
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* runs from ROM, and we can't switch buses because we can't modify |
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@ -110,7 +113,7 @@ i2c_wait(int write) |
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return -1; |
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} |
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if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { |
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { |
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debug("i2c_wait: No RXACK\n"); |
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return -1; |
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} |
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@ -131,7 +134,7 @@ i2c_write_addr (u8 dev, u8 dir, int rsta) |
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writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); |
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if (i2c_wait(I2C_WRITE) < 0) |
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if (i2c_wait(I2C_WRITE_BIT) < 0) |
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return 0; |
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return 1; |
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@ -148,7 +151,7 @@ __i2c_write(u8 *data, int length) |
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for (i = 0; i < length; i++) { |
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writeb(data[i], &i2c_dev[i2c_bus_num]->dr); |
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if (i2c_wait(I2C_WRITE) < 0) |
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if (i2c_wait(I2C_WRITE_BIT) < 0) |
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break; |
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} |
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@ -167,7 +170,7 @@ __i2c_read(u8 *data, int length) |
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readb(&i2c_dev[i2c_bus_num]->dr); |
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for (i = 0; i < length; i++) { |
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if (i2c_wait(I2C_READ) < 0) |
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if (i2c_wait(I2C_READ_BIT) < 0) |
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break; |
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/* Generate ack on last next to last byte */ |
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@ -192,9 +195,9 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) |
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u8 *a = (u8*)&addr; |
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if (i2c_wait4bus() >= 0 |
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&& i2c_write_addr(dev, I2C_WRITE, 0) != 0 |
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 |
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&& __i2c_write(&a[4 - alen], alen) == alen |
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&& i2c_write_addr(dev, I2C_READ, 1) != 0) { |
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&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) { |
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i = __i2c_read(data, length); |
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} |
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@ -213,7 +216,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) |
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u8 *a = (u8*)&addr; |
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if (i2c_wait4bus() >= 0 |
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&& i2c_write_addr(dev, I2C_WRITE, 0) != 0 |
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 |
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&& __i2c_write(&a[4 - alen], alen) == alen) { |
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i = __i2c_write(data, length); |
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} |
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