Tom Rini
8 years ago
commit
19d1f1a2f3
@ -0,0 +1,100 @@ |
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/*
|
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* Copyright (C) 2017 Intel Corporation <www.intel.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#ifndef _FPGA_MANAGER_ARRIA10_H_ |
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#define _FPGA_MANAGER_ARRIA10_H_ |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) |
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) |
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) |
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) |
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) |
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) |
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#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) |
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#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) |
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 |
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) |
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 |
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#ifndef __ASSEMBLY__ |
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struct socfpga_fpga_manager { |
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u32 _pad_0x0_0x7[2]; |
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u32 dclkcnt; |
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u32 dclkstat; |
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u32 gpo; |
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u32 gpi; |
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u32 misci; |
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u32 _pad_0x1c_0x2f[5]; |
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u32 emr_data0; |
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u32 emr_data1; |
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u32 emr_data2; |
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u32 emr_data3; |
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u32 emr_data4; |
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u32 emr_data5; |
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u32 emr_valid; |
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u32 emr_en; |
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u32 jtag_config; |
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u32 jtag_status; |
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u32 jtag_kick; |
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u32 _pad_0x5c_0x5f; |
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u32 jtag_data_w; |
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u32 jtag_data_r; |
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u32 _pad_0x68_0x6f[2]; |
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u32 imgcfg_ctrl_00; |
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u32 imgcfg_ctrl_01; |
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u32 imgcfg_ctrl_02; |
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u32 _pad_0x7c_0x7f; |
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u32 imgcfg_stat; |
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u32 intr_masked_status; |
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u32 intr_mask; |
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u32 intr_polarity; |
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u32 dma_config; |
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u32 imgcfg_fifo_status; |
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}; |
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/* Functions */ |
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int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); |
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int fpgamgr_program_finish(void); |
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int is_fpgamgr_user_mode(void); |
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int fpgamgr_wait_early_user_mode(void); |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _FPGA_MANAGER_ARRIA10_H_ */ |
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@ -0,0 +1,68 @@ |
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> |
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* All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef _FPGA_MANAGER_GEN5_H_ |
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#define _FPGA_MANAGER_GEN5_H_ |
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#define FPGAMGRREGS_STAT_MODE_MASK 0x7 |
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#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 |
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#define FPGAMGRREGS_STAT_MSEL_LSB 3 |
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#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) |
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#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) |
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#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) |
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#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) |
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#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) |
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#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) |
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#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) |
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/* FPGA Mode */ |
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#define FPGAMGRREGS_MODE_FPGAOFF 0x0 |
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#define FPGAMGRREGS_MODE_RESETPHASE 0x1 |
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#define FPGAMGRREGS_MODE_CFGPHASE 0x2 |
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#define FPGAMGRREGS_MODE_INITPHASE 0x3 |
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#define FPGAMGRREGS_MODE_USERMODE 0x4 |
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#define FPGAMGRREGS_MODE_UNKNOWN 0x5 |
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#ifndef __ASSEMBLY__ |
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struct socfpga_fpga_manager { |
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/* FPGA Manager Module */ |
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u32 stat; /* 0x00 */ |
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u32 ctrl; |
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u32 dclkcnt; |
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u32 dclkstat; |
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u32 gpo; /* 0x10 */ |
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u32 gpi; |
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u32 misci; /* 0x18 */ |
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u32 _pad_0x1c_0x82c[517]; |
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/* Configuration Monitor (MON) Registers */ |
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u32 gpio_inten; /* 0x830 */ |
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u32 gpio_intmask; |
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u32 gpio_inttype_level; |
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u32 gpio_int_polarity; |
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u32 gpio_intstatus; /* 0x840 */ |
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u32 gpio_raw_intstatus; |
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u32 _pad_0x848; |
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u32 gpio_porta_eoi; |
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u32 gpio_ext_porta; /* 0x850 */ |
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u32 _pad_0x854_0x85c[3]; |
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u32 gpio_1s_sync; /* 0x860 */ |
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u32 _pad_0x864_0x868[2]; |
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u32 gpio_ver_id_code; |
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u32 gpio_config_reg2; /* 0x870 */ |
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u32 gpio_config_reg1; |
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}; |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _FPGA_MANAGER_GEN5_H_ */ |
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@ -0,0 +1,479 @@ |
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/*
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* Copyright (C) 2017 Intel Corporation <www.intel.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <asm/io.h> |
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#include <asm/arch/fpga_manager.h> |
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#include <asm/arch/reset_manager.h> |
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#include <asm/arch/system_manager.h> |
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#include <asm/arch/sdram.h> |
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#include <asm/arch/misc.h> |
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#include <altera.h> |
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#include <common.h> |
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#include <errno.h> |
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#include <wait_bit.h> |
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#include <watchdog.h> |
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#define CFGWDTH_32 1 |
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#define MIN_BITSTREAM_SIZECHECK 230 |
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#define ENCRYPTION_OFFSET 69 |
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#define COMPRESSION_OFFSET 229 |
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#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ |
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#define FPGA_TIMEOUT_CNT 0x1000000 |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct socfpga_fpga_manager *fpga_manager_base = |
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(void *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
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static const struct socfpga_system_manager *system_manager_base = |
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(void *)SOCFPGA_SYSMGR_ADDRESS; |
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static void fpgamgr_set_cd_ratio(unsigned long ratio); |
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static uint32_t fpgamgr_get_msel(void) |
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{ |
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u32 reg; |
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reg = readl(&fpga_manager_base->imgcfg_stat); |
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reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >> |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB; |
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return reg; |
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} |
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static void fpgamgr_set_cfgwdth(int width) |
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{ |
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if (width) |
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
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ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); |
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else |
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
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ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK); |
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} |
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int is_fpgamgr_user_mode(void) |
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{ |
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return (readl(&fpga_manager_base->imgcfg_stat) & |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0; |
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} |
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static int wait_for_user_mode(void) |
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{ |
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return wait_for_bit(__func__, |
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&fpga_manager_base->imgcfg_stat, |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK, |
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1, FPGA_TIMEOUT_MSEC, false); |
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} |
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static int is_fpgamgr_early_user_mode(void) |
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{ |
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return (readl(&fpga_manager_base->imgcfg_stat) & |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; |
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} |
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int fpgamgr_wait_early_user_mode(void) |
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{ |
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u32 sync_data = 0xffffffff; |
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u32 i = 0; |
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unsigned start = get_timer(0); |
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unsigned long cd_ratio; |
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/* Getting existing CDRATIO */ |
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cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & |
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >> |
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB; |
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/* Using CDRATIO_X1 for better compatibility */ |
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fpgamgr_set_cd_ratio(CDRATIO_x1); |
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while (!is_fpgamgr_early_user_mode()) { |
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if (get_timer(start) > FPGA_TIMEOUT_MSEC) |
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return -ETIMEDOUT; |
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fpgamgr_program_write((const long unsigned int *)&sync_data, |
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sizeof(sync_data)); |
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udelay(FPGA_TIMEOUT_MSEC); |
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i++; |
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} |
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debug("Additional %i sync word needed\n", i); |
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/* restoring original CDRATIO */ |
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fpgamgr_set_cd_ratio(cd_ratio); |
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return 0; |
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} |
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/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */ |
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static int wait_for_nconfig_pin_and_nstatus_pin(void) |
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{ |
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unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK | |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK; |
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/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
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* timeout at 1000ms |
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*/ |
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return wait_for_bit(__func__, |
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&fpga_manager_base->imgcfg_stat, |
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mask, |
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false, FPGA_TIMEOUT_MSEC, false); |
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} |
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static int wait_for_f2s_nstatus_pin(unsigned long value) |
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{ |
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/* Poll until f2s to specific value, timeout at 1000ms */ |
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return wait_for_bit(__func__, |
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&fpga_manager_base->imgcfg_stat, |
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ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK, |
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value, FPGA_TIMEOUT_MSEC, false); |
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} |
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/* set CD ratio */ |
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static void fpgamgr_set_cd_ratio(unsigned long ratio) |
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{ |
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); |
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
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(ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & |
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ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); |
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} |
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/* get the MSEL value, verify we are set for FPP configuration mode */ |
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static int fpgamgr_verify_msel(void) |
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{ |
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u32 msel = fpgamgr_get_msel(); |
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if (msel & ~BIT(0)) { |
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printf("Fail: read msel=%d\n", msel); |
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return -EPERM; |
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} |
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return 0; |
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} |
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/*
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* Write cdratio and cdwidth based on whether the bitstream is compressed |
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* and/or encoded |
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*/ |
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static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data, |
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size_t rbf_size) |
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{ |
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unsigned int cd_ratio; |
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bool encrypt, compress; |
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/*
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* According to the bitstream specification, |
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* both encryption and compression status are |
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* in location before offset 230 of the buffer. |
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*/ |
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if (rbf_size < MIN_BITSTREAM_SIZECHECK) |
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return -EINVAL; |
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encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3; |
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encrypt = encrypt != 0; |
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compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1; |
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compress = !compress; |
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debug("header word %d = %08x\n", 69, rbf_data[69]); |
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debug("header word %d = %08x\n", 229, rbf_data[229]); |
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debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress); |
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/*
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* from the register map description of cdratio in imgcfg_ctrl_02: |
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* Normal Configuration : 32bit Passive Parallel |
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* Partial Reconfiguration : 16bit Passive Parallel |
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*/ |
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/*
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* cd ratio is dependent on cfg width and whether the bitstream |
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* is encrypted and/or compressed. |
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* |
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* | width | encr. | compr. | cd ratio | |
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* | 16 | 0 | 0 | 1 | |
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* | 16 | 0 | 1 | 4 | |
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* | 16 | 1 | 0 | 2 | |
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* | 16 | 1 | 1 | 4 | |
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* | 32 | 0 | 0 | 1 | |
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* | 32 | 0 | 1 | 8 | |
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* | 32 | 1 | 0 | 4 | |
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* | 32 | 1 | 1 | 8 | |
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*/ |
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if (!compress && !encrypt) { |
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cd_ratio = CDRATIO_x1; |
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} else { |
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if (compress) |
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cd_ratio = CDRATIO_x4; |
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else |
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cd_ratio = CDRATIO_x2; |
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/* if 32 bit, double the cd ratio (so register
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field setting is incremented) */ |
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if (cfg_width == CFGWDTH_32) |
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cd_ratio += 1; |
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} |
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fpgamgr_set_cfgwdth(cfg_width); |
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fpgamgr_set_cd_ratio(cd_ratio); |
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return 0; |
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} |
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static int fpgamgr_reset(void) |
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{ |
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unsigned long reg; |
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/* S2F_NCONFIG = 0 */ |
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clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
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/* Wait for f2s_nstatus == 0 */ |
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if (wait_for_f2s_nstatus_pin(0)) |
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return -ETIME; |
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/* S2F_NCONFIG = 1 */ |
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setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
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ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
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/* Wait for f2s_nstatus == 1 */ |
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if (wait_for_f2s_nstatus_pin(1)) |
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return -ETIME; |
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/* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */ |
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reg = readl(&fpga_manager_base->imgcfg_stat); |
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if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0) |
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return -EPERM; |
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if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0) |
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return -EPERM; |
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return 0; |
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} |
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/* Start the FPGA programming by initialize the FPGA Manager */ |
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int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size) |
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{ |
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int ret; |
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/* Step 1 */ |
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if (fpgamgr_verify_msel()) |
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return -EPERM; |
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/* Step 2 */ |
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if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size)) |
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return -EPERM; |
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/*
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* Step 3: |
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* Make sure no other external devices are trying to interfere with |
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* programming: |
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*/ |
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if (wait_for_nconfig_pin_and_nstatus_pin()) |
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return -ETIME; |
||||
|
||||
/*
|
||||
* Step 4: |
||||
* Deassert the signal drives from HPS |
||||
* |
||||
* S2F_NCE = 1 |
||||
* S2F_PR_REQUEST = 0 |
||||
* EN_CFG_CTRL = 0 |
||||
* EN_CFG_DATA = 0 |
||||
* S2F_NCONFIG = 1 |
||||
* S2F_NSTATUS_OE = 0 |
||||
* S2F_CONDONE_OE = 0 |
||||
*/ |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
||||
|
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK); |
||||
|
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
||||
|
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK); |
||||
|
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK | |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK); |
||||
|
||||
/*
|
||||
* Step 5: |
||||
* Enable overrides |
||||
* S2F_NENABLE_CONFIG = 0 |
||||
* S2F_NENABLE_NCONFIG = 0 |
||||
*/ |
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); |
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); |
||||
|
||||
/*
|
||||
* Disable driving signals that HPS doesn't need to drive. |
||||
* S2F_NENABLE_NSTATUS = 1 |
||||
* S2F_NENABLE_CONDONE = 1 |
||||
*/ |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK | |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK); |
||||
|
||||
/*
|
||||
* Step 6: |
||||
* Drive chip select S2F_NCE = 0 |
||||
*/ |
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
||||
|
||||
/* Step 7 */ |
||||
if (wait_for_nconfig_pin_and_nstatus_pin()) |
||||
return -ETIME; |
||||
|
||||
/* Step 8 */ |
||||
ret = fpgamgr_reset(); |
||||
|
||||
if (ret) |
||||
return ret; |
||||
|
||||
/*
|
||||
* Step 9: |
||||
* EN_CFG_CTRL and EN_CFG_DATA = 1 |
||||
*/ |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering config done */ |
||||
static int fpgamgr_program_poll_cd(void) |
||||
{ |
||||
unsigned long reg, i; |
||||
|
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
reg = readl(&fpga_manager_base->imgcfg_stat); |
||||
if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) |
||||
return 0; |
||||
|
||||
if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) { |
||||
printf("nstatus == 0 while waiting for condone\n"); |
||||
return -EPERM; |
||||
} |
||||
} |
||||
|
||||
if (i == FPGA_TIMEOUT_CNT) |
||||
return -ETIME; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
static int fpgamgr_program_poll_usermode(void) |
||||
{ |
||||
unsigned long reg; |
||||
int ret = 0; |
||||
|
||||
if (fpgamgr_dclkcnt_set(0xf)) |
||||
return -ETIME; |
||||
|
||||
ret = wait_for_user_mode(); |
||||
if (ret < 0) { |
||||
printf("%s: Failed to enter user mode with ", __func__); |
||||
printf("error code %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
/*
|
||||
* Step 14: |
||||
* Stop DATA path and Dclk |
||||
* EN_CFG_CTRL and EN_CFG_DATA = 0 |
||||
*/ |
||||
clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK | |
||||
ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK); |
||||
|
||||
/*
|
||||
* Step 15: |
||||
* Disable overrides |
||||
* S2F_NENABLE_CONFIG = 1 |
||||
* S2F_NENABLE_NCONFIG = 1 |
||||
*/ |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK); |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, |
||||
ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK); |
||||
|
||||
/* Disable chip select S2F_NCE = 1 */ |
||||
setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, |
||||
ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK); |
||||
|
||||
/*
|
||||
* Step 16: |
||||
* Final check |
||||
*/ |
||||
reg = readl(&fpga_manager_base->imgcfg_stat); |
||||
if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != |
||||
ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) || |
||||
((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != |
||||
ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) || |
||||
((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) != |
||||
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK)) |
||||
return -EPERM; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int fpgamgr_program_finish(void) |
||||
{ |
||||
/* Ensure the FPGA entering config done */ |
||||
int status = fpgamgr_program_poll_cd(); |
||||
|
||||
if (status) { |
||||
printf("FPGA: Poll CD failed with error code %d\n", status); |
||||
return -EPERM; |
||||
} |
||||
WATCHDOG_RESET(); |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
status = fpgamgr_program_poll_usermode(); |
||||
if (status) { |
||||
printf("FPGA: Poll usermode failed with error code %d\n", |
||||
status); |
||||
return -EPERM; |
||||
} |
||||
|
||||
printf("Full Configuration Succeeded.\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
||||
* Return 0 for sucess, non-zero for error. |
||||
*/ |
||||
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
||||
{ |
||||
unsigned long status; |
||||
|
||||
/* disable all signals from hps peripheral controller to fpga */ |
||||
writel(0, &system_manager_base->fpgaintf_en_global); |
||||
|
||||
/* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
||||
socfpga_bridges_reset(); |
||||
|
||||
/* Initialize the FPGA Manager */ |
||||
status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Write the RBF data to FPGA Manager */ |
||||
fpgamgr_program_write(rbf_data, rbf_size); |
||||
|
||||
return fpgamgr_program_finish(); |
||||
} |
||||
@ -0,0 +1,252 @@ |
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
* All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: BSD-3-Clause |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <linux/errno.h> |
||||
#include <asm/arch/fpga_manager.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/arch/system_manager.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define FPGA_TIMEOUT_CNT 0x1000000 |
||||
|
||||
static struct socfpga_fpga_manager *fpgamgr_regs = |
||||
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; |
||||
static struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
/* Set CD ratio */ |
||||
static void fpgamgr_set_cd_ratio(unsigned long ratio) |
||||
{ |
||||
clrsetbits_le32(&fpgamgr_regs->ctrl, |
||||
0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB, |
||||
(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB); |
||||
} |
||||
|
||||
/* Start the FPGA programming by initialize the FPGA Manager */ |
||||
static int fpgamgr_program_init(void) |
||||
{ |
||||
unsigned long msel, i; |
||||
|
||||
/* Get the MSEL value */ |
||||
msel = readl(&fpgamgr_regs->stat); |
||||
msel &= FPGAMGRREGS_STAT_MSEL_MASK; |
||||
msel >>= FPGAMGRREGS_STAT_MSEL_LSB; |
||||
|
||||
/*
|
||||
* Set the cfg width |
||||
* If MSEL[3] = 1, cfg width = 32 bit |
||||
*/ |
||||
if (msel & 0x8) { |
||||
setbits_le32(&fpgamgr_regs->ctrl, |
||||
FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
||||
|
||||
/* To determine the CD ratio */ |
||||
/* MSEL[1:0] = 0, CD Ratio = 1 */ |
||||
if ((msel & 0x3) == 0x0) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x1); |
||||
/* MSEL[1:0] = 1, CD Ratio = 4 */ |
||||
else if ((msel & 0x3) == 0x1) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x4); |
||||
/* MSEL[1:0] = 2, CD Ratio = 8 */ |
||||
else if ((msel & 0x3) == 0x2) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x8); |
||||
|
||||
} else { /* MSEL[3] = 0 */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, |
||||
FPGAMGRREGS_CTRL_CFGWDTH_MASK); |
||||
|
||||
/* To determine the CD ratio */ |
||||
/* MSEL[1:0] = 0, CD Ratio = 1 */ |
||||
if ((msel & 0x3) == 0x0) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x1); |
||||
/* MSEL[1:0] = 1, CD Ratio = 2 */ |
||||
else if ((msel & 0x3) == 0x1) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x2); |
||||
/* MSEL[1:0] = 2, CD Ratio = 4 */ |
||||
else if ((msel & 0x3) == 0x2) |
||||
fpgamgr_set_cd_ratio(CDRATIO_x4); |
||||
} |
||||
|
||||
/* To enable FPGA Manager configuration */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); |
||||
|
||||
/* To enable FPGA Manager drive over configuration line */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
||||
|
||||
/* Put FPGA into reset phase */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
||||
|
||||
/* (1) wait until FPGA enter reset phase */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in reset state, return error */ |
||||
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) { |
||||
puts("FPGA: Could not reset\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/* Release FPGA from reset phase */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); |
||||
|
||||
/* (2) wait until FPGA enter configuration phase */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in configuration state, return error */ |
||||
if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) { |
||||
puts("FPGA: Could not configure\n"); |
||||
return -2; |
||||
} |
||||
|
||||
/* Clear all interrupts in CB Monitor */ |
||||
writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi); |
||||
|
||||
/* Enable AXI configuration */ |
||||
setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering config done */ |
||||
static int fpgamgr_program_poll_cd(void) |
||||
{ |
||||
const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK | |
||||
FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK; |
||||
unsigned long reg, i; |
||||
|
||||
/* (3) wait until full config done */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
reg = readl(&fpgamgr_regs->gpio_ext_porta); |
||||
|
||||
/* Config error */ |
||||
if (!(reg & mask)) { |
||||
printf("FPGA: Configuration error.\n"); |
||||
return -3; |
||||
} |
||||
|
||||
/* Config done without error */ |
||||
if (reg & mask) |
||||
break; |
||||
} |
||||
|
||||
/* Timeout happened, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) { |
||||
printf("FPGA: Timeout waiting for program.\n"); |
||||
return -4; |
||||
} |
||||
|
||||
/* Disable AXI configuration */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering init phase */ |
||||
static int fpgamgr_program_poll_initphase(void) |
||||
{ |
||||
unsigned long i; |
||||
|
||||
/* Additional clocks for the CB to enter initialization phase */ |
||||
if (fpgamgr_dclkcnt_set(0x4)) |
||||
return -5; |
||||
|
||||
/* (4) wait until FPGA enter init phase or user mode */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE) |
||||
break; |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
||||
break; |
||||
} |
||||
|
||||
/* If not in configuration state, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) |
||||
return -6; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
static int fpgamgr_program_poll_usermode(void) |
||||
{ |
||||
unsigned long i; |
||||
|
||||
/* Additional clocks for the CB to exit initialization phase */ |
||||
if (fpgamgr_dclkcnt_set(0x5000)) |
||||
return -7; |
||||
|
||||
/* (5) wait until FPGA enter user mode */ |
||||
for (i = 0; i < FPGA_TIMEOUT_CNT; i++) { |
||||
if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE) |
||||
break; |
||||
} |
||||
/* If not in configuration state, return error */ |
||||
if (i == FPGA_TIMEOUT_CNT) |
||||
return -8; |
||||
|
||||
/* To release FPGA Manager drive over configuration line */ |
||||
clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* FPGA Manager to program the FPGA. This is the interface used by FPGA driver. |
||||
* Return 0 for sucess, non-zero for error. |
||||
*/ |
||||
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) |
||||
{ |
||||
unsigned long status; |
||||
|
||||
if ((uint32_t)rbf_data & 0x3) { |
||||
puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/* Prior programming the FPGA, all bridges need to be shut off */ |
||||
|
||||
/* Disable all signals from hps peripheral controller to fpga */ |
||||
writel(0, &sysmgr_regs->fpgaintfgrp_module); |
||||
|
||||
/* Disable all signals from FPGA to HPS SDRAM */ |
||||
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |
||||
writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); |
||||
|
||||
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ |
||||
socfpga_bridges_reset(1); |
||||
|
||||
/* Unmap the bridges from NIC-301 */ |
||||
writel(0x1, SOCFPGA_L3REGS_ADDRESS); |
||||
|
||||
/* Initialize the FPGA Manager */ |
||||
status = fpgamgr_program_init(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Write the RBF data to FPGA Manager */ |
||||
fpgamgr_program_write(rbf_data, rbf_size); |
||||
|
||||
/* Ensure the FPGA entering config done */ |
||||
status = fpgamgr_program_poll_cd(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Ensure the FPGA entering init phase */ |
||||
status = fpgamgr_program_poll_initphase(); |
||||
if (status) |
||||
return status; |
||||
|
||||
/* Ensure the FPGA entering user mode */ |
||||
return fpgamgr_program_poll_usermode(); |
||||
} |
||||
Loading…
Reference in new issue