From 44cdb5b6a10a7eb2e240866cb842e44ff9999960 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Mon, 27 Nov 2017 15:40:17 +0800 Subject: [PATCH 01/12] armv8: ls1088ardb: support force SDHC mode by hwconfig The BRDCFG5[SPISDHC] register field of Qixis device is used to control SPI and SDHC signal routing. 10 = Force SDHC Mode - SPI_CS[0] is routed to CPLD for SDHC_VS use. - SPI_CS[1] is unused. - SPI_CS[2:3] are routed to the TDMRiser slot. 11 = Force eMMC Mode - SPI_CS[0:3] are routed to the eMMC card. 0X = Auto Mode - If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode described above. - Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC mode described above. In default the hardware uses auto mode, but sometimes we need to use force SDHC mode to support SD card hotplug, or SD sleep waking up in kernel. This patch is to support force SDHC mode by hwconfig. Signed-off-by: Yangbo Lu Reviewed-by: York Sun --- board/freescale/ls1088a/ls1088a.c | 18 ++++++++++++++++++ board/freescale/ls1088a/ls1088a_qixis.h | 6 ++++++ include/configs/ls1088ardb.h | 2 ++ 3 files changed, 26 insertions(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 9daa007..cb58957 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -296,6 +297,23 @@ void board_retimer_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); } +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_TARGET_LS1088ARDB + u8 brdcfg5; + + if (hwconfig("esdhc-force-sd")) { + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; + brdcfg5 |= BRDCFG5_FORCE_SD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif + return 0; +} +#endif + int board_init(void) { init_final_memctl_regs(); diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h index 4790461..6cad396 100644 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ b/board/freescale/ls1088a/ls1088a_qixis.h @@ -36,4 +36,10 @@ #define BRDCFG9_SFPTX_MASK 0x10 #define BRDCFG9_SFPTX_SHIFT 4 +/* Definitions of QIXIS Registers for LS1088ARDB */ + +/* BRDCFG5 */ +#define BRDCFG5_SPISDHC_MASK 0x0C +#define BRDCFG5_FORCE_SD 0x08 + #endif diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 1da8153..1438bec 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -11,6 +11,8 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_MISC_INIT_R + #if defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ From a81357a264a8fb57a314f5dbcf39a09b7467b94f Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Thu, 30 Nov 2017 16:44:38 +0530 Subject: [PATCH 02/12] arm64: ls1012ardb: Add distro boot support Include common config_distro_defaults.h and config_distro_bootcmd.h for u-boot enviroments to support automatical distro boot which scan boot.scr from external storage devices(e.g. SD and USB) and execute autoboot script. Signed-off-by: Bhaskar Upadhaya Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- configs/ls1012ardb_qspi_defconfig | 1 + include/configs/ls1012a_common.h | 10 ++++++++- include/configs/ls1012ardb.h | 43 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 81702e3..39d7a54 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -50,3 +50,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 57cae94..db920bc 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -87,6 +87,14 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#include +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) +#include +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ @@ -98,6 +106,7 @@ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ +#undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ "$kernel_start $kernel_size && "\ "bootm $kernel_load" @@ -105,7 +114,6 @@ /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 89aa952..a14021f 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -58,6 +58,49 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012ardb_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "installer=load mmc 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #include From 4c616a13de3e1cd526009e39a56674ba60e9c769 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Thu, 30 Nov 2017 16:44:45 +0530 Subject: [PATCH 03/12] arm64: ls1012afrdm: Add distro boot support Include common config_distro_defaults.h and config_distro_bootcmd.h for u-boot enviroments to support automatical distro boot which scan boot.scr from external storage devices(e.g. SD and USB) and execute autoboot script. Signed-off-by: Bhaskar Upadhaya Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- configs/ls1012afrdm_qspi_defconfig | 1 + include/configs/ls1012afrdm.h | 57 ++++++++++++++++++++++++++++++++------ 2 files changed, 49 insertions(+), 9 deletions(-) diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index fe95f04..42acff0 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -46,3 +46,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 5b4bf28..297c057 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -20,16 +20,55 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) +#endif + #undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_load=0x96000000\0" \ - "kernel_size=0x2800000\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "scriptaddr=0x80000000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0x96000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012afrdm_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "installer=load usb 0:2 $load_addr " \ + "/flex_installer_arm64.itb; " \ + "bootm $load_addr#$board\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size && bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd" #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST From a8f33034f2ed029dd04aae4cfdf11bf1f13a03a2 Mon Sep 17 00:00:00 2001 From: Wenbin song Date: Mon, 4 Dec 2017 12:18:28 +0800 Subject: [PATCH 04/12] armv8: ls1043a/ls2080a: check SoC by device ID Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++---- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++-- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 ++++----- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++-- drivers/net/fsl-mc/dpio/qbman_private.h | 4 ++-- drivers/usb/common/fsl-errata.c | 7 +++++-- 6 files changed, 19 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d082629..00d2564 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,8 +538,8 @@ int arch_early_init_r(void) * erratum A009635 is valid only for LS2080A SoC and * its personalitiesi */ - svr_dev_id = get_svr() >> 16; - if (svr_dev_id == SVR_DEV_LS2080A) + svr_dev_id = get_svr(); + if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) erratum_a009635(); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) @@ -604,8 +604,8 @@ int timer_init(void) * For LS2080A SoC and its personalities, timer controller * offset is different */ - svr_dev_id = get_svr() >> 16; - if (svr_dev_id == SVR_DEV_LS2080A) + svr_dev_id = get_svr(); + if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index cae59da..d1a7d0d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob) val = gur_in32(&gur->svr); - if (SVR_SOC_VER(val) != SVR_LS1043A) { + if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) { align_64k = 1; } else if (SVR_REV(val) != REV1_0) { val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT); @@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob) rev = gur_in32(&gur->svr); - if (SVR_SOC_VER(rev) != SVR_LS1043A) + if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A))) return; rev = SVR_REV(rev); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index fa93096..c089cee 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -37,9 +37,8 @@ ENTRY(get_gic_offset) ldr x2, =DCFG_CCSR_SVR ldr w2, [x2] rev w2, w2 - mov w3, w2 - ands w3, w3, #SVR_WO_E << 8 - mov w4, #SVR_LS1043A << 8 + lsr w3, w2, #16 + ldr w4, =SVR_DEV(SVR_LS1043A) cmp w3, w4 b.ne 1f ands w2, w2, #0xff @@ -92,7 +91,7 @@ ENTRY(lowlevel_init) */ bl get_svr lsr w0, w0, #16 - ldr w1, =SVR_DEV_LS2080A + ldr w1, =SVR_DEV(SVR_LS2080A) cmp w0, w1 b.eq 1f @@ -224,7 +223,7 @@ ENTRY(lowlevel_init) */ bl get_svr lsr w0, w0, #16 - ldr w1, =SVR_DEV_LS2080A + ldr w1, =SVR_DEV(SVR_LS2080A) cmp w0, w1 b.eq 1f diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 247f09e..09f64e7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -76,8 +76,6 @@ struct cpu_type { #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 -#define SVR_DEV_LS2080A 0x8701 - #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) @@ -85,6 +83,8 @@ struct cpu_type { #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) +#define SVR_DEV(svr) ((svr) >> 8) +#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe diff --git a/drivers/net/fsl-mc/dpio/qbman_private.h b/drivers/net/fsl-mc/dpio/qbman_private.h index 73bbae3..873323b 100644 --- a/drivers/net/fsl-mc/dpio/qbman_private.h +++ b/drivers/net/fsl-mc/dpio/qbman_private.h @@ -175,8 +175,8 @@ void qbman_version(u32 *major, u32 *minor) * LS2080A SoC and its personalities has qbman cotroller version 4.0 * New SoCs like LS2088A, LS1088A has qbman conroller version 4.1 */ - svr_dev_id = get_svr() >> 16; - if (svr_dev_id == SVR_DEV_LS2080A) { + svr_dev_id = get_svr(); + if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) { *major = 4; *minor = 0; } else { diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 823beb3..6e2a464 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -198,6 +198,11 @@ bool has_erratum_a010151(void) u32 svr = get_svr(); u32 soc = SVR_SOC_VER(svr); +#ifdef CONFIG_ARM64 + if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A))) + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); +#endif + switch (soc) { #ifdef CONFIG_ARM64 case SVR_LS2080A: @@ -209,8 +214,6 @@ bool has_erratum_a010151(void) case SVR_LS1046A: case SVR_LS1012A: return IS_SVR_REV(svr, 1, 0); - case SVR_LS1043A: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); #endif #ifdef CONFIG_ARCH_LS1021A case SOC_VER_LS1020: From 20c7305101219aba62c9f1f84920a99d4026cad5 Mon Sep 17 00:00:00 2001 From: Wenbin song Date: Mon, 4 Dec 2017 12:18:29 +0800 Subject: [PATCH 05/12] armv8: layerscape: Discard the needless cpu nodes Using "cpu_pos_mask()" function to detect the real online cpus, and discard the needless cpu nodes on kernel dts. Signed-off-by: Wenbin Song Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index d1a7d0d..39ffe1a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -42,6 +42,33 @@ void ft_fixup_cpu(void *blob) int addr_cells; u64 val, core_id; size_t *boot_code_size = &(__secondary_boot_code_size); + u32 mask = cpu_pos_mask(); + int off_prev = -1; + + off = fdt_path_offset(blob, "/cpus"); + if (off < 0) { + puts("couldn't find /cpus node\n"); + return; + } + + fdt_support_default_count_cells(blob, off, &addr_cells, NULL); + + off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type", + "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); + if (reg) { + core_id = fdt_read_number(reg, addr_cells); + if (!test_bit(id_to_core(core_id), &mask)) { + fdt_del_node(blob, off); + off = off_prev; + } + } + off_prev = off; + off = fdt_node_offset_by_prop_value(blob, off_prev, + "device_type", "cpu", 4); + } + #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) int node; From 70a131eb5ac1f4cceb5500ad3224473020497cc9 Mon Sep 17 00:00:00 2001 From: Yogesh Gaur Date: Thu, 7 Dec 2017 11:10:14 +0530 Subject: [PATCH 06/12] board/ls2080a, ls1088a: Add check for mc-dpl applied in fdt Function fdt_fixup_board_enet() performs fdt fixup. Only return fdt_status_okay() when both MC is applied and DPL is deployed, else return fdt_status_fail(). This check is added to LS1088A/LS2080A/LS2088A boards. Signed-off-by: Yogesh Gaur Reviewed-by: York Sun --- board/freescale/ls1088a/ls1088a.c | 2 +- board/freescale/ls2080a/ls2080a.c | 2 +- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/ls2080ardb/ls2080ardb.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index cb58957..96f183e 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -378,7 +378,7 @@ void fdt_fixup_board_enet(void *fdt) return; } - if (get_mc_boot_status() == 0) + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 41417e9..c60a090 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -90,7 +90,7 @@ void fdt_fixup_board_enet(void *fdt) return; } - if (get_mc_boot_status() == 0) + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 1842d14..28c9538 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -295,7 +295,7 @@ void fdt_fixup_board_enet(void *fdt) return; } - if (get_mc_boot_status() == 0) + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 827bfad..ee0f3a2 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -331,7 +331,7 @@ void fdt_fixup_board_enet(void *fdt) return; } - if (get_mc_boot_status() == 0) + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) fdt_status_okay(fdt, offset); else fdt_status_fail(fdt, offset); From 481fb01f41feec75366cd0790ff672638384b60a Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 8 Dec 2017 15:35:35 +0800 Subject: [PATCH 07/12] armv8: ls1012ardb: clean up definitions for I2C IO expanders This patch is to clean up definitions for I2C IO expanders. The value 0x10 of __SW_BOOT_EMU is wrong. It should be 0x2. Fixed it in this patch. Signed-off-by: Yangbo Lu Reviewed-by: York Sun --- board/freescale/ls1012ardb/ls1012ardb.c | 14 +++++++------- include/configs/ls1012ardb.h | 18 ++++++++++-------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index c6c1c71..2f1d637 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -35,25 +35,25 @@ int checkboard(void) /* Initialize i2c early for Serial flash bank information */ i2c_set_bus_num(0); - if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { + if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1) < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } puts("Version"); - if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) + if ((in1 & SW_REV_MASK) == SW_REV_A) puts(": RevA"); - else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) + else if ((in1 & SW_REV_MASK) == SW_REV_B) puts(": RevB"); else puts(": unknown"); printf(", boot from QSPI"); - if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) + if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) puts(": emu\n"); - else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1) puts(": bank1\n"); - else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2) puts(": bank2\n"); else puts("unknown\n"); @@ -152,7 +152,7 @@ int esdhc_status_fixup(void *blob, const char *compat) * 10 - eMMC Memory * 11 - SPI */ - if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) { + if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index a14021f..d0ceae2 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -24,14 +24,16 @@ * I2C IO expander */ -#define I2C_MUX_IO1_ADDR 0x24 -#define __SW_BOOT_MASK 0xFC -#define __SW_BOOT_EMU 0x10 -#define __SW_BOOT_BANK1 0x00 -#define __SW_BOOT_BANK2 0x01 -#define __SW_REV_MASK 0x07 -#define __SW_REV_A 0xF8 -#define __SW_REV_B 0xF0 +#define I2C_MUX_IO_ADDR 0x24 +#define I2C_MUX_IO_0 0 +#define I2C_MUX_IO_1 1 +#define SW_BOOT_MASK 0x03 +#define SW_BOOT_EMU 0x02 +#define SW_BOOT_BANK1 0x00 +#define SW_BOOT_BANK2 0x01 +#define SW_REV_MASK 0xF8 +#define SW_REV_A 0xF8 +#define SW_REV_B 0xF0 /* MMC */ #ifdef CONFIG_MMC From 4a47bf8a2ba61e21b022b81e2234fdb47570ad22 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 8 Dec 2017 15:35:36 +0800 Subject: [PATCH 08/12] armv8: ls1012ardb: add more board version information Add LS1012ARDB RevC/RevC1/RevC2/RevD/RevE information and detect it when u-boot starts up. Signed-off-by: Yangbo Lu Reviewed-by: York Sun --- board/freescale/ls1012ardb/ls1012ardb.c | 26 +++++++++++++++++++++++--- include/configs/ls1012ardb.h | 5 +++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 2f1d637..421b0a7 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -41,12 +41,32 @@ int checkboard(void) } puts("Version"); - if ((in1 & SW_REV_MASK) == SW_REV_A) + switch (in1 & SW_REV_MASK) { + case SW_REV_A: puts(": RevA"); - else if ((in1 & SW_REV_MASK) == SW_REV_B) + break; + case SW_REV_B: puts(": RevB"); - else + break; + case SW_REV_C: + puts(": RevC"); + break; + case SW_REV_C1: + puts(": RevC1"); + break; + case SW_REV_C2: + puts(": RevC2"); + break; + case SW_REV_D: + puts(": RevD"); + break; + case SW_REV_E: + puts(": RevE"); + break; + default: puts(": unknown"); + break; + } printf(", boot from QSPI"); if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index d0ceae2..ab139b0 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -34,6 +34,11 @@ #define SW_REV_MASK 0xF8 #define SW_REV_A 0xF8 #define SW_REV_B 0xF0 +#define SW_REV_C 0xE8 +#define SW_REV_C1 0xE0 +#define SW_REV_C2 0xD8 +#define SW_REV_D 0xD0 +#define SW_REV_E 0xC8 /* MMC */ #ifdef CONFIG_MMC From 6aaa539f47fc9305de5af64c02b076136852cc3b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 8 Dec 2017 15:35:37 +0800 Subject: [PATCH 09/12] armv8: ls1012ardb: support hwconfig for eSDHC1 enabling I2C reading for DIP switch setting is not reliable for LS1012ARDB RevD and later versions. This patch is to add hwconfig support to enable/disable eSDHC1 manually for these boards. Also drop 'status' fix-up for eSDHC0 and leave it as it is. It shouldn't always be fixed up with 'okay'. Signed-off-by: Yangbo Lu Reviewed-by: York Sun --- board/freescale/ls1012ardb/ls1012ardb.c | 55 +++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 421b0a7..286f9d8 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -152,34 +152,49 @@ int board_init(void) int esdhc_status_fixup(void *blob, const char *compat) { - char esdhc0_path[] = "/soc/esdhc@1560000"; char esdhc1_path[] = "/soc/esdhc@1580000"; - u8 io = 0; + bool sdhc2_en = false; u8 mux_sdhc2; - - do_fixup_by_path(blob, esdhc0_path, "status", "okay", - sizeof("okay"), 1); + u8 io = 0; i2c_set_bus_num(0); - /* - * The I2C IO-expander for mux select is used to control the muxing - * of various onboard interfaces. - * - * IO1[3:2] indicates SDHC2 interface demultiplexer select lines. - * 00 - SDIO wifi - * 01 - GPIO (to Arduino) - * 10 - eMMC Memory - * 11 - SPI - */ - if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) { + /* IO1[7:3] is the field of board revision info. */ + if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1) < 0) { printf("Error reading i2c boot information!\n"); - return 0; /* Don't want to hang() on this error */ + return 0; + } + + /* hwconfig method is used for RevD and later versions. */ + if ((io & SW_REV_MASK) <= SW_REV_D) { +#ifdef CONFIG_HWCONFIG + if (hwconfig("esdhc1")) + sdhc2_en = true; +#endif + } else { + /* + * The I2C IO-expander for mux select is used to control + * the muxing of various onboard interfaces. + * + * IO0[3:2] indicates SDHC2 interface demultiplexer + * select lines. + * 00 - SDIO wifi + * 01 - GPIO (to Arduino) + * 10 - eMMC Memory + * 11 - SPI + */ + if (i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; + } + + mux_sdhc2 = (io & 0x0c) >> 2; + /* Enable SDHC2 only when use SDIO wifi and eMMC */ + if (mux_sdhc2 == 2 || mux_sdhc2 == 0) + sdhc2_en = true; } - mux_sdhc2 = (io & 0x0c) >> 2; - /* Enable SDHC2 only when use SDIO wifi and eMMC */ - if (mux_sdhc2 == 2 || mux_sdhc2 == 0) + if (sdhc2_en) do_fixup_by_path(blob, esdhc1_path, "status", "okay", sizeof("okay"), 1); else From 63143a5f92f45457f75ba94f886a2bea74ddfff3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 18 Dec 2017 08:24:55 -0800 Subject: [PATCH 10/12] armv8: ls2080a: Increase load image len for NAND boot Again the image size increases and the length needs to be adjusted. Signed-off-by: York Sun --- include/configs/ls2080a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index f897869..576785e 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -237,7 +237,7 @@ unsigned long long get_qixis_addr(void); #endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (640 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ From f440aba172c3b1107176d59f9cd0d7b209afc0a8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Dec 2017 14:37:40 -0800 Subject: [PATCH 11/12] armv8: ls2085a: Update README file for NAND boot Update README file to note LS2088A and LS1088A don't support booting from NAND flash. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 025a1b7..6c98d99 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -154,8 +154,8 @@ Booting from NAND ------------------- Booting from NAND requires two images, RCW and u-boot-with-spl.bin. The difference between NAND boot RCW image and NOR boot image is the PBI -command sequence. Below is one example for PBI commands for QDS which uses -NAND device with 2KB/page, block size 128KB. +command sequence. Below is one example for PBI commands for LS2085AQDS which +uses NAND device with 2KB/page, block size 128KB. 1) CCSR 4-byte write to 0x00e00404, data=0x00000000 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 @@ -188,7 +188,7 @@ nand write 200000 With these two images in NAND device, the board can boot from NAND. -Another example for RDB boards, +Another example for LS2085ARDB boards, 1) CCSR 4-byte write to 0x00e00404, data=0x00000000 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 @@ -201,6 +201,8 @@ nand write 80000 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image to match board NAND device with 4KB/page, block size 512KB. +Note, LS2088A and LS1088A don't support booting from NAND. + Booting from SD/eMMC ------------------- Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin. From 1b7910a37ccc889e1b58a5f6e095a39728564bb8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 11 Dec 2017 08:39:05 -0800 Subject: [PATCH 12/12] armv8: ls1046aqds: Adjust IFC timing for NOR flash Increase setup, assertion and hold time related to chip-select signal. Additional delay is needed for the signal to propogate through FPGA. This adjustment slightly increase the read and write cycle but has no impact on burst read or write. Signed-off-by: York Sun --- include/configs/ls1046aqds.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index f510f24..c3b0f4d 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -176,12 +176,13 @@ unsigned long get_board_ddr_clk(void); CSOR_NOR_TRHZ_80) #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ + FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0