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@ -166,7 +166,7 @@ |
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#undef CONFIG_SYS_RAMBOOT |
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#endif |
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
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/*
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@ -223,15 +223,17 @@ |
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*/ |
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#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define NAND_MAX_CHIPS 1 |
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#define CONFIG_MTD_NAND_VERIFY_WRITE |
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#define NAND_MAX_CHIPS 1 |
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#define CONFIG_MTD_NAND_VERIFY_WRITE 1 |
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#define CONFIG_CMD_NAND 1 |
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#define CONFIG_NAND_FSL_ELBC 1 |
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#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ |
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#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ |
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */ |
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#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
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#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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