Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>master
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/sys_proto.h> |
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static char *get_reset_cause(char *); |
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u32 get_cpu_rev(void) |
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{ |
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/* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ |
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return (MXC_CPU_MX7ULP << 12) | (1 << 4); |
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} |
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#ifdef CONFIG_REVISION_TAG |
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u32 __weak get_board_rev(void) |
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{ |
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return get_cpu_rev(); |
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} |
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#endif |
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enum bt_mode get_boot_mode(void) |
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{ |
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u32 bt0_cfg = 0; |
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bt0_cfg = readl(CMC0_RBASE + 0x40); |
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bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); |
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if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { |
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/* No low power boot */ |
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if (bt0_cfg & BT0CFG_DUALBOOT_MASK) |
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return DUAL_BOOT; |
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else |
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return SINGLE_BOOT; |
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} |
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return LOW_POWER_BOOT; |
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} |
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int arch_cpu_init(void) |
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{ |
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return 0; |
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} |
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#ifdef CONFIG_BOARD_POSTCLK_INIT |
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int board_postclk_init(void) |
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{ |
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return 0; |
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} |
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#endif |
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ |
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ |
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */ |
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */ |
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static void disable_wdog(u32 wdog_base) |
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{ |
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writel(UNLOCK_WORD0, (wdog_base + 0x04)); |
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writel(UNLOCK_WORD1, (wdog_base + 0x04)); |
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writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ |
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writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ |
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writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ |
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writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ |
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writel(REFRESH_WORD1, (wdog_base + 0x04)); |
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} |
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void init_wdog(void) |
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{ |
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/*
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* ROM will configure WDOG1, disable it or enable it |
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* depending on FUSE. The update bit is set for reconfigurable. |
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* We have to use unlock sequence to reconfigure it. |
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* WDOG2 is not touched by ROM, so it will have default value |
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* which is enabled. We can directly configure it. |
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* To simplify the codes, we still use same reconfigure |
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* process as WDOG1. Because the update bit is not set for |
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* WDOG2, the unlock sequence won't take effect really. |
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* It actually directly configure the wdog. |
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* In this function, we will disable both WDOG1 and WDOG2, |
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* and set update bit for both. So that kernel can reconfigure them. |
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*/ |
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disable_wdog(WDG1_RBASE); |
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disable_wdog(WDG2_RBASE); |
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} |
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void s_init(void) |
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{ |
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/* Disable wdog */ |
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init_wdog(); |
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/* clock configuration. */ |
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clock_init(); |
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return; |
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} |
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#ifndef CONFIG_ULP_WATCHDOG |
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void reset_cpu(ulong addr) |
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{ |
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setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET); |
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while (1) |
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; |
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} |
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#endif |
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#if defined(CONFIG_DISPLAY_CPUINFO) |
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const char *get_imx_type(u32 imxtype) |
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{ |
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return "7ULP"; |
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} |
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int print_cpuinfo(void) |
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{ |
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u32 cpurev; |
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char cause[18]; |
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cpurev = get_cpu_rev(); |
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", |
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get_imx_type((cpurev & 0xFF000) >> 12), |
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(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, |
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mxc_get_clock(MXC_ARM_CLK) / 1000000); |
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printf("Reset cause: %s\n", get_reset_cause(cause)); |
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printf("Boot mode: "); |
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switch (get_boot_mode()) { |
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case LOW_POWER_BOOT: |
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printf("Low power boot\n"); |
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break; |
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case DUAL_BOOT: |
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printf("Dual boot\n"); |
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break; |
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case SINGLE_BOOT: |
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default: |
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printf("Single boot\n"); |
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break; |
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} |
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return 0; |
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} |
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#endif |
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#define CMC_SRS_TAMPER (1 << 31) |
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#define CMC_SRS_SECURITY (1 << 30) |
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#define CMC_SRS_TZWDG (1 << 29) |
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#define CMC_SRS_JTAG_RST (1 << 28) |
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#define CMC_SRS_CORE1 (1 << 16) |
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#define CMC_SRS_LOCKUP (1 << 15) |
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#define CMC_SRS_SW (1 << 14) |
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#define CMC_SRS_WDG (1 << 13) |
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#define CMC_SRS_PIN_RESET (1 << 8) |
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#define CMC_SRS_WARM (1 << 4) |
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#define CMC_SRS_HVD (1 << 3) |
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#define CMC_SRS_LVD (1 << 2) |
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#define CMC_SRS_POR (1 << 1) |
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#define CMC_SRS_WUP (1 << 0) |
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static u32 reset_cause = -1; |
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static char *get_reset_cause(char *ret) |
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{ |
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u32 cause1, cause = 0, srs = 0; |
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u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); |
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u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20); |
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if (!ret) |
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return "null"; |
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srs = readl(reg_srs); |
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cause1 = readl(reg_ssrs); |
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writel(cause1, reg_ssrs); |
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reset_cause = cause1; |
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cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); |
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switch (cause) { |
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case CMC_SRS_POR: |
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sprintf(ret, "%s", "POR"); |
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break; |
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case CMC_SRS_WUP: |
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sprintf(ret, "%s", "WUP"); |
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break; |
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case CMC_SRS_WARM: |
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cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | |
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CMC_SRS_JTAG_RST); |
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switch (cause) { |
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case CMC_SRS_WDG: |
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sprintf(ret, "%s", "WARM-WDG"); |
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break; |
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case CMC_SRS_SW: |
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sprintf(ret, "%s", "WARM-SW"); |
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break; |
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case CMC_SRS_JTAG_RST: |
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sprintf(ret, "%s", "WARM-JTAG"); |
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break; |
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default: |
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sprintf(ret, "%s", "WARM-UNKN"); |
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break; |
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} |
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break; |
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default: |
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sprintf(ret, "%s-%X", "UNKN", cause1); |
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break; |
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} |
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debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1); |
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return ret; |
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} |
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#ifdef CONFIG_ENV_IS_IN_MMC |
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__weak int board_mmc_get_env_dev(int devno) |
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{ |
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return CONFIG_SYS_MMC_ENV_DEV; |
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} |
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int mmc_get_env_dev(void) |
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{ |
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int devno = 0; |
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u32 bt1_cfg = 0; |
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/* If not boot from sd/mmc, use default value */ |
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if (get_boot_mode() == LOW_POWER_BOOT) |
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return CONFIG_SYS_MMC_ENV_DEV; |
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bt1_cfg = readl(CMC1_RBASE + 0x40); |
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devno = (bt1_cfg >> 9) & 0x7; |
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return board_mmc_get_env_dev(devno); |
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} |
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#endif |
@ -0,0 +1,21 @@ |
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SYS_PROTO_MX7ULP_H_ |
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#define _SYS_PROTO_MX7ULP_H_ |
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#include <asm/imx-common/sys_proto.h> |
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#define BT0CFG_LPBOOT_MASK 0x1 |
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#define BT0CFG_DUALBOOT_MASK 0x2 |
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enum bt_mode { |
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LOW_POWER_BOOT, /* LP_BT = 1 */ |
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DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ |
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SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ |
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}; |
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#endif |
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