Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>master
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