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ARM64: zynqmp: Enable CLK and SPL_CLK by default

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Serial driver starts to use clk framework that's why
enable it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
master
Michal Simek 8 years ago
parent 1eefe14f66
commit 1f29738ad1
8 changed files with 2 additions and 14 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      arch/arm/Kconfig
  2. 2
      configs/xilinx_zynqmp_ep_defconfig
  3. 2
      configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
  4. 2
      configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
  5. 2
      configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
  6. 2
      configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
  7. 2
      configs/xilinx_zynqmp_zcu102_defconfig
  8. 2
      configs/xilinx_zynqmp_zcu102_revB_defconfig

2
arch/arm/Kconfig
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@ -669,6 +669,8 @@ config ARCH_ZYNQMP
select OF_CONTROL
select DM_SERIAL
select SUPPORT_SPL
select CLK
select SPL_CLK
config TEGRA
bool "NVIDIA Tegra"

2
configs/xilinx_zynqmp_ep_defconfig
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@ -42,8 +42,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
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@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
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@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_NAND_ARASAN=y

2
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
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@ -29,8 +29,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
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@ -28,8 +28,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zcu102_defconfig
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@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y

2
configs/xilinx_zynqmp_zcu102_revB_defconfig
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@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y

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