Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

i.MX6Q: icore: Add SPL_OF_CONTROL support

Browse Source 
Add OF_CONTROL support for SPL code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
master
Jagan Teki 7 years ago committed by Stefano Babic
parent a1797beed2
commit 1f6e9bd2a7
9 changed files with 31 additions and 187 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 2
      arch/arm/dts/imx6qdl-icore-rqs.dtsi
  2. 2
      arch/arm/dts/imx6qdl-icore.dtsi
  3. 5
      arch/arm/dts/imx6qdl.dtsi
  4. 8
      arch/arm/mach-imx/mx6/Kconfig
  5. 75
      board/engicam/icorem6/icorem6.c
  6. 102
      board/engicam/icorem6_rqs/icorem6_rqs.c
  7. 1
      configs/imx6qdl_icore_mmc_defconfig
  8. 1
      configs/imx6qdl_icore_rqs_defconfig
  9. 22
      include/configs/imx6-engicam.h

2
arch/arm/dts/imx6qdl-icore-rqs.dtsi
Unescape View File

@ -100,6 +100,7 @@
};
&usdhc3 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -165,6 +166,7 @@
};
pinctrl_usdhc3: usdhc3grp {
u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070

2
arch/arm/dts/imx6qdl-icore.dtsi
Unescape View File

@ -118,6 +118,7 @@
};
&usdhc1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@ -208,6 +209,7 @@
};
pinctrl_usdhc1: usdhc1grp {
u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070

5
arch/arm/dts/imx6qdl.dtsi
Unescape View File

@ -77,6 +77,7 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
u-boot,dm-spl;
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@ -225,6 +226,7 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@ -516,6 +518,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@ -805,6 +808,7 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
u-boot,dm-spl;
};
ldb: ldb@020e0008 {
@ -889,6 +893,7 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
u-boot,dm-spl;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";

8
arch/arm/mach-imx/mx6/Kconfig
Unescape View File

@ -219,6 +219,10 @@ config TARGET_MX6Q_ICORE
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
config TARGET_MX6Q_ICORE_RQS
bool "Support Engicam i.Core RQS"
@ -234,6 +238,10 @@ config TARGET_MX6Q_ICORE_RQS
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
select SPL_DM if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SPL_PINCTRL if SPL
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"

75
board/engicam/icorem6/icorem6.c
Unescape View File

@ -7,7 +7,6 @@
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
@ -191,77 +190,3 @@ void setup_display(void)
writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */
#ifdef CONFIG_SPL_BUILD
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC1_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#endif
#endif /* CONFIG_SPL_BUILD */

102
board/engicam/icorem6_rqs/icorem6_rqs.c
Unescape View File

@ -6,21 +6,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include "../common/board.h"
DECLARE_GLOBAL_DATA_PTR;
@ -34,93 +20,6 @@ int board_mmc_get_env_dev(int devno)
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1, 4},
{USDHC4_BASE_ADDR, 1, 8},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC3_BASE_ADDR:
case USDHC4_BASE_ADDR:
ret = 1;
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC3
* mmc1 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
@ -146,5 +45,4 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[0] = boot_dev;
}
#endif
#endif
#endif /* CONFIG_SPL_BUILD */

1
configs/imx6qdl_icore_mmc_defconfig
Unescape View File

@ -48,3 +48,4 @@ CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IPUV3=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

1
configs/imx6qdl_icore_rqs_defconfig
Unescape View File

@ -40,3 +40,4 @@ CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_SYS_MALLOC_F_LEN=0x2000

22
include/configs/imx6-engicam.h
Unescape View File

@ -216,16 +216,18 @@
# include "imx6_spl.h"
# ifdef CONFIG_SPL_BUILD
# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)
# define CONFIG_SYS_FSL_USDHC_NUM 2
# else
# define CONFIG_SYS_FSL_USDHC_NUM 1
# endif
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
# undef CONFIG_DM_GPIO
# undef CONFIG_DM_MMC
# endif
# if defined(CONFIG_IMX6UL)
# if defined(CONFIG_TARGET_MX6UL_ISIOT)
# define CONFIG_SYS_FSL_USDHC_NUM 2
# else
# define CONFIG_SYS_FSL_USDHC_NUM 1
# endif
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
# undef CONFIG_DM_GPIO
# undef CONFIG_DM_MMC
# endif /* CONFIG_IMX6UL */
# endif /* CONFIG_SPL_BUILD */
#endif
#endif /* __IMX6_ENGICAM_CONFIG_H */

Write Preview
Loading…
Cancel
Save