Merge branch 'master' of http://git.denx.de/u-boot-sunxi
Tom Rini
8 years ago
commit
1f9ef0dca0
@ -0,0 +1,39 @@ |
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/*
|
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* Common PSCI functions |
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* |
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* Copyright (C) 2016 Chen-Yu Tsai |
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* Author: Chen-Yu Tsai <wens@csie.org> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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#include <config.h> |
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#include <asm/armv7.h> |
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#include <asm/macro.h> |
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#include <asm/psci.h> |
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#include <asm/secure.h> |
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#include <linux/linkage.h> |
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|
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static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; |
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|
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void __secure psci_save_target_pc(int cpu, u32 pc) |
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{ |
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psci_target_pc[cpu] = pc; |
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DSB; |
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} |
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|
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u32 __secure psci_get_target_pc(int cpu) |
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{ |
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return psci_target_pc[cpu]; |
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} |
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|
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@ -1,66 +0,0 @@ |
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/* |
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* Copyright (C) 2013 - ARM Ltd |
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* Author: Marc Zyngier <marc.zyngier@arm.com>
|
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* |
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* Based on code by Carl van Schaik <carl@ok-labs.com>.
|
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* |
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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#include <config.h> |
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#include <linux/linkage.h> |
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|
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#include <asm/arch-armv7/generictimer.h> |
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#include <asm/gic.h> |
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#include <asm/macro.h> |
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#include <asm/psci.h> |
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#include <asm/arch/cpu.h> |
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|
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/* |
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* Memory layout: |
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* |
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* SECURE_RAM to text_end : |
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* ._secure_text section
|
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* text_end to ALIGN_PAGE(text_end): |
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* nothing |
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) |
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* 1kB of stack per CPU (4 CPUs max). |
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*/ |
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|
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.pushsection ._secure.text, "ax" |
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|
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.arch_extension sec
|
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|
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#define GICD_BASE (SUNXI_GIC400_BASE + 0x1000) |
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#define GICC_BASE (SUNXI_GIC400_BASE + 0x2000) |
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|
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@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
|
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@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
|
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@ this function.
|
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ENTRY(psci_arch_init) |
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mov r6, lr |
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mov r7, r0 |
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bl psci_get_cpu_id @ CPU ID => r0
|
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bl psci_get_cpu_stack_top @ stack top => r0
|
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sub r0, r0, #4 @ Save space for target PC
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mov sp, r0 |
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mov r0, r7 |
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mov lr, r6 |
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|
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push {r0, r1, r2, ip, lr} |
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bl sunxi_gic_init |
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pop {r0, r1, r2, ip, pc} |
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ENDPROC(psci_arch_init) |
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|
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ENTRY(psci_text_end) |
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.popsection |
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@ -0,0 +1,178 @@ |
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/* |
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* Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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#include "sun8i-h3.dtsi" |
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#include "sunxi-common-regulators.dtsi" |
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|
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/pinctrl/sun4i-a10.h> |
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|
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/ { |
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model = "Xunlong Orange Pi Lite"; |
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compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; |
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|
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aliases { |
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/* The H3 emac is not used so the wifi is ethernet0 */ |
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ethernet1 = &rtl8189ftv; |
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serial0 = &uart0; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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leds { |
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compatible = "gpio-leds"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&leds_opc>, <&leds_r_opc>; |
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|
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pwr_led { |
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label = "orangepi:green:pwr"; |
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gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; |
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default-state = "on"; |
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}; |
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|
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status_led { |
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label = "orangepi:red:status"; |
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gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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|
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r_gpio_keys { |
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compatible = "gpio-keys"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&sw_r_opc>; |
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|
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sw4 { |
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label = "sw4"; |
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linux,code = <BTN_0>; |
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gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; |
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}; |
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}; |
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}; |
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|
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&ehci1 { |
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status = "okay"; |
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}; |
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|
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&ehci2 { |
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status = "okay"; |
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}; |
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|
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&ir { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&ir_pins_a>; |
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status = "okay"; |
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}; |
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|
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&mmc0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; |
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vmmc-supply = <®_vcc3v3>; |
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bus-width = <4>; |
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ |
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cd-inverted; |
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status = "okay"; |
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}; |
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|
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&mmc1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&mmc1_pins_a>; |
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vmmc-supply = <®_vcc3v3>; |
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bus-width = <4>; |
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non-removable; |
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status = "okay"; |
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|
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/* |
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* Explicitly define the sdio device, so that we can add an ethernet |
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* alias for it (which e.g. makes u-boot set a mac-address). |
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*/ |
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rtl8189ftv: sdio_wifi@1 { |
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reg = <1>; |
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}; |
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}; |
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|
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&ohci1 { |
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status = "okay"; |
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}; |
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|
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&ohci2 { |
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status = "okay"; |
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}; |
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|
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&pio { |
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leds_opc: led_pins@0 { |
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allwinner,pins = "PA15"; |
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allwinner,function = "gpio_out"; |
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allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
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}; |
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}; |
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|
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&r_pio { |
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leds_r_opc: led_pins@0 { |
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allwinner,pins = "PL10"; |
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allwinner,function = "gpio_out"; |
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allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
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}; |
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|
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sw_r_opc: key_pins@0 { |
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allwinner,pins = "PL3"; |
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allwinner,function = "gpio_in"; |
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allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; |
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}; |
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}; |
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|
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&uart0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&uart0_pins_a>; |
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status = "okay"; |
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}; |
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|
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&usbphy { |
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/* USB VBUS is always on */ |
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status = "okay"; |
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}; |
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@ -0,0 +1,15 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_SUNXI=y |
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CONFIG_MACH_SUN8I_H3=y |
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CONFIG_DRAM_CLK=672 |
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CONFIG_DRAM_ZQ=3881979 |
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CONFIG_DRAM_ODT_EN=y |
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CONFIG_MMC0_CD_PIN="PF6" |
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# CONFIG_VIDEO is not set |
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CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" |
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set |
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CONFIG_SPL=y |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_FPGA is not set |
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CONFIG_USB_EHCI_HCD=y |
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@ -0,0 +1,283 @@ |
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/*
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* Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <spl.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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|
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#ifdef CONFIG_SPL_OS_BOOT |
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#error CONFIG_SPL_OS_BOOT is not supported yet |
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#endif |
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|
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/*
|
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* This is a very simple U-Boot image loading implementation, trying to |
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* replicate what the boot ROM is doing when loading the SPL. Because we |
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* know the exact pins where the SPI Flash is connected and also know |
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* that the Read Data Bytes (03h) command is supported, the hardware |
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* configuration is very simple and we don't need the extra flexibility |
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* of the SPI framework. Moreover, we rely on the default settings of |
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* the SPI controler hardware registers and only adjust what needs to |
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* be changed. This is good for the code size and this implementation |
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* adds less than 400 bytes to the SPL. |
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* |
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* There are two variants of the SPI controller in Allwinner SoCs: |
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* A10/A13/A20 (sun4i variant) and everything else (sun6i variant). |
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* Both of them are supported. |
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* |
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* The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are |
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* supported at the moment. |
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*/ |
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|
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/*****************************************************************************/ |
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/* SUN4I variant of the SPI controller */ |
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/*****************************************************************************/ |
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|
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#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) |
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#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) |
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#define SUN4I_SPI0_RX (0x01C05000 + 0x00) |
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#define SUN4I_SPI0_TX (0x01C05000 + 0x04) |
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#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) |
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#define SUN4I_SPI0_BC (0x01C05000 + 0x20) |
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#define SUN4I_SPI0_TC (0x01C05000 + 0x24) |
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|
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#define SUN4I_CTL_ENABLE BIT(0) |
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#define SUN4I_CTL_MASTER BIT(1) |
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#define SUN4I_CTL_TF_RST BIT(8) |
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#define SUN4I_CTL_RF_RST BIT(9) |
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#define SUN4I_CTL_XCH BIT(10) |
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|
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/*****************************************************************************/ |
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/* SUN6I variant of the SPI controller */ |
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/*****************************************************************************/ |
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|
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#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) |
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#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) |
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#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) |
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#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) |
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#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) |
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#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) |
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#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) |
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#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) |
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#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) |
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|
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#define SUN6I_CTL_ENABLE BIT(0) |
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#define SUN6I_CTL_MASTER BIT(1) |
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#define SUN6I_CTL_SRST BIT(31) |
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#define SUN6I_TCR_XCH BIT(31) |
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|
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/*****************************************************************************/ |
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|
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#define CCM_AHB_GATING0 (0x01C20000 + 0x60) |
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#define CCM_SPI0_CLK (0x01C20000 + 0xA0) |
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#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) |
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|
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#define AHB_RESET_SPI0_SHIFT 20 |
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#define AHB_GATE_OFFSET_SPI0 20 |
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|
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#define SPI0_CLK_DIV_BY_2 0x1000 |
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#define SPI0_CLK_DIV_BY_4 0x1001 |
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|
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/*****************************************************************************/ |
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|
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/*
|
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* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting |
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* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. |
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*/ |
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static void spi0_pinmux_setup(unsigned int pin_function) |
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{ |
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unsigned int pin; |
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|
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for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) |
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sunxi_gpio_set_cfgpin(pin, pin_function); |
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|
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if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) |
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sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); |
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else |
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sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); |
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} |
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|
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/*
|
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* Setup 6 MHz from OSC24M (because the BROM is doing the same). |
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*/ |
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static void spi0_enable_clock(void) |
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{ |
||||
/* Deassert SPI0 reset on SUN6I */ |
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if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) |
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setbits_le32(SUN6I_BUS_SOFT_RST_REG0, |
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(1 << AHB_RESET_SPI0_SHIFT)); |
||||
|
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/* Open the SPI0 gate */ |
||||
setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); |
||||
|
||||
/* Divide by 4 */ |
||||
writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? |
||||
SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); |
||||
/* 24MHz from OSC24M */ |
||||
writel((1 << 31), CCM_SPI0_CLK); |
||||
|
||||
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { |
||||
/* Enable SPI in the master mode and do a soft reset */ |
||||
setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | |
||||
SUN6I_CTL_ENABLE | |
||||
SUN6I_CTL_SRST); |
||||
/* Wait for completion */ |
||||
while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) |
||||
; |
||||
} else { |
||||
/* Enable SPI in the master mode and reset FIFO */ |
||||
setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | |
||||
SUN4I_CTL_ENABLE | |
||||
SUN4I_CTL_TF_RST | |
||||
SUN4I_CTL_RF_RST); |
||||
} |
||||
} |
||||
|
||||
static void spi0_disable_clock(void) |
||||
{ |
||||
/* Disable the SPI0 controller */ |
||||
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) |
||||
clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | |
||||
SUN6I_CTL_ENABLE); |
||||
else |
||||
clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | |
||||
SUN4I_CTL_ENABLE); |
||||
|
||||
/* Disable the SPI0 clock */ |
||||
writel(0, CCM_SPI0_CLK); |
||||
|
||||
/* Close the SPI0 gate */ |
||||
clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); |
||||
|
||||
/* Assert SPI0 reset on SUN6I */ |
||||
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) |
||||
clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, |
||||
(1 << AHB_RESET_SPI0_SHIFT)); |
||||
} |
||||
|
||||
static int spi0_init(void) |
||||
{ |
||||
unsigned int pin_function = SUNXI_GPC_SPI0; |
||||
if (IS_ENABLED(CONFIG_MACH_SUN50I)) |
||||
pin_function = SUN50I_GPC_SPI0; |
||||
|
||||
spi0_pinmux_setup(pin_function); |
||||
spi0_enable_clock(); |
||||
} |
||||
|
||||
static void spi0_deinit(void) |
||||
{ |
||||
/* New SoCs can disable pins, older could only set them as input */ |
||||
unsigned int pin_function = SUNXI_GPIO_INPUT; |
||||
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) |
||||
pin_function = SUNXI_GPIO_DISABLE; |
||||
|
||||
spi0_disable_clock(); |
||||
spi0_pinmux_setup(pin_function); |
||||
} |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ |
||||
|
||||
static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, |
||||
u32 spi_ctl_reg, |
||||
u32 spi_ctl_xch_bitmask, |
||||
u32 spi_fifo_reg, |
||||
u32 spi_tx_reg, |
||||
u32 spi_rx_reg, |
||||
u32 spi_bc_reg, |
||||
u32 spi_tc_reg, |
||||
u32 spi_bcc_reg) |
||||
{ |
||||
writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ |
||||
writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ |
||||
if (spi_bcc_reg) |
||||
writel(4, spi_bcc_reg); /* SUN6I also needs this */ |
||||
|
||||
/* Send the Read Data Bytes (03h) command header */ |
||||
writeb(0x03, spi_tx_reg); |
||||
writeb((u8)(addr >> 16), spi_tx_reg); |
||||
writeb((u8)(addr >> 8), spi_tx_reg); |
||||
writeb((u8)(addr), spi_tx_reg); |
||||
|
||||
/* Start the data transfer */ |
||||
setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); |
||||
|
||||
/* Wait until everything is received in the RX FIFO */ |
||||
while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) |
||||
; |
||||
|
||||
/* Skip 4 bytes */ |
||||
readl(spi_rx_reg); |
||||
|
||||
/* Read the data */ |
||||
while (bufsize-- > 0) |
||||
*buf++ = readb(spi_rx_reg); |
||||
|
||||
/* tSHSL time is up to 100 ns in various SPI flash datasheets */ |
||||
udelay(1); |
||||
} |
||||
|
||||
static void spi0_read_data(void *buf, u32 addr, u32 len) |
||||
{ |
||||
u8 *buf8 = buf; |
||||
u32 chunk_len; |
||||
|
||||
while (len > 0) { |
||||
chunk_len = len; |
||||
if (chunk_len > SPI_READ_MAX_SIZE) |
||||
chunk_len = SPI_READ_MAX_SIZE; |
||||
|
||||
if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { |
||||
sunxi_spi0_read_data(buf8, addr, chunk_len, |
||||
SUN6I_SPI0_TCR, |
||||
SUN6I_TCR_XCH, |
||||
SUN6I_SPI0_FIFO_STA, |
||||
SUN6I_SPI0_TXD, |
||||
SUN6I_SPI0_RXD, |
||||
SUN6I_SPI0_MBC, |
||||
SUN6I_SPI0_MTC, |
||||
SUN6I_SPI0_BCC); |
||||
} else { |
||||
sunxi_spi0_read_data(buf8, addr, chunk_len, |
||||
SUN4I_SPI0_CTL, |
||||
SUN4I_CTL_XCH, |
||||
SUN4I_SPI0_FIFO_STA, |
||||
SUN4I_SPI0_TX, |
||||
SUN4I_SPI0_RX, |
||||
SUN4I_SPI0_BC, |
||||
SUN4I_SPI0_TC, |
||||
0); |
||||
} |
||||
|
||||
len -= chunk_len; |
||||
buf8 += chunk_len; |
||||
addr += chunk_len; |
||||
} |
||||
} |
||||
|
||||
/*****************************************************************************/ |
||||
|
||||
int spl_spi_load_image(void) |
||||
{ |
||||
int err; |
||||
struct image_header *header; |
||||
header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); |
||||
|
||||
spi0_init(); |
||||
|
||||
spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); |
||||
err = spl_parse_image_header(header); |
||||
if (err) |
||||
return err; |
||||
|
||||
spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, |
||||
spl_image.size); |
||||
|
||||
spi0_deinit(); |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,789 @@ |
||||
/*
|
||||
* (C) Copyright 2016 |
||||
* Author: Amit Singh Tomar, amittomer25@gmail.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Ethernet driver for H3/A64/A83T based SoC's |
||||
* |
||||
* It is derived from the work done by |
||||
* LABBE Corentin & Chen-Yu Tsai for Linux, THANKS! |
||||
* |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <fdt_support.h> |
||||
#include <linux/err.h> |
||||
#include <malloc.h> |
||||
#include <miiphy.h> |
||||
#include <net.h> |
||||
|
||||
#define SCTL_EMAC_TX_CLK_SRC_MII BIT(0) |
||||
#define SCTL_EMAC_EPIT_MII BIT(2) |
||||
#define SCTL_EMAC_CLK_SEL BIT(18) /* 25 Mhz */ |
||||
|
||||
#define MDIO_CMD_MII_BUSY BIT(0) |
||||
#define MDIO_CMD_MII_WRITE BIT(1) |
||||
|
||||
#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 |
||||
#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 |
||||
#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 |
||||
#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 |
||||
|
||||
#define CONFIG_TX_DESCR_NUM 32 |
||||
#define CONFIG_RX_DESCR_NUM 32 |
||||
#define CONFIG_ETH_BUFSIZE 2024 |
||||
|
||||
#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) |
||||
#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) |
||||
|
||||
#define H3_EPHY_DEFAULT_VALUE 0x58000 |
||||
#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) |
||||
#define H3_EPHY_ADDR_SHIFT 20 |
||||
#define REG_PHY_ADDR_MASK GENMASK(4, 0) |
||||
#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ |
||||
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ |
||||
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ |
||||
|
||||
#define SC_RMII_EN BIT(13) |
||||
#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */ |
||||
#define SC_ETCS_MASK GENMASK(1, 0) |
||||
#define SC_ETCS_EXT_GMII 0x1 |
||||
#define SC_ETCS_INT_GMII 0x2 |
||||
|
||||
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) |
||||
|
||||
#define AHB_GATE_OFFSET_EPHY 0 |
||||
|
||||
#if defined(CONFIG_MACH_SUN8I_H3) |
||||
#define SUN8I_GPD8_GMAC 2 |
||||
#else |
||||
#define SUN8I_GPD8_GMAC 4 |
||||
#endif |
||||
|
||||
/* H3/A64 EMAC Register's offset */ |
||||
#define EMAC_CTL0 0x00 |
||||
#define EMAC_CTL1 0x04 |
||||
#define EMAC_INT_STA 0x08 |
||||
#define EMAC_INT_EN 0x0c |
||||
#define EMAC_TX_CTL0 0x10 |
||||
#define EMAC_TX_CTL1 0x14 |
||||
#define EMAC_TX_FLOW_CTL 0x1c |
||||
#define EMAC_TX_DMA_DESC 0x20 |
||||
#define EMAC_RX_CTL0 0x24 |
||||
#define EMAC_RX_CTL1 0x28 |
||||
#define EMAC_RX_DMA_DESC 0x34 |
||||
#define EMAC_MII_CMD 0x48 |
||||
#define EMAC_MII_DATA 0x4c |
||||
#define EMAC_ADDR0_HIGH 0x50 |
||||
#define EMAC_ADDR0_LOW 0x54 |
||||
#define EMAC_TX_DMA_STA 0xb0 |
||||
#define EMAC_TX_CUR_DESC 0xb4 |
||||
#define EMAC_TX_CUR_BUF 0xb8 |
||||
#define EMAC_RX_DMA_STA 0xc0 |
||||
#define EMAC_RX_CUR_DESC 0xc4 |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
enum emac_variant { |
||||
A83T_EMAC = 1, |
||||
H3_EMAC, |
||||
A64_EMAC, |
||||
}; |
||||
|
||||
struct emac_dma_desc { |
||||
u32 status; |
||||
u32 st; |
||||
u32 buf_addr; |
||||
u32 next; |
||||
} __aligned(ARCH_DMA_MINALIGN); |
||||
|
||||
struct emac_eth_dev { |
||||
struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; |
||||
struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; |
||||
char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
||||
char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
||||
|
||||
u32 interface; |
||||
u32 phyaddr; |
||||
u32 link; |
||||
u32 speed; |
||||
u32 duplex; |
||||
u32 phy_configured; |
||||
u32 tx_currdescnum; |
||||
u32 rx_currdescnum; |
||||
u32 addr; |
||||
u32 tx_slot; |
||||
bool use_internal_phy; |
||||
|
||||
enum emac_variant variant; |
||||
void *mac_reg; |
||||
phys_addr_t sysctl_reg; |
||||
struct phy_device *phydev; |
||||
struct mii_dev *bus; |
||||
}; |
||||
|
||||
static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
||||
{ |
||||
struct emac_eth_dev *priv = bus->priv; |
||||
ulong start; |
||||
u32 miiaddr = 0; |
||||
int timeout = CONFIG_MDIO_TIMEOUT; |
||||
|
||||
miiaddr &= ~MDIO_CMD_MII_WRITE; |
||||
miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
||||
miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & |
||||
MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
||||
|
||||
miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; |
||||
|
||||
miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & |
||||
MDIO_CMD_MII_PHY_ADDR_MASK; |
||||
|
||||
miiaddr |= MDIO_CMD_MII_BUSY; |
||||
|
||||
writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); |
||||
|
||||
start = get_timer(0); |
||||
while (get_timer(start) < timeout) { |
||||
if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) |
||||
return readl(priv->mac_reg + EMAC_MII_DATA); |
||||
udelay(10); |
||||
}; |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
||||
u16 val) |
||||
{ |
||||
struct emac_eth_dev *priv = bus->priv; |
||||
ulong start; |
||||
u32 miiaddr = 0; |
||||
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; |
||||
|
||||
miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
||||
miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & |
||||
MDIO_CMD_MII_PHY_REG_ADDR_MASK; |
||||
|
||||
miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; |
||||
miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & |
||||
MDIO_CMD_MII_PHY_ADDR_MASK; |
||||
|
||||
miiaddr |= MDIO_CMD_MII_WRITE; |
||||
miiaddr |= MDIO_CMD_MII_BUSY; |
||||
|
||||
writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); |
||||
writel(val, priv->mac_reg + EMAC_MII_DATA); |
||||
|
||||
start = get_timer(0); |
||||
while (get_timer(start) < timeout) { |
||||
if (!(readl(priv->mac_reg + EMAC_MII_CMD) & |
||||
MDIO_CMD_MII_BUSY)) { |
||||
ret = 0; |
||||
break; |
||||
} |
||||
udelay(10); |
||||
}; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id) |
||||
{ |
||||
u32 macid_lo, macid_hi; |
||||
|
||||
macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + |
||||
(mac_id[3] << 24); |
||||
macid_hi = mac_id[4] + (mac_id[5] << 8); |
||||
|
||||
writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH); |
||||
writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void sun8i_adjust_link(struct emac_eth_dev *priv, |
||||
struct phy_device *phydev) |
||||
{ |
||||
u32 v; |
||||
|
||||
v = readl(priv->mac_reg + EMAC_CTL0); |
||||
|
||||
if (phydev->duplex) |
||||
v |= BIT(0); |
||||
else |
||||
v &= ~BIT(0); |
||||
|
||||
v &= ~0x0C; |
||||
|
||||
switch (phydev->speed) { |
||||
case 1000: |
||||
break; |
||||
case 100: |
||||
v |= BIT(2); |
||||
v |= BIT(3); |
||||
break; |
||||
case 10: |
||||
v |= BIT(3); |
||||
break; |
||||
} |
||||
writel(v, priv->mac_reg + EMAC_CTL0); |
||||
} |
||||
|
||||
static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) |
||||
{ |
||||
if (priv->use_internal_phy) { |
||||
/* H3 based SoC's that has an Internal 100MBit PHY
|
||||
* needs to be configured and powered up before use |
||||
*/ |
||||
*reg &= ~H3_EPHY_DEFAULT_MASK; |
||||
*reg |= H3_EPHY_DEFAULT_VALUE; |
||||
*reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; |
||||
*reg &= ~H3_EPHY_SHUTDOWN; |
||||
*reg |= H3_EPHY_SELECT; |
||||
} else |
||||
/* This is to select External Gigabit PHY on
|
||||
* the boards with H3 SoC. |
||||
*/ |
||||
*reg &= ~H3_EPHY_SELECT; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) |
||||
{ |
||||
int ret; |
||||
u32 reg; |
||||
|
||||
reg = readl(priv->sysctl_reg); |
||||
|
||||
if (priv->variant == H3_EMAC) { |
||||
ret = sun8i_emac_set_syscon_ephy(priv, ®); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
reg &= ~(SC_ETCS_MASK | SC_EPIT); |
||||
if (priv->variant == H3_EMAC || priv->variant == A64_EMAC) |
||||
reg &= ~SC_RMII_EN; |
||||
|
||||
switch (priv->interface) { |
||||
case PHY_INTERFACE_MODE_MII: |
||||
/* default */ |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
reg |= SC_EPIT | SC_ETCS_INT_GMII; |
||||
break; |
||||
case PHY_INTERFACE_MODE_RMII: |
||||
if (priv->variant == H3_EMAC || |
||||
priv->variant == A64_EMAC) { |
||||
reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; |
||||
break; |
||||
} |
||||
/* RMII not supported on A83T */ |
||||
default: |
||||
debug("%s: Invalid PHY interface\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
writel(reg, priv->sysctl_reg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) |
||||
{ |
||||
struct phy_device *phydev; |
||||
|
||||
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); |
||||
if (!phydev) |
||||
return -ENODEV; |
||||
|
||||
phy_connect_dev(phydev, dev); |
||||
|
||||
priv->phydev = phydev; |
||||
phy_config(priv->phydev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void rx_descs_init(struct emac_eth_dev *priv) |
||||
{ |
||||
struct emac_dma_desc *desc_table_p = &priv->rx_chain[0]; |
||||
char *rxbuffs = &priv->rxbuffer[0]; |
||||
struct emac_dma_desc *desc_p; |
||||
u32 idx; |
||||
|
||||
/* flush Rx buffers */ |
||||
flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs + |
||||
RX_TOTAL_BUFSIZE); |
||||
|
||||
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
||||
desc_p = &desc_table_p[idx]; |
||||
desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE] |
||||
; |
||||
desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; |
||||
desc_p->st |= CONFIG_ETH_BUFSIZE; |
||||
desc_p->status = BIT(31); |
||||
} |
||||
|
||||
/* Correcting the last pointer of the chain */ |
||||
desc_p->next = (uintptr_t)&desc_table_p[0]; |
||||
|
||||
flush_dcache_range((uintptr_t)priv->rx_chain, |
||||
(uintptr_t)priv->rx_chain + |
||||
sizeof(priv->rx_chain)); |
||||
|
||||
writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC)); |
||||
priv->rx_currdescnum = 0; |
||||
} |
||||
|
||||
static void tx_descs_init(struct emac_eth_dev *priv) |
||||
{ |
||||
struct emac_dma_desc *desc_table_p = &priv->tx_chain[0]; |
||||
char *txbuffs = &priv->txbuffer[0]; |
||||
struct emac_dma_desc *desc_p; |
||||
u32 idx; |
||||
|
||||
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { |
||||
desc_p = &desc_table_p[idx]; |
||||
desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE] |
||||
; |
||||
desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; |
||||
desc_p->status = (1 << 31); |
||||
desc_p->st = 0; |
||||
} |
||||
|
||||
/* Correcting the last pointer of the chain */ |
||||
desc_p->next = (uintptr_t)&desc_table_p[0]; |
||||
|
||||
/* Flush all Tx buffer descriptors */ |
||||
flush_dcache_range((uintptr_t)priv->tx_chain, |
||||
(uintptr_t)priv->tx_chain + |
||||
sizeof(priv->tx_chain)); |
||||
|
||||
writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC); |
||||
priv->tx_currdescnum = 0; |
||||
} |
||||
|
||||
static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) |
||||
{ |
||||
u32 reg, v; |
||||
int timeout = 100; |
||||
|
||||
reg = readl((priv->mac_reg + EMAC_CTL1)); |
||||
|
||||
if (!(reg & 0x1)) { |
||||
/* Soft reset MAC */ |
||||
setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1); |
||||
do { |
||||
reg = readl(priv->mac_reg + EMAC_CTL1); |
||||
} while ((reg & 0x01) != 0 && (--timeout)); |
||||
if (!timeout) { |
||||
printf("%s: Timeout\n", __func__); |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
/* Rewrite mac address after reset */ |
||||
_sun8i_write_hwaddr(priv, enetaddr); |
||||
|
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1); |
||||
/* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/ |
||||
v |= BIT(1); |
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1); |
||||
|
||||
v = readl(priv->mac_reg + EMAC_RX_CTL1); |
||||
/* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
|
||||
* complete frame has been written to RX DMA FIFO |
||||
*/ |
||||
v |= BIT(1); |
||||
writel(v, priv->mac_reg + EMAC_RX_CTL1); |
||||
|
||||
/* DMA */ |
||||
writel(8 << 24, priv->mac_reg + EMAC_CTL1); |
||||
|
||||
/* Initialize rx/tx descriptors */ |
||||
rx_descs_init(priv); |
||||
tx_descs_init(priv); |
||||
|
||||
/* PHY Start Up */ |
||||
genphy_parse_link(priv->phydev); |
||||
|
||||
sun8i_adjust_link(priv, priv->phydev); |
||||
|
||||
/* Start RX DMA */ |
||||
v = readl(priv->mac_reg + EMAC_RX_CTL1); |
||||
v |= BIT(30); |
||||
writel(v, priv->mac_reg + EMAC_RX_CTL1); |
||||
/* Start TX DMA */ |
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1); |
||||
v |= BIT(30); |
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1); |
||||
|
||||
/* Enable RX/TX */ |
||||
setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); |
||||
setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int parse_phy_pins(struct udevice *dev) |
||||
{ |
||||
int offset; |
||||
const char *pin_name; |
||||
int drive, pull, i; |
||||
|
||||
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
||||
"pinctrl-0"); |
||||
if (offset < 0) { |
||||
printf("WARNING: emac: cannot find pinctrl-0 node\n"); |
||||
return offset; |
||||
} |
||||
|
||||
drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, |
||||
"allwinner,drive", 4); |
||||
pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, |
||||
"allwinner,pull", 0); |
||||
for (i = 0; ; i++) { |
||||
int pin; |
||||
|
||||
if (fdt_get_string_index(gd->fdt_blob, offset, |
||||
"allwinner,pins", i, &pin_name)) |
||||
break; |
||||
if (pin_name[0] != 'P') |
||||
continue; |
||||
pin = (pin_name[1] - 'A') << 5; |
||||
if (pin >= 26 << 5) |
||||
continue; |
||||
pin += simple_strtol(&pin_name[2], NULL, 10); |
||||
|
||||
sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); |
||||
sunxi_gpio_set_drv(pin, drive); |
||||
sunxi_gpio_set_pull(pin, pull); |
||||
} |
||||
|
||||
if (!i) { |
||||
printf("WARNING: emac: cannot find allwinner,pins property\n"); |
||||
return -2; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp) |
||||
{ |
||||
u32 status, desc_num = priv->rx_currdescnum; |
||||
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; |
||||
int length = -EAGAIN; |
||||
int good_packet = 1; |
||||
uintptr_t desc_start = (uintptr_t)desc_p; |
||||
uintptr_t desc_end = desc_start + |
||||
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
||||
|
||||
ulong data_start = (uintptr_t)desc_p->buf_addr; |
||||
ulong data_end; |
||||
|
||||
/* Invalidate entire buffer descriptor */ |
||||
invalidate_dcache_range(desc_start, desc_end); |
||||
|
||||
status = desc_p->status; |
||||
|
||||
/* Check for DMA own bit */ |
||||
if (!(status & BIT(31))) { |
||||
length = (desc_p->status >> 16) & 0x3FFF; |
||||
|
||||
if (length < 0x40) { |
||||
good_packet = 0; |
||||
debug("RX: Bad Packet (runt)\n"); |
||||
} |
||||
|
||||
data_end = data_start + length; |
||||
/* Invalidate received data */ |
||||
invalidate_dcache_range(rounddown(data_start, |
||||
ARCH_DMA_MINALIGN), |
||||
roundup(data_end, |
||||
ARCH_DMA_MINALIGN)); |
||||
if (good_packet) { |
||||
if (length > CONFIG_ETH_BUFSIZE) { |
||||
printf("Received packet is too big (len=%d)\n", |
||||
length); |
||||
return -EMSGSIZE; |
||||
} |
||||
*packetp = (uchar *)(ulong)desc_p->buf_addr; |
||||
return length; |
||||
} |
||||
} |
||||
|
||||
return length; |
||||
} |
||||
|
||||
static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet, |
||||
int len) |
||||
{ |
||||
u32 v, desc_num = priv->tx_currdescnum; |
||||
struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num]; |
||||
uintptr_t desc_start = (uintptr_t)desc_p; |
||||
uintptr_t desc_end = desc_start + |
||||
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
||||
|
||||
uintptr_t data_start = (uintptr_t)desc_p->buf_addr; |
||||
uintptr_t data_end = data_start + |
||||
roundup(len, ARCH_DMA_MINALIGN); |
||||
|
||||
/* Invalidate entire buffer descriptor */ |
||||
invalidate_dcache_range(desc_start, desc_end); |
||||
|
||||
desc_p->st = len; |
||||
/* Mandatory undocumented bit */ |
||||
desc_p->st |= BIT(24); |
||||
|
||||
memcpy((void *)data_start, packet, len); |
||||
|
||||
/* Flush data to be sent */ |
||||
flush_dcache_range(data_start, data_end); |
||||
|
||||
/* frame end */ |
||||
desc_p->st |= BIT(30); |
||||
desc_p->st |= BIT(31); |
||||
|
||||
/*frame begin */ |
||||
desc_p->st |= BIT(29); |
||||
desc_p->status = BIT(31); |
||||
|
||||
/*Descriptors st and status field has changed, so FLUSH it */ |
||||
flush_dcache_range(desc_start, desc_end); |
||||
|
||||
/* Move to next Descriptor and wrap around */ |
||||
if (++desc_num >= CONFIG_TX_DESCR_NUM) |
||||
desc_num = 0; |
||||
priv->tx_currdescnum = desc_num; |
||||
|
||||
/* Start the DMA */ |
||||
v = readl(priv->mac_reg + EMAC_TX_CTL1); |
||||
v |= BIT(31);/* mandatory */ |
||||
v |= BIT(30);/* mandatory */ |
||||
writel(v, priv->mac_reg + EMAC_TX_CTL1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int sun8i_eth_write_hwaddr(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
return _sun8i_write_hwaddr(priv, pdata->enetaddr); |
||||
} |
||||
|
||||
static void sun8i_emac_board_setup(struct emac_eth_dev *priv) |
||||
{ |
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; |
||||
|
||||
if (priv->use_internal_phy) { |
||||
/* Set clock gating for ephy */ |
||||
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); |
||||
|
||||
/* Set Tx clock source as MII with rate 25 MZ */ |
||||
setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII | |
||||
SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL); |
||||
/* Deassert EPHY */ |
||||
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); |
||||
} |
||||
|
||||
/* Set clock gating for emac */ |
||||
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); |
||||
|
||||
/* Set EMAC clock */ |
||||
setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0))); |
||||
|
||||
/* De-assert EMAC */ |
||||
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); |
||||
} |
||||
|
||||
static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) |
||||
{ |
||||
struct mii_dev *bus = mdio_alloc(); |
||||
|
||||
if (!bus) { |
||||
debug("Failed to allocate MDIO bus\n"); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
bus->read = sun8i_mdio_read; |
||||
bus->write = sun8i_mdio_write; |
||||
snprintf(bus->name, sizeof(bus->name), name); |
||||
bus->priv = (void *)priv; |
||||
|
||||
return mdio_register(bus); |
||||
} |
||||
|
||||
static int sun8i_emac_eth_start(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
|
||||
return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr); |
||||
} |
||||
|
||||
static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length) |
||||
{ |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
return _sun8i_emac_eth_send(priv, packet, length); |
||||
} |
||||
|
||||
static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
||||
{ |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
return _sun8i_eth_recv(priv, packetp); |
||||
} |
||||
|
||||
static int _sun8i_free_pkt(struct emac_eth_dev *priv) |
||||
{ |
||||
u32 desc_num = priv->rx_currdescnum; |
||||
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; |
||||
uintptr_t desc_start = (uintptr_t)desc_p; |
||||
uintptr_t desc_end = desc_start + |
||||
roundup(sizeof(u32), ARCH_DMA_MINALIGN); |
||||
|
||||
/* Make the current descriptor valid again */ |
||||
desc_p->status |= BIT(31); |
||||
|
||||
/* Flush Status field of descriptor */ |
||||
flush_dcache_range(desc_start, desc_end); |
||||
|
||||
/* Move to next desc and wrap-around condition. */ |
||||
if (++desc_num >= CONFIG_RX_DESCR_NUM) |
||||
desc_num = 0; |
||||
priv->rx_currdescnum = desc_num; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet, |
||||
int length) |
||||
{ |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
return _sun8i_free_pkt(priv); |
||||
} |
||||
|
||||
static void sun8i_emac_eth_stop(struct udevice *dev) |
||||
{ |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
/* Stop Rx/Tx transmitter */ |
||||
clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); |
||||
clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); |
||||
|
||||
/* Stop TX DMA */ |
||||
clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30)); |
||||
|
||||
phy_shutdown(priv->phydev); |
||||
} |
||||
|
||||
static int sun8i_emac_eth_probe(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
|
||||
priv->mac_reg = (void *)pdata->iobase; |
||||
|
||||
sun8i_emac_board_setup(priv); |
||||
|
||||
sun8i_mdio_init(dev->name, priv); |
||||
priv->bus = miiphy_get_dev_by_name(dev->name); |
||||
|
||||
sun8i_emac_set_syscon(priv); |
||||
|
||||
return sun8i_phy_init(priv, dev); |
||||
} |
||||
|
||||
static const struct eth_ops sun8i_emac_eth_ops = { |
||||
.start = sun8i_emac_eth_start, |
||||
.write_hwaddr = sun8i_eth_write_hwaddr, |
||||
.send = sun8i_emac_eth_send, |
||||
.recv = sun8i_emac_eth_recv, |
||||
.free_pkt = sun8i_eth_free_pkt, |
||||
.stop = sun8i_emac_eth_stop, |
||||
}; |
||||
|
||||
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct eth_pdata *pdata = dev_get_platdata(dev); |
||||
struct emac_eth_dev *priv = dev_get_priv(dev); |
||||
const char *phy_mode; |
||||
int offset = 0; |
||||
|
||||
pdata->iobase = dev_get_addr_name(dev, "emac"); |
||||
priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); |
||||
|
||||
pdata->phy_interface = -1; |
||||
priv->phyaddr = -1; |
||||
priv->use_internal_phy = false; |
||||
|
||||
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
||||
"phy"); |
||||
if (offset > 0) |
||||
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", |
||||
-1); |
||||
|
||||
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); |
||||
|
||||
if (phy_mode) |
||||
pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
||||
printf("phy interface%d\n", pdata->phy_interface); |
||||
|
||||
if (pdata->phy_interface == -1) { |
||||
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
priv->variant = dev_get_driver_data(dev); |
||||
|
||||
if (!priv->variant) { |
||||
printf("%s: Missing variant '%s'\n", __func__, |
||||
(char *)priv->variant); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
if (priv->variant == H3_EMAC) { |
||||
if (fdt_getprop(gd->fdt_blob, dev->of_offset, |
||||
"allwinner,use-internal-phy", NULL)) |
||||
priv->use_internal_phy = true; |
||||
} |
||||
|
||||
priv->interface = pdata->phy_interface; |
||||
|
||||
if (!priv->use_internal_phy) |
||||
parse_phy_pins(dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id sun8i_emac_eth_ids[] = { |
||||
{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, |
||||
{.compatible = "allwinner,sun50i-a64-emac", |
||||
.data = (uintptr_t)A64_EMAC }, |
||||
{.compatible = "allwinner,sun8i-a83t-emac", |
||||
.data = (uintptr_t)A83T_EMAC }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(eth_sun8i_emac) = { |
||||
.name = "eth_sun8i_emac", |
||||
.id = UCLASS_ETH, |
||||
.of_match = sun8i_emac_eth_ids, |
||||
.ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata, |
||||
.probe = sun8i_emac_eth_probe, |
||||
.ops = &sun8i_emac_eth_ops, |
||||
.priv_auto_alloc_size = sizeof(struct emac_eth_dev), |
||||
.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
||||
.flags = DM_FLAG_ALLOC_PRIV_DMA, |
||||
}; |
||||
Loading…
Reference in new issue