Tom Rini
11 years ago
commit
2086e388d5
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/**
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* Copyright 2014 Freescale Semiconductor |
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* |
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* Author: Chunhe Lan <Chunhe.Lan@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* This file provides support for the board-specific CPLD used on some Freescale |
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* reference boards. |
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* |
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* The following macros need to be defined: |
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* |
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* CONFIG_SYS_CPLD_BASE - The virtual address of the base of the |
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* CPLD register map |
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* |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include "cpld.h" |
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u8 cpld_read(unsigned int reg) |
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{ |
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void *p = (void *)CONFIG_SYS_CPLD_BASE; |
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return in_8(p + reg); |
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} |
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void cpld_write(unsigned int reg, u8 value) |
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{ |
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void *p = (void *)CONFIG_SYS_CPLD_BASE; |
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out_8(p + reg, value); |
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} |
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/**
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* Set the boot bank to the alternate bank |
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*/ |
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void cpld_set_altbank(void) |
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{ |
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u8 val, curbank, altbank, override; |
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val = CPLD_READ(vbank); |
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curbank = val & CPLD_BANK_SEL_MASK; |
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switch (curbank) { |
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case CPLD_SELECT_BANK0: |
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altbank = CPLD_SELECT_BANK4; |
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CPLD_WRITE(vbank, altbank); |
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override = CPLD_READ(software_on); |
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CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); |
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CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); |
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break; |
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case CPLD_SELECT_BANK4: |
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altbank = CPLD_SELECT_BANK0; |
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CPLD_WRITE(vbank, altbank); |
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override = CPLD_READ(software_on); |
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CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); |
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CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); |
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break; |
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default: |
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printf("CPLD Altbank Fail: Invalid value!\n"); |
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return; |
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} |
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} |
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/**
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* Set the boot bank to the default bank |
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*/ |
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void cpld_set_defbank(void) |
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{ |
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u8 val; |
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val = CPLD_DEFAULT_BANK; |
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CPLD_WRITE(global_reset, val); |
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} |
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#ifdef DEBUG |
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static void cpld_dump_regs(void) |
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{ |
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printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); |
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printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); |
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printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); |
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printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); |
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printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); |
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printf("software_on = 0x%02x\n", CPLD_READ(software_on)); |
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printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); |
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printf("res0 = 0x%02x\n", CPLD_READ(res0)); |
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printf("vbank = 0x%02x\n", CPLD_READ(vbank)); |
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printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); |
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printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); |
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printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); |
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printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); |
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printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); |
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printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); |
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printf("res1 = 0x%02x\n", CPLD_READ(res1)); |
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putc('\n'); |
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} |
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#endif |
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#ifndef CONFIG_SPL_BUILD |
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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int rc = 0; |
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if (argc <= 1) |
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return cmd_usage(cmdtp); |
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if (strcmp(argv[1], "reset") == 0) { |
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if (strcmp(argv[2], "altbank") == 0) |
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cpld_set_altbank(); |
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else |
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cpld_set_defbank(); |
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#ifdef DEBUG |
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} else if (strcmp(argv[1], "dump") == 0) { |
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cpld_dump_regs(); |
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#endif |
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} else |
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rc = cmd_usage(cmdtp); |
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return rc; |
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} |
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U_BOOT_CMD( |
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cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, |
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"Reset the board or alternate bank", |
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"reset - reset to default bank\n" |
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"cpld reset altbank - reset to alternate bank\n" |
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#ifdef DEBUG |
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"cpld dump - display the CPLD registers\n" |
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#endif |
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); |
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#endif |
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@ -0,0 +1,49 @@ |
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/**
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* Copyright 2014 Freescale Semiconductor |
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* |
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* Author: Chunhe Lan <Chunhe.Lan@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* This file provides support for the ngPIXIS, a board-specific FPGA used on |
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* some Freescale reference boards. |
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*/ |
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary. |
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*/ |
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struct cpld_data { |
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u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ |
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u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ |
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u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ |
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u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ |
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u8 hw_ver; /* 0x04 - PCBA Version Register */ |
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u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ |
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u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ |
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u8 res0; /* 0x07 - not used */ |
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u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ |
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u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ |
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u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ |
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u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ |
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u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ |
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u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ |
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u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ |
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u8 res1; /* 0x0f - not used */ |
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}; |
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#define CPLD_BANK_SEL_MASK 0x07 |
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#define CPLD_BANK_SEL_EN 0x04 |
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#define CPLD_SYSTEM_RESET 0x01 |
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#define CPLD_SELECT_BANK0 0x00 |
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#define CPLD_SELECT_BANK4 0x04 |
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#define CPLD_DEFAULT_BANK 0x01 |
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/* Pointer to the CPLD register set */ |
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u8 cpld_read(unsigned int reg); |
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void cpld_write(unsigned int reg, u8 value); |
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) |
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#define CPLD_WRITE(reg, value) \ |
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cpld_write(offsetof(struct cpld_data, reg), value) |
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