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@ -51,6 +51,17 @@ static iomux_v3_cfg_t const gw5904_emmc_pads[] = { |
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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}; |
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/* 4-bit microSD on SD2 */ |
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static iomux_v3_cfg_t const gw5904_mmc_pads[] = { |
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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/* CD */ |
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IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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}; |
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/* 8-bit eMMC on SD2/NAND */ |
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static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = { |
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IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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@ -412,6 +423,39 @@ static iomux_v3_cfg_t const gw560x_gpio_pads[] = { |
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IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw5903_gpio_pads[] = { |
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/* BKLT_12VEN */ |
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IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), |
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/* EMMY_PDN# */ |
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IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG), |
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/* EMMY_CFG1# */ |
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IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), |
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/* EMMY_CFG1# */ |
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IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG), |
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/* USBH1_PEN (EHCI) */ |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), |
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/* USBH2_PEN (OTG) */ |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), |
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/* USBDPC_PEN */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* TOUCH_RST */ |
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IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), |
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/* AUDIO_RST# */ |
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IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), |
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/* UART1_TEN# */ |
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IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG), |
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/* MX6_LOCLED# */ |
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IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), |
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/* LVDS_BKLEN # */ |
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IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), |
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/* RGMII_PDWN# */ |
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IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG), |
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/* TOUCH_IRQ# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* TOUCH_RST# */ |
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IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw5904_gpio_pads[] = { |
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/* USB_HUBRST# */ |
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IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), |
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@ -688,6 +732,9 @@ struct dio_cfg gw560x_dio[] = { |
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}, |
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}; |
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struct dio_cfg gw5903_dio[] = { |
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}; |
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struct dio_cfg gw5904_dio[] = { |
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{ |
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{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, |
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@ -951,6 +998,19 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { |
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.mmc_cd = IMX_GPIO_NR(7, 0), |
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}, |
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/* GW5903 */ |
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{ |
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.gpio_pads = gw5903_gpio_pads, |
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.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2, |
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.dio_cfg = gw5903_dio, |
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.dio_num = ARRAY_SIZE(gw5903_dio), |
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.leds = { |
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IMX_GPIO_NR(6, 14), |
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}, |
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.otgpwr_en = IMX_GPIO_NR(4, 15), |
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.mmc_cd = IMX_GPIO_NR(6, 11), |
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}, |
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/* GW5904 */ |
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{ |
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.gpio_pads = gw5904_gpio_pads, |
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@ -1087,6 +1147,22 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) |
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gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); |
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gpio_direction_output(IMX_GPIO_NR(4, 26), 1); |
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break; |
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case GW5903: |
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gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr"); |
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gpio_direction_output(IMX_GPIO_NR(3, 31), 1); |
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gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr"); |
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gpio_direction_output(IMX_GPIO_NR(4, 15), 1); |
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gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr"); |
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gpio_direction_output(IMX_GPIO_NR(4, 15), 1); |
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gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en"); |
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gpio_direction_output(IMX_GPIO_NR(1, 25), 1); |
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gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#"); |
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gpio_direction_input(IMX_GPIO_NR(4, 6)); |
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gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst"); |
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gpio_direction_output(IMX_GPIO_NR(4, 8), 1); |
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gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven"); |
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gpio_direction_output(IMX_GPIO_NR(1, 7), 1); |
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break; |
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case GW5904: |
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gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#"); |
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gpio_direction_output(IMX_GPIO_NR(5, 11), 1); |
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@ -1248,6 +1324,13 @@ void setup_pmic(void) |
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/* set SW3 (VDD_ARM) */ |
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pmic_reg_write(p, LTC3676_DVB3A, 0x1f); |
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break; |
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case GW5903: |
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/* mask PGOOD during SW4 transition */ |
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pmic_reg_write(p, LTC3676_DVB4B, |
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0x1f | LTC3676_PGOOD_MASK); |
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/* set SW4 (VDD_SOC) */ |
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pmic_reg_write(p, LTC3676_DVB4A, 0x1f); |
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break; |
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default: |
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/* mask PGOOD during SW1 transition */ |
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pmic_reg_write(p, LTC3676_DVB1B, |
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@ -1299,6 +1382,21 @@ int board_mmc_init(bd_t *bis) |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[1].max_bus_width = 4; |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); |
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case GW5903: |
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/* usdhc3: 8-bit eMMC */ |
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SETUP_IOMUX_PADS(gw5904_emmc_pads); |
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg[0].max_bus_width = 8; |
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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if (ret) |
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return ret; |
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/* usdhc2: 4-bit microSD */ |
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SETUP_IOMUX_PADS(gw5904_mmc_pads); |
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usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; |
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
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usdhc_cfg[1].max_bus_width = 4; |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); |
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case GW5904: |
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/* usdhc3: 8bit eMMC */ |
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SETUP_IOMUX_PADS(gw5904_emmc_pads); |
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@ -1326,6 +1424,7 @@ int board_mmc_getcd(struct mmc *mmc) |
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if (cfg->esdhc_base == USDHC2_BASE_ADDR) |
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return 1; |
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break; |
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case GW5903: |
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case GW5904: |
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/* emmc is always present */ |
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if (cfg->esdhc_base == USDHC3_BASE_ADDR) |
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