Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>lime2-spi
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marek Vasut <marex@denx.de> |
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* |
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* Altera SoCFPGA EMAC extras |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <dm.h> |
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#include <clk.h> |
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#include <phy.h> |
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#include <regmap.h> |
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#include <reset.h> |
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#include <syscon.h> |
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#include "designware.h" |
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#include <asm/arch/system_manager.h> |
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enum dwmac_type { |
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DWMAC_SOCFPGA_GEN5 = 0, |
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DWMAC_SOCFPGA_ARRIA10, |
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DWMAC_SOCFPGA_STRATIX10, |
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}; |
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struct dwmac_socfpga_platdata { |
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struct dw_eth_pdata dw_eth_pdata; |
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enum dwmac_type type; |
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void *phy_intf; |
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}; |
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static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); |
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struct regmap *regmap; |
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struct ofnode_phandle_args args; |
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void *range; |
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int ret; |
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ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, |
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2, 0, &args); |
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if (ret) { |
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dev_err(dev, "Failed to get syscon: %d\n", ret); |
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return ret; |
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} |
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if (args.args_count != 2) { |
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dev_err(dev, "Invalid number of syscon args\n"); |
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return -EINVAL; |
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} |
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regmap = syscon_node_to_regmap(args.node); |
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if (IS_ERR(regmap)) { |
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ret = PTR_ERR(regmap); |
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dev_err(dev, "Failed to get regmap: %d\n", ret); |
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return ret; |
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} |
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range = regmap_get_range(regmap, 0); |
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if (!range) { |
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dev_err(dev, "Failed to get regmap range\n"); |
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return -ENOMEM; |
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} |
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pdata->phy_intf = range + args.args[0]; |
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/*
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* Sadly, the Altera DT bindings don't have SoC-specific compatibles, |
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* so we have to guesstimate which SoC we are running on from the |
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* DWMAC version. Luckily, Altera at least updated the DWMAC with |
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* each SoC. |
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*/ |
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if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a")) |
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pdata->type = DWMAC_SOCFPGA_GEN5; |
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if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a")) |
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pdata->type = DWMAC_SOCFPGA_ARRIA10; |
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if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a")) |
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pdata->type = DWMAC_SOCFPGA_STRATIX10; |
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return designware_eth_ofdata_to_platdata(dev); |
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} |
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static int dwmac_socfpga_probe(struct udevice *dev) |
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{ |
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struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); |
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struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; |
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struct reset_ctl_bulk reset_bulk; |
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int ret; |
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u8 modereg; |
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if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { |
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switch (edata->phy_interface) { |
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case PHY_INTERFACE_MODE_MII: |
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case PHY_INTERFACE_MODE_GMII: |
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; |
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break; |
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case PHY_INTERFACE_MODE_RMII: |
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; |
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break; |
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case PHY_INTERFACE_MODE_RGMII: |
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modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; |
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break; |
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default: |
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dev_err(dev, "Unsupported PHY mode\n"); |
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return -EINVAL; |
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} |
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ret = reset_get_bulk(dev, &reset_bulk); |
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if (ret) { |
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dev_err(dev, "Failed to get reset: %d\n", ret); |
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return ret; |
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} |
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reset_assert_bulk(&reset_bulk); |
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clrsetbits_le32(pdata->phy_intf, |
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SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, |
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modereg); |
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reset_release_bulk(&reset_bulk); |
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} |
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return designware_eth_probe(dev); |
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} |
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static const struct udevice_id dwmac_socfpga_ids[] = { |
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{ .compatible = "altr,socfpga-stmmac" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(dwmac_socfpga) = { |
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.name = "dwmac_socfpga", |
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.id = UCLASS_ETH, |
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.of_match = dwmac_socfpga_ids, |
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.ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata, |
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.probe = dwmac_socfpga_probe, |
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.ops = &designware_eth_ops, |
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.priv_auto_alloc_size = sizeof(struct dw_eth_dev), |
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.platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata), |
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.flags = DM_FLAG_ALLOC_PRIV_DMA, |
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}; |
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