This patch adds a common config header file for all the Keystone II EVM platforms. It combines a lot of general definitions in one file. The common header included in the EVM should be specific configuration header. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>master
Hao Zhang
11 years ago
committed by
Tom Rini
parent
8dfc15f56c
commit
2221cd12cd
@ -0,0 +1,275 @@ |
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/*
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* Common configuration header file for all Keystone II EVM platforms |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_KS2_EVM_H |
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#define __CONFIG_KS2_EVM_H |
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#define CONFIG_SOC_KEYSTONE |
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/* U-Boot Build Configuration */ |
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ |
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#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_SYS_THUMB_BUILD |
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/* SoC Configuration */ |
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#define CONFIG_ARMV7 |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_SYS_ARCH_TIMER |
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#define CONFIG_SYS_HZ 1000 |
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#define CONFIG_SYS_TEXT_BASE 0x0c001000 |
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#define CONFIG_SPL_TARGET "u-boot-spi.gph" |
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#define CONFIG_SYS_DCACHE_OFF |
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/* Memory Configuration */ |
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#define CONFIG_NR_DRAM_BANKS 2 |
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 |
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#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 |
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#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ |
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#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ |
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ |
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GENERATED_GBL_DATA_SIZE) |
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/* SPL SPI Loader Configuration */ |
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#define CONFIG_SPL_PAD_TO 65536 |
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) |
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#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ |
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CONFIG_SPL_MAX_SIZE) |
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#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) |
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
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CONFIG_SPL_BSS_MAX_SIZE) |
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#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) |
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#define CONFIG_SPL_STACK_SIZE (8 * 1024) |
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#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ |
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CONFIG_SYS_SPL_MALLOC_SIZE + \
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CONFIG_SPL_STACK_SIZE - 4) |
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#define CONFIG_SPL_LIBCOMMON_SUPPORT |
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#define CONFIG_SPL_LIBGENERIC_SUPPORT |
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#define CONFIG_SPL_SERIAL_SUPPORT |
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#define CONFIG_SPL_SPI_FLASH_SUPPORT |
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#define CONFIG_SPL_SPI_SUPPORT |
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#define CONFIG_SPL_BOARD_INIT |
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#define CONFIG_SPL_SPI_LOAD |
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#define CONFIG_SPL_SPI_BUS 0 |
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#define CONFIG_SPL_SPI_CS 0 |
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#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
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#define CONFIG_SPL_FRAMEWORK |
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/* UART Configuration */ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_MEM32 |
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#define CONFIG_SYS_NS16550_REG_SIZE -4 |
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#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE |
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#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE |
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#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_BAUDRATE 115200 |
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/* SPI Configuration */ |
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#define CONFIG_SPI |
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#define CONFIG_SPI_FLASH |
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#define CONFIG_SPI_FLASH_STMICRO |
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#define CONFIG_DAVINCI_SPI |
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#define CONFIG_CMD_SPI |
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#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) |
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#define CONFIG_SF_DEFAULT_SPEED 30000000 |
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED |
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#define CONFIG_SYS_SPI0 |
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#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE |
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#define CONFIG_SYS_SPI0_NUM_CS 4 |
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#define CONFIG_SYS_SPI1 |
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#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE |
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#define CONFIG_SYS_SPI1_NUM_CS 4 |
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#define CONFIG_SYS_SPI2 |
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#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE |
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#define CONFIG_SYS_SPI2_NUM_CS 4 |
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/* Network Configuration */ |
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#define CONFIG_MII |
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#define CONFIG_BOOTP_DEFAULT |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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#define CONFIG_NET_RETRY_COUNT 32 |
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#define CONFIG_NET_MULTI |
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#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 |
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#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 |
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#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 |
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#define CONFIG_SYS_SGMII_RATESCALE 2 |
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/* AEMIF */ |
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#define CONFIG_TI_AEMIF |
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#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE |
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/* I2C Configuration */ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_DAVINCI |
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 |
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ |
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#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 |
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ |
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#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 |
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ |
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#define I2C_BUS_MAX 3 |
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/* EEPROM definitions */ |
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#define CONFIG_SYS_I2C_MULTI_EEPROMS |
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 |
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 |
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#define CONFIG_ENV_EEPROM_IS_ON_I2C |
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/* NAND Configuration */ |
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#define CONFIG_NAND_DAVINCI |
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#define CONFIG_KEYSTONE_RBL_NAND |
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#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET |
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#define CONFIG_SYS_NAND_MASK_CLE 0x4000 |
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#define CONFIG_SYS_NAND_MASK_ALE 0x2000 |
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#define CONFIG_SYS_NAND_CS 2 |
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#define CONFIG_SYS_NAND_USE_FLASH_BBT |
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
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#define CONFIG_SYS_NAND_LARGEPAGE |
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#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
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#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE |
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#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_OFFSET 0x100000 |
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#define CONFIG_MTD_PARTITIONS |
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#define CONFIG_MTD_DEVICE |
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#define CONFIG_RBTREE |
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#define CONFIG_LZO |
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#define MTDIDS_DEFAULT "nand0=davinci_nand.0" |
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#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ |
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"1024k(bootloader)ro,512k(params)ro," \
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"-(ubifs)" |
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/* U-Boot command configuration */ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_SAVES |
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#define CONFIG_CMD_MTDPARTS |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_UBI |
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#define CONFIG_CMD_UBIFS |
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#define CONFIG_CMD_SF |
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#define CONFIG_CMD_EEPROM |
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/* U-Boot general configuration */ |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_SYS_CBSIZE 1024 |
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#define CONFIG_SYS_PBSIZE 2048 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_CRC32_VERIFY |
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#define CONFIG_MX_CYCLIC |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_VERSION_VARIABLE |
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#define CONFIG_TIMESTAMP |
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/* EDMA3 */ |
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#define CONFIG_TI_EDMA3 |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_BOOTFILE "uImage" |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"boot=ramfs\0" \
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"tftp_root=/\0" \
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"nfs_root=/export\0" \
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"mem_lpae=1\0" \
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"mem_reserve=512M\0" \
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"addr_fdt=0x87000000\0" \
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"addr_kern=0x88000000\0" \
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KS2_ADDR_MON \
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"addr_uboot=0x87000000\0" \
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"addr_fs=0x82000000\0" \
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"addr_ubi=0x82000000\0" \
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"addr_secdb_key=0xc000000\0" \
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"fdt_high=0xffffffff\0" \
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KS2_FDT_NAME \
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"name_fs=arago-console-image.cpio.gz\0" \
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"name_kern=uImage\0" \
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KS2_NAME_MON \
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NAME_UBOOT \
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NAME_UBI \
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"run_mon=mon_install ${addr_mon}\0" \
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"run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
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"init_net=run args_all args_net\0" \
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"init_ubi=run args_all args_ubi; " \
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"ubi part ubifs; ubifsmount boot;" \
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"ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
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"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
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"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
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"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
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"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
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"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
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"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
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"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
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"burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
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"sf write ${addr_uboot} 0 ${filesize}\0" \
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"burn_uboot_nand=nand erase 0 0x100000; " \
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"nand write ${addr_uboot} 0 ${filesize}\0" \
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"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
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KS2_ARGS_UBI \
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"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
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"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
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"${nfs_options} ip=dhcp\0" \
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"nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
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"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
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"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
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"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
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"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
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"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
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"burn_ubi=nand erase.part ubifs; " \
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"nand write ${addr_ubi} ubifs ${filesize}\0" \
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"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
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"args_ramfs=setenv bootargs ${bootargs} " \
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"rdinit=/sbin/init rw root=/dev/ram0 " \
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"initrd=0x802000000,9M\0" \
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"no_post=1\0" \
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"mtdparts=mtdparts=davinci_nand.0:" \
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"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" |
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#define CONFIG_BOOTCOMMAND \ |
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"run init_${boot} get_fdt_${boot} get_mon_${boot} " \
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"get_kern_${boot} run_mon run_kern" |
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#define CONFIG_BOOTARGS \ |
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/* Linux interfacing */ |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_OF_LIBFDT 1 |
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#define CONFIG_OF_BOARD_SETUP |
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#define CONFIG_SYS_BARGSIZE 1024 |
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) |
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#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) |
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#define CONFIG_SUPPORT_RAW_INITRD |
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/* we may include files below only after all above definitions */ |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/clock.h> |
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#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) |
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/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
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which is NOT applicable for DDR ECC test */ |
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#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ |
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#endif /* __CONFIG_KS2_EVM_H */ |
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