From 226502e01bc7ffa79dde28604075949f8f816cfc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 16 Sep 2011 12:54:58 +0200 Subject: [PATCH] ppc4xx: Flush dcache after DDR2 autocalibration with caches on Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 95df1d9..4a2f337 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -657,6 +657,13 @@ phys_size_t initdram(int board_type) #endif /* + * Flush the dcache before removing the TLB with caches + * enabled. Otherwise this might lead to problems later on, + * e.g. while booting Linux (as seen on ICON-440SPe). + */ + flush_dcache(); + + /* * Now after initialization (auto-calibration and ECC generation) * remove the TLB entries with caches enabled and program again with * desired cache functionality