Tom Rini
9 years ago
commit
2311335d4c
@ -0,0 +1,50 @@ |
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/*
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* Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include "ehci.h" |
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/*
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* Even though here we don't explicitly use "struct ehci_ctrl" |
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* ehci_register() expects it to be the first thing that resides in |
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* device's private data. |
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*/ |
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struct generic_ehci { |
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struct ehci_ctrl ctrl; |
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}; |
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static int ehci_usb_probe(struct udevice *dev) |
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{ |
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struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev); |
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struct ehci_hcor *hcor; |
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hcor = (struct ehci_hcor *)((uintptr_t)hccr + |
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HC_LENGTH(ehci_readl(&hccr->cr_capbase))); |
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return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); |
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} |
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static int ehci_usb_remove(struct udevice *dev) |
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{ |
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return ehci_deregister(dev); |
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} |
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static const struct udevice_id ehci_usb_ids[] = { |
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{ .compatible = "generic-ehci" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(ehci_generic) = { |
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.name = "ehci_generic", |
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.id = UCLASS_USB, |
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.of_match = ehci_usb_ids, |
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.probe = ehci_usb_probe, |
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.remove = ehci_usb_remove, |
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.ops = &ehci_usb_ops, |
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.priv_auto_alloc_size = sizeof(struct generic_ehci), |
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.flags = DM_FLAG_ALLOC_PRIV_DMA, |
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}; |
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@ -0,0 +1,126 @@ |
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/*
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* Copyright 2015 Xilinx, Inc. |
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* |
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* Zynq USB HOST xHCI Controller |
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* |
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* Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com> |
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* |
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* This file was reused from Freescale USB xHCI |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <usb.h> |
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#include <asm-generic/errno.h> |
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#include <asm/arch-zynqmp/hardware.h> |
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#include <linux/compat.h> |
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#include <linux/usb/dwc3.h> |
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#include "xhci.h" |
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/* Declare global data pointer */ |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Default to the ZYNQMP XHCI defines */ |
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 |
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC |
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#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) |
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#define USB3_PHY_RX_POWERON BIT(14) |
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#define USB3_PHY_TX_POWERON BIT(15) |
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) |
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14 |
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 |
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|
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/* USBOTGSS_WRAPPER definitions */ |
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#define USBOTGSS_WRAPRESET BIT(17) |
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#define USBOTGSS_DMADISABLE BIT(16) |
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#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) |
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#define USBOTGSS_STANDBYMODE_SMRT BIT(5) |
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) |
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#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) |
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#define USBOTGSS_IDLEMODE_SMRT BIT(3) |
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) |
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/* USBOTGSS_IRQENABLE_SET_0 bit */ |
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#define USBOTGSS_COREIRQ_EN BIT(1) |
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/* USBOTGSS_IRQENABLE_SET_1 bits */ |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) |
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#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) |
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) |
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struct zynqmp_xhci { |
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struct xhci_hccr *hcd; |
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struct dwc3 *dwc3_reg; |
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}; |
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static struct zynqmp_xhci zynqmp_xhci; |
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unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; |
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static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) |
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{ |
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int ret = 0; |
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ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); |
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if (ret) { |
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debug("%s:failed to initialize core\n", __func__); |
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return ret; |
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} |
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/* We are hard-coding DWC3 core to Host Mode */ |
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dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
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return ret; |
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} |
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
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{ |
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struct zynqmp_xhci *ctx = &zynqmp_xhci; |
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int ret = 0; |
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uint32_t hclen; |
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if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) |
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return -EINVAL; |
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ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; |
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ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET); |
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ret = board_usb_init(index, USB_INIT_HOST); |
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if (ret != 0) { |
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puts("Failed to initialize board for USB\n"); |
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return ret; |
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} |
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ret = zynqmp_xhci_core_init(ctx); |
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if (ret < 0) { |
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puts("Failed to initialize xhci\n"); |
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return ret; |
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} |
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*hccr = (struct xhci_hccr *)ctx->hcd; |
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hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)); |
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*hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen); |
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debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n", |
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*hccr, *hcor, hclen); |
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return ret; |
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} |
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void xhci_hcd_stop(int index) |
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{ |
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/*
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* Currently zynqmp socs do not support PHY shutdown from |
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* sw. But this support may be added in future socs. |
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*/ |
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return; |
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} |
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