Matthias Fuchs
9 years ago
committed by
Tom Rini
parent
b5e7c84f72
commit
2404124c47
@ -1,12 +0,0 @@ |
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if TARGET_CMS700 |
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config SYS_BOARD |
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default "cms700" |
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config SYS_VENDOR |
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default "esd" |
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config SYS_CONFIG_NAME |
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default "CMS700" |
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endif |
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@ -1,6 +0,0 @@ |
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CMS700 BOARD |
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
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S: Maintained |
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F: board/esd/cms700/ |
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F: include/configs/CMS700.h |
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F: configs/CMS700_defconfig |
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@ -1,16 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Objects for Xilinx JTAG programming (CPLD)
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CPLD = ../common/xilinx_jtag/lenval.o \
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../common/xilinx_jtag/micro.o \
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../common/xilinx_jtag/ports.o
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obj-y = cms700.o flash.o \
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../common/misc.o \
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$(CPLD) \
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../common/esd405ep_nand.o \
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@ -1,192 +0,0 @@ |
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/*
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* (C) Copyright 2005-2007 |
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <command.h> |
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#include <malloc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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extern void lxt971_no_sleep(void); |
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int board_early_init_f (void) |
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{ |
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
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*/ |
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
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mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ |
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
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*/ |
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mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
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/*
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* Reset CPLD via GPIO12 (CS3) pin |
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*/ |
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET); |
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udelay(1000); /* wait 1ms */ |
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET); |
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udelay(1000); /* wait 1ms */ |
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return 0; |
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} |
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int misc_init_r (void) |
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{ |
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/* adjust flash start and offset */ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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/*
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* Setup and enable EEPROM write protection |
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*/ |
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); |
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return (0); |
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} |
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/*
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* Check Board Identity: |
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*/ |
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#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000) |
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int checkboard (void) |
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{ |
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char str[64]; |
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int flashcnt; |
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int delay; |
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puts ("Board: "); |
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if (getenv_f("serial#", str, sizeof(str)) == -1) { |
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puts ("### No HW ID - assuming CMS700"); |
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} else { |
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puts(str); |
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} |
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printf(" (PLD-Version=%02d)\n", |
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in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001))); |
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/*
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* Flash LEDs |
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*/ |
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for (flashcnt = 0; flashcnt < 3; flashcnt++) { |
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out_8((void *)LED_REG, 0x00); /* LEDs off */ |
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for (delay = 0; delay < 100; delay++) |
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udelay(1000); |
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out_8((void *)LED_REG, 0x0f); /* LEDs on */ |
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for (delay = 0; delay < 50; delay++) |
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udelay(1000); |
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} |
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out_8((void *)LED_REG, 0x70); |
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return 0; |
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} |
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/* ------------------------------------------------------------------------- */ |
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#if defined(CONFIG_SYS_EEPROM_WREN) |
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state |
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* 0: disable write |
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* 1: enable write |
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* Returns: -1: wrong device address |
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* 0: dis-/en- able done |
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* 0/1: current state if <state> was -1. |
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*/ |
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int eeprom_write_enable (unsigned dev_addr, int state) |
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{ |
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if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { |
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return -1; |
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} else { |
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switch (state) { |
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case 1: |
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/* Enable write access, clear bit GPIO_SINT2. */ |
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); |
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state = 0; |
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break; |
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case 0: |
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/* Disable write access, set bit GPIO_SINT2. */ |
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); |
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state = 0; |
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break; |
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default: |
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/* Read current status back. */ |
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state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); |
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break; |
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} |
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} |
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return state; |
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} |
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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int query = argc == 1; |
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int state = 0; |
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if (query) { |
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/* Query write access state. */ |
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state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); |
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if (state < 0) { |
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puts ("Query of write access state failed.\n"); |
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} else { |
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printf ("Write access for device 0x%0x is %sabled.\n", |
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CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); |
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state = 0; |
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} |
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} else { |
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if ('0' == argv[1][0]) { |
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/* Disable write access. */ |
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state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); |
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} else { |
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/* Enable write access. */ |
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state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); |
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} |
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if (state < 0) { |
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puts ("Setup of write access state failed.\n"); |
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} |
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} |
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return state; |
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} |
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, |
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"Enable / disable / query EEPROM write access", |
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"" |
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); |
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#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ |
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/* ------------------------------------------------------------------------- */ |
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void reset_phy(void) |
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{ |
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#ifdef CONFIG_LXT971_NO_SLEEP |
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/*
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* Disable sleep mode in LXT971 |
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*/ |
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lxt971_no_sleep(); |
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#endif |
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} |
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@ -1,85 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/processor.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0; |
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int i; |
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uint pbcr; |
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unsigned long base_b0; |
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int size_val = 0; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0<<20); |
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} |
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/* Setup offsets */ |
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flash_get_offsets (-size_b0, &flash_info[0]); |
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/* Re-do sizing to get full correct info */ |
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mtdcr(EBC0_CFGADDR, PB0CR); |
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pbcr = mfdcr(EBC0_CFGDATA); |
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mtdcr(EBC0_CFGADDR, PB0CR); |
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base_b0 = -size_b0; |
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switch (size_b0) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
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case 4 << 20: |
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size_val = 2; |
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break; |
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case 8 << 20: |
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size_val = 3; |
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break; |
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case 16 << 20: |
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size_val = 4; |
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break; |
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} |
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); |
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mtdcr(EBC0_CFGDATA, pbcr); |
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-CONFIG_SYS_MONITOR_LEN, |
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0xffffffff, |
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&flash_info[0]); |
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flash_info[0].size = size_b0; |
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return (size_b0); |
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} |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_4xx=y |
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CONFIG_TARGET_CMS700=y |
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@ -1,308 +0,0 @@ |
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/*
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* (C) Copyright 2005 |
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* CMS700.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
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#define CONFIG_VOM405 1 /* ...on a VOM405 board */ |
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#define CONFIG_SYS_TEXT_BASE 0xFFFC8000 |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
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#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
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#define CONFIG_BAUDRATE 9600 |
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
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#undef CONFIG_BOOTARGS |
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#undef CONFIG_BOOTCOMMAND |
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#define CONFIG_PREBOOT /* enable preboot variable */ |
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#define CONFIG_PPC4xx_EMAC |
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#undef CONFIG_HAS_ETH1 |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_PHY_ADDR 0 /* PHY address */ |
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_SUBNETMASK |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_DNS |
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#define CONFIG_BOOTP_DNS2 |
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#define CONFIG_BOOTP_SEND_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_BSP |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_EEPROM |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
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#undef CONFIG_PRAM /* no "protected RAM" */ |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE 1 |
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#define CONFIG_SYS_NS16550_CLK get_serial_clock() |
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
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#define CONFIG_SYS_BASE_BAUD 691200 |
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/* The following table includes the supported baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 } |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
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/*-----------------------------------------------------------------------
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* RTC stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#define CONFIG_RTC_DS1337 |
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
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/*-----------------------------------------------------------------------
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* NAND-FLASH stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
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#define NAND_BIG_DELAY_US 25 |
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#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ |
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#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ |
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#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ |
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#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ |
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#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
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#define CONFIG_SYS_NAND_QUIET 1 |
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
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#define CONFIG_SYS_NAND_MAX_ECCPOS 48 |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
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#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
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#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
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/*
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* The following defines are added for buggy IOP480 byte interface. |
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* All other boards should use the standard values (CPCI405 etc.) |
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*/ |
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#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
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#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
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#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
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#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) |
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# define CONFIG_SYS_RAMBOOT 1 |
||||
#else |
||||
# undef CONFIG_SYS_RAMBOOT |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
||||
#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ |
||||
/* total size of a CAT24WC16 is 2048 bytes */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC16) for environment |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_PPC4XX |
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
#define CONFIG_SYS_EEPROM_WREN 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
#define CONFIG_SYS_PLD_BASE 0xf0000000 |
||||
#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ |
||||
#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
||||
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff |
||||
*/ |
||||
#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 |
||||
|
||||
/* FPGA program pin configuration */ |
||||
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ |
||||
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
||||
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific) |
||||
* |
||||
* GPIO0[0] - External Bus Controller BLAST output |
||||
* GPIO0[1-9] - Instruction trace outputs -> GPIO |
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||
* GPIO0[28-29] - UART1 data signal input/output |
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
||||
*/ |
||||
/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */ |
||||
/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ |
||||
/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ |
||||
/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ |
||||
#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ |
||||
#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ |
||||
#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ |
||||
|
||||
#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ |
||||
#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ |
||||
|
||||
/*
|
||||
* Default speed selection (cpu_plb_opb_ebc) in mhz. |
||||
* This value will be set if iic boot eprom is disabled. |
||||
*/ |
||||
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue