Add a driver for the Xilinx LogiCORE DisplayPort IP core, which is a pure DP transmitter core for Xiling FPGA (no display capabilities). Signed-off-by: Mario Six <mario.six@gdsys.cc>lime2-spi
Mario Six
6 years ago
committed by
Anatolij Gustschin
parent
77d512ff18
commit
25a9f9747a
@ -0,0 +1,341 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* logicore_dp_dpcd.h |
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* |
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* DPCD interface definition for XILINX LogiCore DisplayPort v6.1 |
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* based on Xilinx dp_v3_1 driver sources |
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* |
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* (C) Copyright 2016 |
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
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*/ |
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#ifndef __GDSYS_LOGICORE_DP_DPCD_H__ |
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#define __GDSYS_LOGICORE_DP_DPCD_H__ |
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/* receiver capability field */ |
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#define DPCD_REV 0x00000 |
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#define DPCD_MAX_LINK_RATE 0x00001 |
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#define DPCD_MAX_LANE_COUNT 0x00002 |
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#define DPCD_MAX_DOWNSPREAD 0x00003 |
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#define DPCD_NORP_PWR_V_CAP 0x00004 |
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#define DPCD_DOWNSP_PRESENT 0x00005 |
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#define DPCD_ML_CH_CODING_CAP 0x00006 |
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#define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007 |
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#define DPCD_RX_PORT0_CAP_0 0x00008 |
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#define DPCD_RX_PORT0_CAP_1 0x00009 |
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#define DPCD_RX_PORT1_CAP_0 0x0000A |
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#define DPCD_RX_PORT1_CAP_1 0x0000B |
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#define DPCD_I2C_SPEED_CTL_CAP 0x0000C |
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#define DPCD_EDP_CFG_CAP 0x0000D |
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#define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E |
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#define DPCD_ADAPTER_CAP 0x0000F |
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#define DPCD_FAUX_CAP 0x00020 |
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#define DPCD_MSTM_CAP 0x00021 |
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#define DPCD_NUM_AUDIO_EPS 0x00022 |
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#define DPCD_AV_GRANULARITY 0x00023 |
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#define DPCD_AUD_DEC_LAT_7_0 0x00024 |
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#define DPCD_AUD_DEC_LAT_15_8 0x00025 |
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#define DPCD_AUD_PP_LAT_7_0 0x00026 |
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#define DPCD_AUD_PP_LAT_15_8 0x00027 |
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#define DPCD_VID_INTER_LAT 0x00028 |
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#define DPCD_VID_PROG_LAT 0x00029 |
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#define DPCD_REP_LAT 0x0002A |
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#define DPCD_AUD_DEL_INS_7_0 0x0002B |
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#define DPCD_AUD_DEL_INS_15_8 0x0002C |
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#define DPCD_AUD_DEL_INS_23_16 0x0002D |
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#define DPCD_GUID 0x00030 |
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#define DPCD_RX_GTC_VALUE_7_0 0x00054 |
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#define DPCD_RX_GTC_VALUE_15_8 0x00055 |
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#define DPCD_RX_GTC_VALUE_23_16 0x00056 |
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#define DPCD_RX_GTC_VALUE_31_24 0x00057 |
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#define DPCD_RX_GTC_MSTR_REQ 0x00058 |
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#define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059 |
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#define DPCD_DOWNSP_0_CAP 0x00080 |
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#define DPCD_DOWNSP_1_CAP 0x00081 |
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#define DPCD_DOWNSP_2_CAP 0x00082 |
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#define DPCD_DOWNSP_3_CAP 0x00083 |
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#define DPCD_DOWNSP_0_DET_CAP 0x00080 |
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#define DPCD_DOWNSP_1_DET_CAP 0x00084 |
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#define DPCD_DOWNSP_2_DET_CAP 0x00088 |
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#define DPCD_DOWNSP_3_DET_CAP 0x0008C |
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/* link configuration field */ |
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#define DPCD_LINK_BW_SET 0x00100 |
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#define DPCD_LANE_COUNT_SET 0x00101 |
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#define DPCD_TP_SET 0x00102 |
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#define DPCD_TRAINING_LANE0_SET 0x00103 |
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#define DPCD_TRAINING_LANE1_SET 0x00104 |
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#define DPCD_TRAINING_LANE2_SET 0x00105 |
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#define DPCD_TRAINING_LANE3_SET 0x00106 |
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#define DPCD_DOWNSPREAD_CTRL 0x00107 |
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#define DPCD_ML_CH_CODING_SET 0x00108 |
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#define DPCD_I2C_SPEED_CTL_SET 0x00109 |
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#define DPCD_EDP_CFG_SET 0x0010A |
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#define DPCD_LINK_QUAL_LANE0_SET 0x0010B |
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#define DPCD_LINK_QUAL_LANE1_SET 0x0010C |
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#define DPCD_LINK_QUAL_LANE2_SET 0x0010D |
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#define DPCD_LINK_QUAL_LANE3_SET 0x0010E |
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#define DPCD_TRAINING_LANE0_1_SET2 0x0010F |
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#define DPCD_TRAINING_LANE2_3_SET2 0x00110 |
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#define DPCD_MSTM_CTRL 0x00111 |
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#define DPCD_AUDIO_DELAY_7_0 0x00112 |
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#define DPCD_AUDIO_DELAY_15_8 0x00113 |
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#define DPCD_AUDIO_DELAY_23_6 0x00114 |
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#define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118 |
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#define DPCD_FAUX_MODE_CTRL 0x00120 |
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#define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121 |
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#define DPCD_BACK_CH_STATUS 0x00122 |
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#define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123 |
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#define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125 |
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#define DPCD_TX_GTC_VALUE_7_0 0x00154 |
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#define DPCD_TX_GTC_VALUE_15_8 0x00155 |
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#define DPCD_TX_GTC_VALUE_23_16 0x00156 |
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#define DPCD_TX_GTC_VALUE_31_24 0x00157 |
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#define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158 |
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#define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159 |
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#define DPCD_ADAPTER_CTRL 0x001A0 |
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#define DPCD_BRANCH_DEVICE_CTRL 0x001A1 |
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#define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0 |
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#define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1 |
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#define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2 |
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/* link/sink status field */ |
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#define DPCD_SINK_COUNT 0x00200 |
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#define DPCD_DEVICE_SERVICE_IRQ 0x00201 |
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#define DPCD_STATUS_LANE_0_1 0x00202 |
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#define DPCD_STATUS_LANE_2_3 0x00203 |
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#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204 |
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#define DPCD_SINK_STATUS 0x00205 |
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#define DPCD_ADJ_REQ_LANE_0_1 0x00206 |
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#define DPCD_ADJ_REQ_LANE_2_3 0x00207 |
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#define DPCD_TRAINING_SCORE_LANE_0 0x00208 |
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#define DPCD_TRAINING_SCORE_LANE_1 0x00209 |
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#define DPCD_TRAINING_SCORE_LANE_2 0x0020A |
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#define DPCD_TRAINING_SCORE_LANE_3 0x0020B |
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#define DPCD_ADJ_REQ_PC2 0x0020C |
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#define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D |
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#define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210 |
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#define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212 |
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#define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214 |
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#define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216 |
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/* automated testing sub-field */ |
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#define DPCD_FAUX_FORWARD_CH_STATUS 0x00280 |
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#define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281 |
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#define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282 |
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#define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0 |
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#define DPCD_VC_PAYLOAD_ID_SLOT(slotnum) \ |
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(DPCD_PAYLOAD_TABLE_UPDATE_STATUS + slotnum) |
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/* sink control field */ |
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#define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 |
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/* sideband message buffers */ |
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#define DPCD_DOWN_REQ 0x01000 |
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#define DPCD_UP_REP 0x01200 |
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#define DPCD_DOWN_REP 0x01400 |
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#define DPCD_UP_REQ 0x01600 |
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/* event status indicator field */ |
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#define DPCD_SINK_COUNT_ESI 0x02002 |
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#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003 |
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#define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004 |
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#define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005 |
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#define DPCD_SINK_LANE0_1_STATUS 0x0200C |
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#define DPCD_SINK_LANE2_3_STATUS 0x0200D |
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#define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E |
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#define DPCD_SINK_STATUS_ESI 0x0200F |
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/*
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* field addresses and sizes. |
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*/ |
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#define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV |
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#define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100 |
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#define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET |
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#define DPCD_LINK_CFG_FIELD_SIZE 0x100 |
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#define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT |
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#define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17 |
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/* 0x00000: DPCD_REV */ |
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#define DPCD_REV_MNR_MASK 0x0F |
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#define DPCD_REV_MJR_MASK 0xF0 |
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#define DPCD_REV_MJR_SHIFT 4 |
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/* 0x00001: MAX_LINK_RATE */ |
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#define DPCD_MAX_LINK_RATE_162GBPS 0x06 |
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#define DPCD_MAX_LINK_RATE_270GBPS 0x0A |
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#define DPCD_MAX_LINK_RATE_540GBPS 0x14 |
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/* 0x00002: MAX_LANE_COUNT */ |
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#define DPCD_MAX_LANE_COUNT_MASK 0x1F |
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#define DPCD_MAX_LANE_COUNT_1 0x01 |
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#define DPCD_MAX_LANE_COUNT_2 0x02 |
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#define DPCD_MAX_LANE_COUNT_4 0x04 |
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#define DPCD_TPS3_SUPPORT_MASK 0x40 |
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#define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 |
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/* 0x00003: MAX_DOWNSPREAD */ |
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#define DPCD_MAX_DOWNSPREAD_MASK 0x01 |
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#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40 |
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/* 0x00005: DOWNSP_PRESENT */ |
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#define DPCD_DOWNSP_PRESENT_MASK 0x01 |
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#define DPCD_DOWNSP_TYPE_MASK 0x06 |
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#define DPCD_DOWNSP_TYPE_SHIFT 1 |
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#define DPCD_DOWNSP_TYPE_DP 0x0 |
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#define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1 |
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#define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2 |
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#define DPCD_DOWNSP_TYPE_OTHERS 0x3 |
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#define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08 |
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#define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10 |
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/* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */ |
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#define DPCD_ML_CH_CODING_MASK 0x01 |
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/* 0x00007: DOWNSP_COUNT_MSA_OUI */ |
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#define DPCD_DOWNSP_COUNT_MASK 0x0F |
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#define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40 |
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#define DPCD_OUI_SUPPORT_MASK 0x80 |
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/* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */ |
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#define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02 |
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#define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04 |
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/* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */ |
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#define DPCD_I2C_SPEED_CTL_NONE 0x00 |
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#define DPCD_I2C_SPEED_CTL_1KBIPS 0x01 |
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#define DPCD_I2C_SPEED_CTL_5KBIPS 0x02 |
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#define DPCD_I2C_SPEED_CTL_10KBIPS 0x04 |
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#define DPCD_I2C_SPEED_CTL_100KBIPS 0x08 |
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#define DPCD_I2C_SPEED_CTL_400KBIPS 0x10 |
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#define DPCD_I2C_SPEED_CTL_1MBIPS 0x20 |
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/* 0x0000E: TRAIN_AUX_RD_INTERVAL */ |
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#define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00 |
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#define DPCD_TRAIN_AUX_RD_INT_4MS 0x01 |
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#define DPCD_TRAIN_AUX_RD_INT_8MS 0x02 |
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#define DPCD_TRAIN_AUX_RD_INT_12MS 0x03 |
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#define DPCD_TRAIN_AUX_RD_INT_16MS 0x04 |
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/* 0x00020: DPCD_FAUX_CAP */ |
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#define DPCD_FAUX_CAP_MASK 0x01 |
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/* 0x00021: MSTM_CAP */ |
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#define DPCD_MST_CAP_MASK 0x01 |
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/* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */ |
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#define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07 |
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#define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0 |
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#define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1 |
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#define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2 |
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#define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3 |
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#define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4 |
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#define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5 |
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#define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5 |
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#define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7 |
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/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ |
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#define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03 |
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#define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0 |
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#define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1 |
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#define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2 |
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#define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3 |
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/* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */ |
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#define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01 |
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#define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02 |
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#define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04 |
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/* link configuration field masks, shifts, and register values */ |
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/* 0x00100: DPCD_LINK_BW_SET */ |
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#define DPCD_LINK_BW_SET_162GBPS 0x06 |
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#define DPCD_LINK_BW_SET_270GBPS 0x0A |
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#define DPCD_LINK_BW_SET_540GBPS 0x14 |
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/* 0x00101: LANE_COUNT_SET */ |
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#define DPCD_LANE_COUNT_SET_MASK 0x1F |
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#define DPCD_LANE_COUNT_SET_1 0x01 |
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#define DPCD_LANE_COUNT_SET_2 0x02 |
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#define DPCD_LANE_COUNT_SET_4 0x04 |
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#define DPCD_ENHANCED_FRAME_EN_MASK 0x80 |
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/* 0x00102: TP_SET */ |
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#define DPCD_TP_SEL_MASK 0x03 |
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#define DPCD_TP_SEL_OFF 0x0 |
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#define DPCD_TP_SEL_TP1 0x1 |
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#define DPCD_TP_SEL_TP2 0x2 |
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#define DPCD_TP_SEL_TP3 0x3 |
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#define DPCD_TP_SET_LQP_MASK 0x06 |
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#define DPCD_TP_SET_LQP_SHIFT 2 |
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#define DPCD_TP_SET_LQP_OFF 0x0 |
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#define DPCD_TP_SET_LQP_D102_TEST 0x1 |
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#define DPCD_TP_SET_LQP_SER_MES 0x2 |
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#define DPCD_TP_SET_LQP_PRBS7 0x3 |
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#define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10 |
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#define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 |
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#define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0 |
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#define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6 |
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#define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0 |
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#define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1 |
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#define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2 |
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/* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */ |
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#define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03 |
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#define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 |
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#define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18 |
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#define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 |
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#define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 |
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/* 0x00107: DOWNSPREAD_CTRL */ |
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#define DPCD_SPREAD_AMP_MASK 0x10 |
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#define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80 |
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/* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */ |
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/* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */ |
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/* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */ |
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#define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03 |
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#define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04 |
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#define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30 |
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#define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4 |
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#define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40 |
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/* 0x00111: MSTM_CTRL */ |
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#define DPCD_MST_EN_MASK 0x01 |
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#define DPCD_UP_REQ_EN_MASK 0x02 |
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#define DPCD_UP_IS_SRC_MASK 0x03 |
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/* link/sink status field masks, shifts, and register values */ |
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/* 0x00200: SINK_COUNT */ |
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#define DPCD_SINK_COUNT_LOW_MASK 0x3F |
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#define DPCD_SINK_CP_READY_MASK 0x40 |
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#define DPCD_SINK_COUNT_HIGH_MASK 0x80 |
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#define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1 |
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/* 0x00202: STATUS_LANE_0_1 */ |
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#define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 |
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#define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 |
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#define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 |
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#define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 |
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#define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 |
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#define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 |
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/* 0x00202: STATUS_LANE_2_3 */ |
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#define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01 |
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#define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02 |
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#define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04 |
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#define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10 |
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#define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20 |
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#define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40 |
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/* 0x00204: LANE_ALIGN_STATUS_UPDATED */ |
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#define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \ |
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0x01 |
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#define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \ |
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0x40 |
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#define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \ |
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0x80 |
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/* 0x00205: SINK_STATUS */ |
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#define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01 |
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#define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02 |
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/* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */ |
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#define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 |
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#define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C |
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#define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 |
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#define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 |
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#define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 |
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#define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 |
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#define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 |
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/* 0x0020C: ADJ_REQ_PC2 */ |
||||
#define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03 |
||||
#define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C |
||||
#define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2 |
||||
#define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30 |
||||
#define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4 |
||||
#define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0 |
||||
#define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6 |
||||
|
||||
#endif /* __GDSYS_LOGICORE_DP_DPCD_H__ */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,54 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* logicore_dp_tx.h |
||||
* |
||||
* Driver for XILINX LogiCore DisplayPort v6.1 TX (Source) |
||||
* |
||||
* (C) Copyright 2016 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
||||
*/ |
||||
|
||||
#ifndef __GDSYS_LOGICORE_DP_TX_H__ |
||||
#define __GDSYS_LOGICORE_DP_TX_H__ |
||||
|
||||
/*
|
||||
* struct logicore_dp_tx_msa - Main Stream Attributes (MSA) |
||||
* @pixel_clock_hz: The pixel clock of the stream (in Hz) |
||||
* @bits_per_color: Number of bits per color component |
||||
* @h_active: Horizontal active resolution (pixels) |
||||
* @h_start: Horizontal blank start (in pixels) |
||||
* @h_sync_polarity: Horizontal sync polarity |
||||
* (0 = negative | 1 = positive) |
||||
* @h_sync_width: Horizontal sync width (pixels) |
||||
* @h_total: Horizontal total (pixels) |
||||
* @v_active: Vertical active resolution (lines) |
||||
* @v_start: Vertical blank start (in lines). |
||||
* @v_sync_polarity: Vertical sync polarity |
||||
* (0 = negative | 1 = positive) |
||||
* @v_sync_width: Vertical sync width (lines) |
||||
* @v_total: Vertical total (lines) |
||||
* @override_user_pixel_width: If true, the value stored for user_pixel_width |
||||
* will be used as the pixel width. |
||||
* @user_pixel_width: The width of the user data input port. |
||||
* |
||||
* This is a stripped down version of struct main_stream_attributes that |
||||
* contains only the parameters that are not set by cfg_msa_recalculate() |
||||
*/ |
||||
struct logicore_dp_tx_msa { |
||||
u32 pixel_clock_hz; |
||||
u32 bits_per_color; |
||||
u16 h_active; |
||||
u32 h_start; |
||||
bool h_sync_polarity; |
||||
u16 h_sync_width; |
||||
u16 h_total; |
||||
u16 v_active; |
||||
u32 v_start; |
||||
bool v_sync_polarity; |
||||
u16 v_sync_width; |
||||
u16 v_total; |
||||
bool override_user_pixel_width; |
||||
u32 user_pixel_width; |
||||
}; |
||||
|
||||
#endif /* __GDSYS_LOGICORE_DP_TX_H__ */ |
||||
@ -0,0 +1,396 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* logicore_dp_tx_regif.h |
||||
* |
||||
* Register interface definition for XILINX LogiCore DisplayPort v6.1 TX |
||||
* (Source) based on Xilinx dp_v3_1 driver sources |
||||
* |
||||
* (C) Copyright 2016 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc |
||||
*/ |
||||
|
||||
#ifndef __GDSYS_LOGICORE_DP_TX_REGIF_H__ |
||||
#define __GDSYS_LOGICORE_DP_TX_REGIF_H__ |
||||
|
||||
enum { |
||||
/* link configuration field */ |
||||
REG_LINK_BW_SET = 0x000, |
||||
REG_LANE_COUNT_SET = 0x004, |
||||
REG_ENHANCED_FRAME_EN = 0x008, |
||||
REG_TRAINING_PATTERN_SET = 0x00C, |
||||
REG_LINK_QUAL_PATTERN_SET = 0x010, |
||||
REG_SCRAMBLING_DISABLE = 0x014, |
||||
REG_DOWNSPREAD_CTRL = 0x018, |
||||
REG_SOFT_RESET = 0x01C, |
||||
}; |
||||
|
||||
enum { |
||||
/* core enables */ |
||||
REG_ENABLE = 0x080, |
||||
REG_ENABLE_MAIN_STREAM = 0x084, |
||||
REG_ENABLE_SEC_STREAM = 0x088, |
||||
REG_FORCE_SCRAMBLER_RESET = 0x0C0, |
||||
REG_MST_CONFIG = 0x0D0, |
||||
REG_LINE_RESET_DISABLE = 0x0F0, |
||||
}; |
||||
|
||||
enum { |
||||
/* core ID */ |
||||
REG_VERSION = 0x0F8, |
||||
REG_CORE_ID = 0x0FC, |
||||
}; |
||||
|
||||
enum { |
||||
/* AUX channel interface */ |
||||
REG_AUX_CMD = 0x100, |
||||
REG_AUX_WRITE_FIFO = 0x104, |
||||
REG_AUX_ADDRESS = 0x108, |
||||
REG_AUX_CLK_DIVIDER = 0x10C, |
||||
REG_USER_FIFO_OVERFLOW = 0x110, |
||||
REG_INTERRUPT_SIG_STATE = 0x130, |
||||
REG_AUX_REPLY_DATA = 0x134, |
||||
REG_AUX_REPLY_CODE = 0x138, |
||||
REG_AUX_REPLY_COUNT = 0x13C, |
||||
REG_INTERRUPT_STATUS = 0x140, |
||||
REG_INTERRUPT_MASK = 0x144, |
||||
REG_REPLY_DATA_COUNT = 0x148, |
||||
REG_REPLY_STATUS = 0x14C, |
||||
REG_HPD_DURATION = 0x150, |
||||
}; |
||||
|
||||
enum { |
||||
/* main stream attributes for SST / MST STREAM1 */ |
||||
REG_STREAM1_MSA_START = 0x180, |
||||
REG_MAIN_STREAM_HTOTAL = 0x180, |
||||
REG_MAIN_STREAM_VTOTAL = 0x184, |
||||
REG_MAIN_STREAM_POLARITY = 0x188, |
||||
REG_MAIN_STREAM_HSWIDTH = 0x18C, |
||||
REG_MAIN_STREAM_VSWIDTH = 0x190, |
||||
REG_MAIN_STREAM_HRES = 0x194, |
||||
REG_MAIN_STREAM_VRES = 0x198, |
||||
REG_MAIN_STREAM_HSTART = 0x19C, |
||||
REG_MAIN_STREAM_VSTART = 0x1A0, |
||||
REG_MAIN_STREAM_MISC0 = 0x1A4, |
||||
REG_MAIN_STREAM_MISC1 = 0x1A8, |
||||
REG_M_VID = 0x1AC, |
||||
REG_TU_SIZE = 0x1B0, |
||||
REG_N_VID = 0x1B4, |
||||
REG_USER_PIXEL_WIDTH = 0x1B8, |
||||
REG_USER_DATA_COUNT_PER_LANE = 0x1BC, |
||||
REG_MAIN_STREAM_INTERLACED = 0x1C0, |
||||
REG_MIN_BYTES_PER_TU = 0x1C4, |
||||
REG_FRAC_BYTES_PER_TU = 0x1C8, |
||||
REG_INIT_WAIT = 0x1CC, |
||||
REG_STREAM1 = 0x1D0, |
||||
REG_STREAM2 = 0x1D4, |
||||
REG_STREAM3 = 0x1D8, |
||||
REG_STREAM4 = 0x1DC, |
||||
}; |
||||
|
||||
enum { |
||||
/* PHY configuration status */ |
||||
REG_PHY_CONFIG = 0x200, |
||||
REG_PHY_VOLTAGE_DIFF_LANE_0 = 0x220, |
||||
REG_PHY_VOLTAGE_DIFF_LANE_1 = 0x224, |
||||
REG_PHY_VOLTAGE_DIFF_LANE_2 = 0x228, |
||||
REG_PHY_VOLTAGE_DIFF_LANE_3 = 0x22C, |
||||
REG_PHY_TRANSMIT_PRBS7 = 0x230, |
||||
REG_PHY_CLOCK_SELECT = 0x234, |
||||
REG_PHY_POWER_DOWN = 0x238, |
||||
REG_PHY_PRECURSOR_LANE_0 = 0x23C, |
||||
REG_PHY_PRECURSOR_LANE_1 = 0x240, |
||||
REG_PHY_PRECURSOR_LANE_2 = 0x244, |
||||
REG_PHY_PRECURSOR_LANE_3 = 0x248, |
||||
REG_PHY_POSTCURSOR_LANE_0 = 0x24C, |
||||
REG_PHY_POSTCURSOR_LANE_1 = 0x250, |
||||
REG_PHY_POSTCURSOR_LANE_2 = 0x254, |
||||
REG_PHY_POSTCURSOR_LANE_3 = 0x258, |
||||
REG_PHY_STATUS = 0x280, |
||||
REG_GT_DRP_COMMAND = 0x2A0, |
||||
REG_GT_DRP_READ_DATA = 0x2A4, |
||||
REG_GT_DRP_CHANNEL_STATUS = 0x2A8, |
||||
}; |
||||
|
||||
enum { |
||||
/* DisplayPort audio */ |
||||
REG_AUDIO_CONTROL = 0x300, |
||||
REG_AUDIO_CHANNELS = 0x304, |
||||
REG_AUDIO_INFO_DATA = 0x308, |
||||
REG_AUDIO_MAUD = 0x328, |
||||
REG_AUDIO_NAUD = 0x32C, |
||||
REG_AUDIO_EXT_DATA = 0x330, |
||||
}; |
||||
|
||||
enum { |
||||
/* HDCP */ |
||||
REG_HDCP_ENABLE = 0x400, |
||||
}; |
||||
|
||||
enum { |
||||
/* main stream attributes for MST STREAM2, 3, and 4 */ |
||||
REG_STREAM2_MSA_START = 0x500, |
||||
REG_STREAM3_MSA_START = 0x550, |
||||
REG_STREAM4_MSA_START = 0x5A0, |
||||
|
||||
REG_VC_PAYLOAD_BUFFER_ADDR = 0x800, |
||||
}; |
||||
|
||||
enum { |
||||
LINK_BW_SET_162GBPS = 0x06, |
||||
LINK_BW_SET_270GBPS = 0x0A, |
||||
LINK_BW_SET_540GBPS = 0x14, |
||||
}; |
||||
|
||||
enum { |
||||
LANE_COUNT_SET_1 = 0x1, |
||||
LANE_COUNT_SET_2 = 0x2, |
||||
LANE_COUNT_SET_4 = 0x4, |
||||
}; |
||||
|
||||
enum { |
||||
TRAINING_PATTERN_SET_OFF = 0x0, |
||||
/* training pattern 1 used for clock recovery */ |
||||
TRAINING_PATTERN_SET_TP1 = 0x1, |
||||
/* training pattern 2 used for channel equalization */ |
||||
TRAINING_PATTERN_SET_TP2 = 0x2, |
||||
/*
|
||||
* training pattern 3 used for channel equalization for cores with DP |
||||
* v1.2 |
||||
*/ |
||||
TRAINING_PATTERN_SET_TP3 = 0x3, |
||||
}; |
||||
|
||||
enum { |
||||
LINK_QUAL_PATTERN_SET_OFF = 0x0, |
||||
/* D10.2 unscrambled test pattern transmitted */ |
||||
LINK_QUAL_PATTERN_SET_D102_TEST = 0x1, |
||||
/* symbol error rate measurement pattern transmitted */ |
||||
LINK_QUAL_PATTERN_SET_SER_MES = 0x2, |
||||
/* pseudo random bit sequence 7 transmitted */ |
||||
LINK_QUAL_PATTERN_SET_PRBS7 = 0x3, |
||||
}; |
||||
|
||||
enum { |
||||
SOFT_RESET_VIDEO_STREAM1_MASK = 0x00000001, |
||||
SOFT_RESET_VIDEO_STREAM2_MASK = 0x00000002, |
||||
SOFT_RESET_VIDEO_STREAM3_MASK = 0x00000004, |
||||
SOFT_RESET_VIDEO_STREAM4_MASK = 0x00000008, |
||||
SOFT_RESET_AUX_MASK = 0x00000080, |
||||
SOFT_RESET_VIDEO_STREAM_ALL_MASK = 0x0000000F, |
||||
}; |
||||
|
||||
enum { |
||||
MST_CONFIG_MST_EN_MASK = 0x00000001, |
||||
}; |
||||
|
||||
enum { |
||||
LINE_RESET_DISABLE_MASK = 0x1, |
||||
}; |
||||
|
||||
#define AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F |
||||
|
||||
#define AUX_CMD_SHIFT 8 |
||||
#define AUX_CMD_MASK 0x00000F00 |
||||
enum { |
||||
AUX_CMD_I2C_WRITE = 0x0, |
||||
AUX_CMD_I2C_READ = 0x1, |
||||
AUX_CMD_I2C_WRITE_STATUS = 0x2, |
||||
AUX_CMD_I2C_WRITE_MOT = 0x4, |
||||
AUX_CMD_I2C_READ_MOT = 0x5, |
||||
AUX_CMD_I2C_WRITE_STATUS_MOT = 0x6, |
||||
AUX_CMD_WRITE = 0x8, |
||||
AUX_CMD_READ = 0x9, |
||||
}; |
||||
|
||||
#define AUX_CLK_DIVIDER_VAL_MASK 0x00FF |
||||
|
||||
#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT 8 |
||||
#define AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK 0xFF00 |
||||
|
||||
enum { |
||||
INTERRUPT_SIG_STATE_HPD_STATE_MASK = 0x00000001, |
||||
INTERRUPT_SIG_STATE_REQUEST_STATE_MASK = 0x00000002, |
||||
INTERRUPT_SIG_STATE_REPLY_STATE_MASK = 0x00000004, |
||||
INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK = 0x00000008, |
||||
}; |
||||
|
||||
enum { |
||||
AUX_REPLY_CODE_ACK = 0x0, |
||||
AUX_REPLY_CODE_I2C_ACK = 0x0, |
||||
AUX_REPLY_CODE_NACK = 0x1, |
||||
AUX_REPLY_CODE_DEFER = 0x2, |
||||
AUX_REPLY_CODE_I2C_NACK = 0x4, |
||||
AUX_REPLY_CODE_I2C_DEFER = 0x8, |
||||
}; |
||||
|
||||
enum { |
||||
INTERRUPT_STATUS_HPD_IRQ_MASK = 0x00000001, |
||||
INTERRUPT_STATUS_HPD_EVENT_MASK = 0x00000002, |
||||
INTERRUPT_STATUS_REPLY_RECEIVED_MASK = 0x00000004, |
||||
INTERRUPT_STATUS_REPLY_TIMEOUT_MASK = 0x00000008, |
||||
INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK = 0x00000010, |
||||
INTERRUPT_STATUS_EXT_PKT_TXD_MASK = 0x00000020, |
||||
}; |
||||
|
||||
enum { |
||||
INTERRUPT_MASK_HPD_IRQ_MASK = 0x00000001, |
||||
INTERRUPT_MASK_HPD_EVENT_MASK = 0x00000002, |
||||
INTERRUPT_MASK_REPLY_RECEIVED_MASK = 0x00000004, |
||||
INTERRUPT_MASK_REPLY_TIMEOUT_MASK = 0x00000008, |
||||
INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK = 0x00000010, |
||||
INTERRUPT_MASK_EXT_PKT_TXD_MASK = 0x00000020, |
||||
}; |
||||
|
||||
#define REPLY_STATUS_REPLY_STATUS_STATE_SHIFT 4 |
||||
#define REPLY_STATUS_REPLY_STATUS_STATE_MASK 0x00000FF0 |
||||
enum { |
||||
REPLY_STATUS_REPLY_RECEIVED_MASK = 0x00000001, |
||||
REPLY_STATUS_REPLY_IN_PROGRESS_MASK = 0x00000002, |
||||
REPLY_STATUS_REQUEST_IN_PROGRESS_MASK = 0x00000004, |
||||
REPLY_STATUS_REPLY_ERROR_MASK = 0x00000008, |
||||
}; |
||||
|
||||
#define MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT 1 |
||||
enum { |
||||
MAIN_STREAMX_POLARITY_HSYNC_POL_MASK = 0x00000001, |
||||
MAIN_STREAMX_POLARITY_VSYNC_POL_MASK = 0x00000002, |
||||
}; |
||||
|
||||
enum { |
||||
MAIN_STREAMX_MISC0_SYNC_CLK_MASK = 0x00000001, |
||||
}; |
||||
|
||||
#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT 1 |
||||
#define MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK 0x00000006 |
||||
enum { |
||||
MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB = 0x0, |
||||
MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 = 0x1, |
||||
MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 = 0x2, |
||||
}; |
||||
|
||||
#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT 3 |
||||
#define MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK 0x00000008 |
||||
|
||||
#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT 4 |
||||
#define MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK 0x00000010 |
||||
|
||||
#define MAIN_STREAMX_MISC0_BDC_SHIFT 5 |
||||
#define MAIN_STREAMX_MISC0_BDC_MASK 0x000000E0 |
||||
enum { |
||||
MAIN_STREAMX_MISC0_BDC_6BPC = 0x0, |
||||
MAIN_STREAMX_MISC0_BDC_8BPC = 0x1, |
||||
MAIN_STREAMX_MISC0_BDC_10BPC = 0x2, |
||||
MAIN_STREAMX_MISC0_BDC_12BPC = 0x3, |
||||
MAIN_STREAMX_MISC0_BDC_16BPC = 0x4, |
||||
}; |
||||
|
||||
enum { |
||||
PHY_CONFIG_PHY_RESET_ENABLE_MASK = 0x0000000, |
||||
PHY_CONFIG_PHY_RESET_MASK = 0x0000001, |
||||
PHY_CONFIG_GTTX_RESET_MASK = 0x0000002, |
||||
PHY_CONFIG_GT_ALL_RESET_MASK = 0x0000003, |
||||
PHY_CONFIG_TX_PHY_PMA_RESET_MASK = 0x0000100, |
||||
PHY_CONFIG_TX_PHY_PCS_RESET_MASK = 0x0000200, |
||||
PHY_CONFIG_TX_PHY_POLARITY_MASK = 0x0000800, |
||||
PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK = 0x0001000, |
||||
PHY_CONFIG_TX_PHY_POLARITY_IND_LANE_MASK = 0x0010000, |
||||
PHY_CONFIG_TX_PHY_POLARITY_LANE0_MASK = 0x0020000, |
||||
PHY_CONFIG_TX_PHY_POLARITY_LANE1_MASK = 0x0040000, |
||||
PHY_CONFIG_TX_PHY_POLARITY_LANE2_MASK = 0x0080000, |
||||
PHY_CONFIG_TX_PHY_POLARITY_LANE3_MASK = 0x0100000, |
||||
PHY_CONFIG_TX_PHY_8B10BEN_MASK = 0x0200000, |
||||
}; |
||||
|
||||
#define PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT 13 |
||||
#define PHY_CONFIG_TX_PHY_LOOPBACK_MASK 0x000E000 |
||||
|
||||
enum { |
||||
PHY_CLOCK_SELECT_162GBPS = 0x1, |
||||
PHY_CLOCK_SELECT_270GBPS = 0x3, |
||||
PHY_CLOCK_SELECT_540GBPS = 0x5, |
||||
}; |
||||
|
||||
enum { |
||||
VS_LEVEL_0 = 0x2, |
||||
VS_LEVEL_1 = 0x5, |
||||
VS_LEVEL_2 = 0x8, |
||||
VS_LEVEL_3 = 0xF, |
||||
VS_LEVEL_OFFSET = 0x4, |
||||
}; |
||||
|
||||
enum { |
||||
PE_LEVEL_0 = 0x00, |
||||
PE_LEVEL_1 = 0x0E, |
||||
PE_LEVEL_2 = 0x14, |
||||
PE_LEVEL_3 = 0x1B, |
||||
}; |
||||
|
||||
enum { |
||||
PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT = 2, |
||||
PHY_STATUS_TX_ERROR_LANE_0_SHIFT = 18, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_1_SHIFT = 20, |
||||
PHY_STATUS_TX_ERROR_LANE_1_SHIFT = 22, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_0_SHIFT = 16, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_2_SHIFT = 24, |
||||
PHY_STATUS_TX_ERROR_LANE_2_SHIFT = 26, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_3_SHIFT = 28, |
||||
PHY_STATUS_TX_ERROR_LANE_3_SHIFT = 30, |
||||
}; |
||||
|
||||
enum { |
||||
PHY_STATUS_RESET_LANE_0_DONE_MASK = 0x00000001, |
||||
PHY_STATUS_RESET_LANE_1_DONE_MASK = 0x00000002, |
||||
PHY_STATUS_RESET_LANE_2_3_DONE_MASK = 0x0000000C, |
||||
PHY_STATUS_PLL_LANE0_1_LOCK_MASK = 0x00000010, |
||||
PHY_STATUS_PLL_LANE2_3_LOCK_MASK = 0x00000020, |
||||
PHY_STATUS_PLL_FABRIC_LOCK_MASK = 0x00000040, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_0_MASK = 0x00030000, |
||||
PHY_STATUS_TX_ERROR_LANE_0_MASK = 0x000C0000, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_1_MASK = 0x00300000, |
||||
PHY_STATUS_TX_ERROR_LANE_1_MASK = 0x00C00000, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_2_MASK = 0x03000000, |
||||
PHY_STATUS_TX_ERROR_LANE_2_MASK = 0x0C000000, |
||||
PHY_STATUS_TX_BUFFER_STATUS_LANE_3_MASK = 0x30000000, |
||||
PHY_STATUS_TX_ERROR_LANE_3_MASK = 0xC0000000, |
||||
}; |
||||
|
||||
#define PHY_STATUS_LANE_0_READY_MASK \ |
||||
(PHY_STATUS_RESET_LANE_0_DONE_MASK | \
|
||||
PHY_STATUS_PLL_LANE0_1_LOCK_MASK) |
||||
#define PHY_STATUS_LANES_0_1_READY_MASK \ |
||||
(PHY_STATUS_LANE_0_READY_MASK | \
|
||||
PHY_STATUS_RESET_LANE_1_DONE_MASK) |
||||
/*
|
||||
* PHY_STATUS_ALL_LANES_READY_MASK seems to be missing lanes 0 and 1 in |
||||
* Xilinx dp_v3_0 implementation |
||||
*/ |
||||
#define PHY_STATUS_ALL_LANES_READY_MASK \ |
||||
(PHY_STATUS_LANES_0_1_READY_MASK | \
|
||||
PHY_STATUS_RESET_LANE_2_3_DONE_MASK | \
|
||||
PHY_STATUS_PLL_LANE2_3_LOCK_MASK) |
||||
|
||||
/**
|
||||
* phy_status_lanes_ready_mask() - Generate phy status ready mask |
||||
* @lane_count: Number of lanes for which to generate a mask |
||||
* |
||||
* Return: The generated phy status ready mask |
||||
*/ |
||||
static inline u32 phy_status_lanes_ready_mask(u8 lane_count) |
||||
{ |
||||
if (lane_count > 2) |
||||
return PHY_STATUS_ALL_LANES_READY_MASK; |
||||
|
||||
if (lane_count == 2) |
||||
return PHY_STATUS_LANES_0_1_READY_MASK; |
||||
|
||||
return PHY_STATUS_LANE_0_READY_MASK; |
||||
} |
||||
|
||||
#define GT_DRP_COMMAND_DRP_ADDR_MASK 0x000F |
||||
#define GT_DRP_COMMAND_DRP_RW_CMD_MASK 0x0080 |
||||
#define GT_DRP_COMMAND_DRP_W_DATA_SHIFT 16 |
||||
#define GT_DRP_COMMAND_DRP_W_DATA_MASK 0xFF00 |
||||
|
||||
#define HDCP_ENABLE_BYPASS_DISABLE_MASK 0x0001 |
||||
|
||||
#endif /* __GDSYS_LOGICORE_DP_TX_REGIF_H__ */ |
||||
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Reference in new issue