add MII routines to the au1x00 ethernet driver; add USB ohci driver (work in progress) Patch by Thomas Sailer, 20 Jan 2005master
Wolfgang Denk
20 years ago
parent
b63de2c053
commit
265817c7e6
@ -0,0 +1,41 @@ |
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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SOBJS = memsetup.o
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$(LIB): .depend $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,63 @@ |
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By Thomas.Lange@corelatus.se 2004-Oct-05 |
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---------------------------------------- |
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DbAu1xx0 are development boards from AMD containing |
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an Alchemy AU1xx0 series cpu with mips32 core. |
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Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 |
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|
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Limitations & comments |
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---------------------- |
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Support was originally big endian only. |
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I have not tested, but several u-boot users report working |
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configurations in little endian mode. |
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|
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I named the board dbau1x00, to allow |
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support for all three development boards |
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( dbau1000, dbau1100 and dbau1500 ). |
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Now there is a new board called dbau1550 also, which |
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should be supported RSN. |
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I only have a dbau1000, so my testing is limited |
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to this board. |
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The board has two different flash banks, that can |
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be selected via dip switch. This makes it possible |
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to test new bootloaders without thrashing the YAMON |
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boot loader delivered with board. |
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NOTE! When you switch between the two boot flashes, the |
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base addresses will be swapped. |
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Have this in mind when you compile u-boot. TEXT_BASE has |
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to match the address where u-boot is located when you |
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actually launch. |
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Ethernet only supported for mac0. |
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PCMCIA only supported for slot 0, only 3.3V. |
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PCMCIA IDE tested with Sandisk Compact Flash and |
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IBM microdrive. |
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################################### |
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######## NOTE!!!!!! ######### |
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################################### |
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If you partition a disk on another system (e.g. laptop), |
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all bytes will be swapped on 16bit level when using |
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PCMCIA and running cpu in big endian mode!!!! |
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This is probably due to an error in Au1000 chip. |
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Solution: |
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a) Boot via network and partition disk directly from |
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dbau1x00. The endian will then be correct. |
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b) Partition disk on "laptop" and fill it with all files |
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you need. Then write a simple program that endian swaps |
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whole disk, |
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Example: |
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Original "laptop" byte order: |
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B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... |
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Dbau1000 byte order will then be: |
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B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... |
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@ -0,0 +1,32 @@ |
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# AMD development board AMD Alchemy Pb1x00, MIPS32 core
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#
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# ROM version
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#TEXT_BASE = 0xbfc00000
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# SDRAM version
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TEXT_BASE = 0x83800000
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@ -0,0 +1,43 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* flash_init() |
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* |
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* sets up flash_info and returns size of FLASH (bytes) |
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*/ |
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unsigned long flash_init (void) |
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{ |
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printf ("Skipping flash_init\n"); |
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return (0); |
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} |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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printf ("write_buff not implemented\n"); |
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return (-1); |
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} |
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@ -0,0 +1,392 @@ |
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/* Memory sub-system initialization code */ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/regdef.h> |
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#include <asm/au1x00.h> |
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#include <asm/mipsregs.h> |
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#define AU1500_SYS_ADDR 0xB1900000 |
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#define sys_endian 0x0038 |
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#define CP0_Config0 $16 |
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#define MEM_1MS ((396000000/1000000) * 1000) |
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.text |
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.set noreorder
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.set mips32
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.globl memsetup
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memsetup: |
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/* |
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* Step 1) Establish CPU endian mode. |
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* NOTE: A fair amount of code is necessary on the Pb1000 to |
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* obtain the value of Switch S8.1 which is used to determine |
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* endian at run-time. |
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*/ |
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/* RCE1 */ |
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li t0, MEM_STCFG1 |
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li t1, 0x00000083 |
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sw t1, 0(t0) |
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li t0, MEM_STTIME1 |
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li t1, 0x33030A10 |
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sw t1, 0(t0) |
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li t0, MEM_STADDR1 |
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li t1, 0x11803E40 |
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sw t1, 0(t0) |
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/* Set DSTRB bits so switch will read correctly */ |
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li t1, 0xBE00000C |
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lw t2, 0(t1) |
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or t2, t2, 0x00000300 |
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sw t2, 0(t1) |
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/* Check switch setting */ |
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li t1, 0xBE000014 |
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lw t2, 0(t1) |
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and t2, t2, 0x00000100 |
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bne t2, zero, big_endian |
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nop |
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little_endian: |
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/* Change Au1 core to little endian */ |
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li t0, AU1500_SYS_ADDR |
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li t1, 1 |
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sw t1, sys_endian(t0) |
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mfc0 t2, CP0_CONFIG |
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mtc0 t2, CP0_CONFIG |
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nop |
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nop |
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/* Big Endian is default so nothing to do but fall through */ |
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big_endian: |
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/* |
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* Step 2) Establish Status Register |
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* (set BEV, clear ERL, clear EXL, clear IE) |
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*/ |
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li t1, 0x00400000 |
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mtc0 t1, CP0_STATUS |
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/* |
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* Step 3) Establish CP0 Config0 |
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* (set OD, set K0=3) |
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*/ |
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li t1, 0x00080003 |
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mtc0 t1, CP0_CONFIG |
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/* |
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* Step 4) Disable Watchpoint facilities |
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*/ |
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li t1, 0x00000000 |
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mtc0 t1, CP0_WATCHLO |
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mtc0 t1, CP0_IWATCHLO |
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/* |
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* Step 5) Disable the performance counters |
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*/ |
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mtc0 zero, CP0_PERFORMANCE |
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nop |
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/* |
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* Step 6) Establish EJTAG Debug register |
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*/ |
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mtc0 zero, CP0_DEBUG |
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nop |
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/* |
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* Step 7) Establish Cause |
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* (set IV bit) |
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*/ |
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li t1, 0x00800000 |
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mtc0 t1, CP0_CAUSE |
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/* Establish Wired (and Random) */ |
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mtc0 zero, CP0_WIRED |
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nop |
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/* First setup pll:s to make serial work ok */ |
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/* We have a 12 MHz crystal */ |
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li t0, SYS_CPUPLL |
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li t1, 0x21 /* 396 MHz */ |
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sw t1, 0(t0) |
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sync |
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nop |
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nop |
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/* wait 1mS for clocks to settle */ |
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li t1, MEM_1MS |
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1: add t1, -1 |
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bne t1, zero, 1b |
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nop |
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/* Setup AUX PLL */ |
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li t0, SYS_AUXPLL |
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li t1, 8 /* 96 MHz */ |
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sw t1, 0(t0) /* aux pll */ |
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sync |
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/* Static memory controller */ |
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/* RCE0 8MB AMD29D323 Flash */ |
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li t0, MEM_STCFG0 |
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li t1, 0x00001403 |
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sw t1, 0(t0) |
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li t0, MEM_STTIME0 |
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li t1, 0xFFFFFFDD |
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sw t1, 0(t0) |
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li t0, MEM_STADDR0 |
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li t1, 0x11F83FE0 |
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sw t1, 0(t0) |
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/* RCE1 CPLD Board Logic */ |
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li t0, MEM_STCFG1 |
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li t1, 0x00000083 |
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sw t1, 0(t0) |
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li t0, MEM_STTIME1 |
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li t1, 0x33030A10 |
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sw t1, 0(t0) |
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li t0, MEM_STADDR1 |
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li t1, 0x11803E40 |
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sw t1, 0(t0) |
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/* RCE2 CPLD Board Logic */ |
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li t0, MEM_STCFG2 |
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li t1, 0x00000004 |
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sw t1, 0(t0) |
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li t0, MEM_STTIME2 |
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li t1, 0x08061908 |
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sw t1, 0(t0) |
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li t0, MEM_STADDR2 |
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li t1, 0x12A03FC0 |
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sw t1, 0(t0) |
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/* RCE3 PCMCIA 250ns */ |
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li t0, MEM_STCFG3 |
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li t1, 0x00000002 |
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sw t1, 0(t0) |
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li t0, MEM_STTIME3 |
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li t1, 0x280E3E07 |
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sw t1, 0(t0) |
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li t0, MEM_STADDR3 |
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li t1, 0x10000000 |
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sw t1, 0(t0) |
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sync |
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/* Set peripherals to a known state */ |
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li t0, IC0_CFG0CLR |
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li t1, 0xFFFFFFFF |
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sw t1, 0(t0) |
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li t0, IC0_CFG0CLR |
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sw t1, 0(t0) |
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li t0, IC0_CFG1CLR |
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sw t1, 0(t0) |
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li t0, IC0_CFG2CLR |
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sw t1, 0(t0) |
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li t0, IC0_SRCSET |
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sw t1, 0(t0) |
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li t0, IC0_ASSIGNSET |
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sw t1, 0(t0) |
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li t0, IC0_WAKECLR |
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sw t1, 0(t0) |
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li t0, IC0_RISINGCLR |
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sw t1, 0(t0) |
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li t0, IC0_FALLINGCLR |
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sw t1, 0(t0) |
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li t0, IC0_TESTBIT |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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sync |
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li t0, IC1_CFG0CLR |
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li t1, 0xFFFFFFFF |
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sw t1, 0(t0) |
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li t0, IC1_CFG0CLR |
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sw t1, 0(t0) |
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li t0, IC1_CFG1CLR |
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sw t1, 0(t0) |
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li t0, IC1_CFG2CLR |
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sw t1, 0(t0) |
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li t0, IC1_SRCSET |
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sw t1, 0(t0) |
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li t0, IC1_ASSIGNSET |
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sw t1, 0(t0) |
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li t0, IC1_WAKECLR |
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sw t1, 0(t0) |
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li t0, IC1_RISINGCLR |
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sw t1, 0(t0) |
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li t0, IC1_FALLINGCLR |
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sw t1, 0(t0) |
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li t0, IC1_TESTBIT |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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sync |
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li t0, SYS_FREQCTRL0 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, SYS_FREQCTRL1 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, SYS_CLKSRC |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, SYS_PININPUTEN |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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sync |
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li t0, 0xB1100100 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, 0xB1400100 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, SYS_WAKEMSK |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, SYS_WAKESRC |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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/* wait 1mS before setup */ |
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li t1, MEM_1MS |
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1: add t1, -1 |
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bne t1, zero, 1b |
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nop |
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/* |
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* Skip memory setup if we are running from memory |
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*/ |
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li t0, 0x90000000 |
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sub t0, ra, t0 |
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bltz t0, skip_memsetup |
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nop |
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/* |
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* SDCS0 - Not used, for SMROM |
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* SDCS1 - 32MB Micron 48LCBM16A2 |
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* SDCS2 - 32MB Micron 48LCBM16A2 |
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*/ |
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li t0, MEM_SDMODE0 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, MEM_SDMODE1 |
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li t1, 0x00552229 |
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sw t1, 0(t0) |
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li t0, MEM_SDMODE2 |
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li t1, 0x00552229 |
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sw t1, 0(t0) |
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li t0, MEM_SDADDR0 |
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li t1, 0x00000000 |
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sw t1, 0(t0) |
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li t0, MEM_SDADDR1 |
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li t1, 0x001003F8 |
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sw t1, 0(t0) |
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li t0, MEM_SDADDR2 |
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li t1, 0x001023F8 |
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sw t1, 0(t0) |
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sync |
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li t0, MEM_SDREFCFG |
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li t1, 0x74000c30 /* Disable */ |
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sw t1, 0(t0) |
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sync |
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li t0, MEM_SDPRECMD |
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sw zero, 0(t0) |
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sync |
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li t0, MEM_SDAUTOREF |
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sw zero, 0(t0) |
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sync |
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sw zero, 0(t0) |
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sync |
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li t0, MEM_SDREFCFG |
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li t1, 0x76000c30 /* Enable */ |
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sw t1, 0(t0) |
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sync |
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li t0, MEM_SDWRMD0 |
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li t1, 0x00000023 |
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sw t1, 0(t0) |
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sync |
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li t0, MEM_SDWRMD1 |
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li t1, 0x00000023 |
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sw t1, 0(t0) |
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sync |
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li t0, MEM_SDWRMD2 |
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li t1, 0x00000023 |
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sw t1, 0(t0) |
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sync |
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/* wait 1mS after setup */ |
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li t1, MEM_1MS |
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1: add t1, -1 |
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bne t1, zero, 1b |
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nop |
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skip_memsetup: |
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li t0, SYS_PINFUNC |
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li t1, 0/*0x00008080*/ |
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sw t1, 0(t0) |
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/* |
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li t0, SYS_TRIOUTCLR |
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li t1, 0x00001FFF |
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sw t1, 0(t0) |
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li t0, SYS_OUTPUTCLR |
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li t1, 0x00008000 |
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sw t1, 0(t0) |
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*/ |
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sync |
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j ra |
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nop |
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@ -0,0 +1,115 @@ |
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/*
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* (C) Copyright 2003 |
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* Thomas.Lange@corelatus.se |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/au1x00.h> |
||||
#include <asm/mipsregs.h> |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
/* Sdram is setup by assembler code */ |
||||
/* If memory could be changed, we should return the true value here */ |
||||
return 64*1024*1024; |
||||
} |
||||
|
||||
#define BCSR_PCMCIA_PC0DRVEN 0x0010 |
||||
#define BCSR_PCMCIA_PC0RST 0x0080 |
||||
|
||||
/* In cpu/mips/cpu.c */ |
||||
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
u16 status; |
||||
/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ |
||||
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; |
||||
u32 proc_id; |
||||
|
||||
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ |
||||
|
||||
proc_id = read_32bit_cp0_register(CP0_PRID); |
||||
|
||||
switch (proc_id >> 24) { |
||||
case 0: |
||||
puts ("Board: Pb1000\n"); |
||||
printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", |
||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
||||
break; |
||||
case 1: |
||||
puts ("Board: Pb1500\n"); |
||||
printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", |
||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
||||
break; |
||||
case 2: |
||||
puts ("Board: Pb1100\n"); |
||||
printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", |
||||
(proc_id >> 8) & 0xFF, proc_id & 0xFF); |
||||
break; |
||||
default: |
||||
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); |
||||
} |
||||
#if defined(CONFIG_IDE_PCMCIA) && 0 |
||||
/* Enable 3.3 V on slot 0 ( VCC )
|
||||
No 5V */ |
||||
status = 4; |
||||
*pcmcia_bcsr = status; |
||||
|
||||
status |= BCSR_PCMCIA_PC0DRVEN; |
||||
*pcmcia_bcsr = status; |
||||
au_sync(); |
||||
|
||||
udelay(300*1000); |
||||
|
||||
status |= BCSR_PCMCIA_PC0RST; |
||||
*pcmcia_bcsr = status; |
||||
au_sync(); |
||||
|
||||
udelay(100*1000); |
||||
|
||||
/* PCMCIA is on a 36 bit physical address.
|
||||
We need to map it into a 32 bit addresses */ |
||||
|
||||
#if 0 |
||||
/* We dont need theese unless we run whole pcmcia package */ |
||||
write_one_tlb(20, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_IO_BASE, /* Hi */ |
||||
0x3C000017, /* Lo0 */ |
||||
0x3C200017); /* Lo1 */ |
||||
|
||||
write_one_tlb(21, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_ATTR_BASE, /* Hi */ |
||||
0x3D000017, /* Lo0 */ |
||||
0x3D200017); /* Lo1 */ |
||||
#endif /* 0 */ |
||||
write_one_tlb(22, /* index */ |
||||
0x01ffe000, /* Pagemask, 16 MB pages */ |
||||
CFG_PCMCIA_MEM_ADDR, /* Hi */ |
||||
0x3E000017, /* Lo0 */ |
||||
0x3E200017); /* Lo1 */ |
||||
#endif /* CONFIG_IDE_PCMCIA */ |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,68 @@ |
||||
/* |
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk Engineering, <wd@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* |
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") |
||||
*/ |
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") |
||||
OUTPUT_ARCH(mips) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.sdata : { *(.sdata) } |
||||
|
||||
_gp = ALIGN(16); |
||||
|
||||
__got_start = .; |
||||
.got : { *(.got) } |
||||
__got_end = .; |
||||
|
||||
.sdata : { *(.sdata) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
uboot_end_data = .; |
||||
num_got_entries = (__got_end - __got_start) >> 2; |
||||
|
||||
. = ALIGN(4); |
||||
.sbss : { *(.sbss) } |
||||
.bss : { *(.bss) } |
||||
uboot_end = .; |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,416 @@ |
||||
/*
|
||||
* URB OHCI HCD (Host Controller Driver) for USB. |
||||
* |
||||
* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
||||
* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> |
||||
* |
||||
* usb-ohci.h |
||||
*/ |
||||
|
||||
|
||||
static int cc_to_error[16] = { |
||||
|
||||
/* mapping of the OHCI CC status to error codes */ |
||||
/* No Error */ 0, |
||||
/* CRC Error */ USB_ST_CRC_ERR, |
||||
/* Bit Stuff */ USB_ST_BIT_ERR, |
||||
/* Data Togg */ USB_ST_CRC_ERR, |
||||
/* Stall */ USB_ST_STALLED, |
||||
/* DevNotResp */ -1, |
||||
/* PIDCheck */ USB_ST_BIT_ERR, |
||||
/* UnExpPID */ USB_ST_BIT_ERR, |
||||
/* DataOver */ USB_ST_BUF_ERR, |
||||
/* DataUnder */ USB_ST_BUF_ERR, |
||||
/* reservd */ -1, |
||||
/* reservd */ -1, |
||||
/* BufferOver */ USB_ST_BUF_ERR, |
||||
/* BuffUnder */ USB_ST_BUF_ERR, |
||||
/* Not Access */ -1, |
||||
/* Not Access */ -1 |
||||
}; |
||||
|
||||
/* ED States */ |
||||
|
||||
#define ED_NEW 0x00 |
||||
#define ED_UNLINK 0x01 |
||||
#define ED_OPER 0x02 |
||||
#define ED_DEL 0x04 |
||||
#define ED_URB_DEL 0x08 |
||||
|
||||
/* usb_ohci_ed */ |
||||
struct ed { |
||||
__u32 hwINFO; |
||||
__u32 hwTailP; |
||||
__u32 hwHeadP; |
||||
__u32 hwNextED; |
||||
|
||||
struct ed *ed_prev; |
||||
__u8 int_period; |
||||
__u8 int_branch; |
||||
__u8 int_load; |
||||
__u8 int_interval; |
||||
__u8 state; |
||||
__u8 type; |
||||
__u16 last_iso; |
||||
struct ed *ed_rm_list; |
||||
|
||||
struct usb_device *usb_dev; |
||||
__u32 unused[3]; |
||||
} __attribute((aligned(16))); |
||||
typedef struct ed ed_t; |
||||
|
||||
|
||||
/* TD info field */ |
||||
#define TD_CC 0xf0000000 |
||||
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) |
||||
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) |
||||
#define TD_EC 0x0C000000 |
||||
#define TD_T 0x03000000 |
||||
#define TD_T_DATA0 0x02000000 |
||||
#define TD_T_DATA1 0x03000000 |
||||
#define TD_T_TOGGLE 0x00000000 |
||||
#define TD_R 0x00040000 |
||||
#define TD_DI 0x00E00000 |
||||
#define TD_DI_SET(X) (((X) & 0x07)<< 21) |
||||
#define TD_DP 0x00180000 |
||||
#define TD_DP_SETUP 0x00000000 |
||||
#define TD_DP_IN 0x00100000 |
||||
#define TD_DP_OUT 0x00080000 |
||||
|
||||
#define TD_ISO 0x00010000 |
||||
#define TD_DEL 0x00020000 |
||||
|
||||
/* CC Codes */ |
||||
#define TD_CC_NOERROR 0x00 |
||||
#define TD_CC_CRC 0x01 |
||||
#define TD_CC_BITSTUFFING 0x02 |
||||
#define TD_CC_DATATOGGLEM 0x03 |
||||
#define TD_CC_STALL 0x04 |
||||
#define TD_DEVNOTRESP 0x05 |
||||
#define TD_PIDCHECKFAIL 0x06 |
||||
#define TD_UNEXPECTEDPID 0x07 |
||||
#define TD_DATAOVERRUN 0x08 |
||||
#define TD_DATAUNDERRUN 0x09 |
||||
#define TD_BUFFEROVERRUN 0x0C |
||||
#define TD_BUFFERUNDERRUN 0x0D |
||||
#define TD_NOTACCESSED 0x0F |
||||
|
||||
|
||||
#define MAXPSW 1 |
||||
|
||||
struct td { |
||||
__u32 hwINFO; |
||||
__u32 hwCBP; /* Current Buffer Pointer */ |
||||
__u32 hwNextTD; /* Next TD Pointer */ |
||||
__u32 hwBE; /* Memory Buffer End Pointer */ |
||||
|
||||
__u16 hwPSW[MAXPSW]; |
||||
__u8 unused; |
||||
__u8 index; |
||||
struct ed *ed; |
||||
struct td *next_dl_td; |
||||
struct usb_device *usb_dev; |
||||
int transfer_len; |
||||
__u32 data; |
||||
|
||||
__u32 unused2[2]; |
||||
} __attribute((aligned(32))); |
||||
typedef struct td td_t; |
||||
|
||||
#define OHCI_ED_SKIP (1 << 14) |
||||
|
||||
/*
|
||||
* The HCCA (Host Controller Communications Area) is a 256 byte |
||||
* structure defined in the OHCI spec. that the host controller is |
||||
* told the base address of. It must be 256-byte aligned. |
||||
*/ |
||||
|
||||
#define NUM_INTS 32 /* part of the OHCI standard */ |
||||
struct ohci_hcca { |
||||
__u32 int_table[NUM_INTS]; /* Interrupt ED table */ |
||||
__u16 frame_no; /* current frame number */ |
||||
__u16 pad1; /* set to 0 on each frame_no change */ |
||||
__u32 done_head; /* info returned for an interrupt */ |
||||
u8 reserved_for_hc[116]; |
||||
} __attribute((aligned(256))); |
||||
|
||||
|
||||
/*
|
||||
* Maximum number of root hub ports. |
||||
*/ |
||||
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ |
||||
|
||||
/*
|
||||
* This is the structure of the OHCI controller's memory mapped I/O |
||||
* region. This is Memory Mapped I/O. You must use the readl() and |
||||
* writel() macros defined in asm/io.h to access these!! |
||||
*/ |
||||
struct ohci_regs { |
||||
/* control and status registers */ |
||||
__u32 revision; |
||||
__u32 control; |
||||
__u32 cmdstatus; |
||||
__u32 intrstatus; |
||||
__u32 intrenable; |
||||
__u32 intrdisable; |
||||
/* memory pointers */ |
||||
__u32 hcca; |
||||
__u32 ed_periodcurrent; |
||||
__u32 ed_controlhead; |
||||
__u32 ed_controlcurrent; |
||||
__u32 ed_bulkhead; |
||||
__u32 ed_bulkcurrent; |
||||
__u32 donehead; |
||||
/* frame counters */ |
||||
__u32 fminterval; |
||||
__u32 fmremaining; |
||||
__u32 fmnumber; |
||||
__u32 periodicstart; |
||||
__u32 lsthresh; |
||||
/* Root hub ports */ |
||||
struct ohci_roothub_regs { |
||||
__u32 a; |
||||
__u32 b; |
||||
__u32 status; |
||||
__u32 portstatus[MAX_ROOT_PORTS]; |
||||
} roothub; |
||||
} __attribute((aligned(32))); |
||||
|
||||
|
||||
/* OHCI CONTROL AND STATUS REGISTER MASKS */ |
||||
|
||||
/*
|
||||
* HcControl (control) register masks |
||||
*/ |
||||
#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
||||
#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
||||
#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
||||
#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
||||
#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
||||
#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
||||
#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
||||
#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
||||
#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
||||
|
||||
/* pre-shifted values for HCFS */ |
||||
# define OHCI_USB_RESET (0 << 6) |
||||
# define OHCI_USB_RESUME (1 << 6) |
||||
# define OHCI_USB_OPER (2 << 6) |
||||
# define OHCI_USB_SUSPEND (3 << 6) |
||||
|
||||
/*
|
||||
* HcCommandStatus (cmdstatus) register masks |
||||
*/ |
||||
#define OHCI_HCR (1 << 0) /* host controller reset */ |
||||
#define OHCI_CLF (1 << 1) /* control list filled */ |
||||
#define OHCI_BLF (1 << 2) /* bulk list filled */ |
||||
#define OHCI_OCR (1 << 3) /* ownership change request */ |
||||
#define OHCI_SOC (3 << 16) /* scheduling overrun count */ |
||||
|
||||
/*
|
||||
* masks used with interrupt registers: |
||||
* HcInterruptStatus (intrstatus) |
||||
* HcInterruptEnable (intrenable) |
||||
* HcInterruptDisable (intrdisable) |
||||
*/ |
||||
#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
||||
#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
||||
#define OHCI_INTR_SF (1 << 2) /* start frame */ |
||||
#define OHCI_INTR_RD (1 << 3) /* resume detect */ |
||||
#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
||||
#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
||||
#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
||||
#define OHCI_INTR_OC (1 << 30) /* ownership change */ |
||||
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
||||
|
||||
|
||||
/* Virtual Root HUB */ |
||||
struct virt_root_hub { |
||||
int devnum; /* Address of Root Hub endpoint */ |
||||
void *dev; /* was urb */ |
||||
void *int_addr; |
||||
int send; |
||||
int interval; |
||||
}; |
||||
|
||||
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ |
||||
|
||||
/* destination of request */ |
||||
#define RH_INTERFACE 0x01 |
||||
#define RH_ENDPOINT 0x02 |
||||
#define RH_OTHER 0x03 |
||||
|
||||
#define RH_CLASS 0x20 |
||||
#define RH_VENDOR 0x40 |
||||
|
||||
/* Requests: bRequest << 8 | bmRequestType */ |
||||
#define RH_GET_STATUS 0x0080 |
||||
#define RH_CLEAR_FEATURE 0x0100 |
||||
#define RH_SET_FEATURE 0x0300 |
||||
#define RH_SET_ADDRESS 0x0500 |
||||
#define RH_GET_DESCRIPTOR 0x0680 |
||||
#define RH_SET_DESCRIPTOR 0x0700 |
||||
#define RH_GET_CONFIGURATION 0x0880 |
||||
#define RH_SET_CONFIGURATION 0x0900 |
||||
#define RH_GET_STATE 0x0280 |
||||
#define RH_GET_INTERFACE 0x0A80 |
||||
#define RH_SET_INTERFACE 0x0B00 |
||||
#define RH_SYNC_FRAME 0x0C80 |
||||
/* Our Vendor Specific Request */ |
||||
#define RH_SET_EP 0x2000 |
||||
|
||||
|
||||
/* Hub port features */ |
||||
#define RH_PORT_CONNECTION 0x00 |
||||
#define RH_PORT_ENABLE 0x01 |
||||
#define RH_PORT_SUSPEND 0x02 |
||||
#define RH_PORT_OVER_CURRENT 0x03 |
||||
#define RH_PORT_RESET 0x04 |
||||
#define RH_PORT_POWER 0x08 |
||||
#define RH_PORT_LOW_SPEED 0x09 |
||||
|
||||
#define RH_C_PORT_CONNECTION 0x10 |
||||
#define RH_C_PORT_ENABLE 0x11 |
||||
#define RH_C_PORT_SUSPEND 0x12 |
||||
#define RH_C_PORT_OVER_CURRENT 0x13 |
||||
#define RH_C_PORT_RESET 0x14 |
||||
|
||||
/* Hub features */ |
||||
#define RH_C_HUB_LOCAL_POWER 0x00 |
||||
#define RH_C_HUB_OVER_CURRENT 0x01 |
||||
|
||||
#define RH_DEVICE_REMOTE_WAKEUP 0x00 |
||||
#define RH_ENDPOINT_STALL 0x01 |
||||
|
||||
#define RH_ACK 0x01 |
||||
#define RH_REQ_ERR -1 |
||||
#define RH_NACK 0x00 |
||||
|
||||
|
||||
/* OHCI ROOT HUB REGISTER MASKS */ |
||||
|
||||
/* roothub.portstatus [i] bits */ |
||||
#define RH_PS_CCS 0x00000001 /* current connect status */ |
||||
#define RH_PS_PES 0x00000002 /* port enable status*/ |
||||
#define RH_PS_PSS 0x00000004 /* port suspend status */ |
||||
#define RH_PS_POCI 0x00000008 /* port over current indicator */ |
||||
#define RH_PS_PRS 0x00000010 /* port reset status */ |
||||
#define RH_PS_PPS 0x00000100 /* port power status */ |
||||
#define RH_PS_LSDA 0x00000200 /* low speed device attached */ |
||||
#define RH_PS_CSC 0x00010000 /* connect status change */ |
||||
#define RH_PS_PESC 0x00020000 /* port enable status change */ |
||||
#define RH_PS_PSSC 0x00040000 /* port suspend status change */ |
||||
#define RH_PS_OCIC 0x00080000 /* over current indicator change */ |
||||
#define RH_PS_PRSC 0x00100000 /* port reset status change */ |
||||
|
||||
/* roothub.status bits */ |
||||
#define RH_HS_LPS 0x00000001 /* local power status */ |
||||
#define RH_HS_OCI 0x00000002 /* over current indicator */ |
||||
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ |
||||
#define RH_HS_LPSC 0x00010000 /* local power status change */ |
||||
#define RH_HS_OCIC 0x00020000 /* over current indicator change */ |
||||
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ |
||||
|
||||
/* roothub.b masks */ |
||||
#define RH_B_DR 0x0000ffff /* device removable flags */ |
||||
#define RH_B_PPCM 0xffff0000 /* port power control mask */ |
||||
|
||||
/* roothub.a masks */ |
||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */ |
||||
#define RH_A_PSM (1 << 8) /* power switching mode */ |
||||
#define RH_A_NPS (1 << 9) /* no power switching */ |
||||
#define RH_A_DT (1 << 10) /* device type (mbz) */ |
||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */ |
||||
#define RH_A_NOCP (1 << 12) /* no over current protection */ |
||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
||||
|
||||
/* urb */ |
||||
#define N_URB_TD 48 |
||||
typedef struct |
||||
{ |
||||
ed_t *ed; |
||||
__u16 length; /* number of tds associated with this request */ |
||||
__u16 td_cnt; /* number of tds already serviced */ |
||||
int state; |
||||
unsigned long pipe; |
||||
int actual_length; |
||||
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ |
||||
} urb_priv_t; |
||||
#define URB_DEL 1 |
||||
|
||||
/*
|
||||
* This is the full ohci controller description |
||||
* |
||||
* Note how the "proper" USB information is just |
||||
* a subset of what the full implementation needs. (Linus) |
||||
*/ |
||||
|
||||
|
||||
typedef struct ohci { |
||||
struct ohci_hcca *hcca; /* hcca */ |
||||
/*dma_addr_t hcca_dma;*/ |
||||
|
||||
int irq; |
||||
int disabled; /* e.g. got a UE, we're hung */ |
||||
int sleeping; |
||||
unsigned long flags; /* for HC bugs */ |
||||
|
||||
struct ohci_regs *regs; /* OHCI controller's memory */ |
||||
|
||||
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ |
||||
ed_t *ed_bulktail; /* last endpoint of bulk list */ |
||||
ed_t *ed_controltail; /* last endpoint of control list */ |
||||
int intrstatus; |
||||
__u32 hc_control; /* copy of the hc control reg */ |
||||
struct usb_device *dev[32]; |
||||
struct virt_root_hub rh; |
||||
|
||||
const char *slot_name; |
||||
} ohci_t; |
||||
|
||||
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ |
||||
|
||||
struct ohci_device { |
||||
ed_t ed[NUM_EDS]; |
||||
int ed_cnt; |
||||
}; |
||||
|
||||
/* hcd */ |
||||
/* endpoint */ |
||||
static int ep_link(ohci_t * ohci, ed_t * ed); |
||||
static int ep_unlink(ohci_t * ohci, ed_t * ed); |
||||
static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); |
||||
|
||||
/*-------------------------------------------------------------------------*/ |
||||
|
||||
/* we need more TDs than EDs */ |
||||
#define NUM_TD 64 |
||||
|
||||
/* +1 so we can align the storage */ |
||||
td_t gtd[NUM_TD+1]; |
||||
/* pointers to aligned storage */ |
||||
td_t *ptd; |
||||
|
||||
/* TDs ... */ |
||||
static inline struct td * |
||||
td_alloc (struct usb_device *usb_dev) |
||||
{ |
||||
int i; |
||||
struct td *td; |
||||
|
||||
td = NULL; |
||||
for (i = 0; i < NUM_TD; i++) { |
||||
if (ptd[i].usb_dev == NULL) { |
||||
td = &ptd[i]; |
||||
td->usb_dev = usb_dev; |
||||
break; |
||||
} |
||||
} |
||||
return td; |
||||
} |
||||
|
||||
static inline void |
||||
ed_free (struct ed *ed) |
||||
{ |
||||
ed->usb_dev = NULL; |
||||
} |
||||
@ -0,0 +1,189 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the dbau1x00 board. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ |
||||
#define CONFIG_PB1X00 1 |
||||
#define CONFIG_AU1X00 1 /* alchemy series cpu */ |
||||
|
||||
#ifdef CONFIG_PB1000 |
||||
#define CONFIG_AU1000 1 |
||||
#else |
||||
#ifdef CONFIG_PB1100 |
||||
#define CONFIG_AU1100 1 |
||||
#else |
||||
#ifdef CONFIG_PB1500 |
||||
#define CONFIG_AU1500 1 |
||||
#else |
||||
#error "No valid board set" |
||||
#endif |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ |
||||
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"addmisc=setenv bootargs $(bootargs) " \
|
||||
"console=ttyS0,$(baudrate) " \
|
||||
"panic=1\0" \
|
||||
"bootfile=/vmlinux.img\0" \
|
||||
"load=tftp 80500000 $(u-boot)\0" \
|
||||
"" |
||||
/* Boot from NFS root */ |
||||
#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; bootm" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args*/ |
||||
|
||||
#define CFG_MALLOC_LEN 128*1024 |
||||
|
||||
#define CFG_BOOTPARAMS_LEN 128*1024 |
||||
|
||||
#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ |
||||
|
||||
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x81000000 /* default load address */ |
||||
|
||||
#define CFG_MEMTEST_START 0x80100000 |
||||
#undef CFG_MEMTEST_START |
||||
#define CFG_MEMTEST_START 0x80200000 |
||||
#define CFG_MEMTEST_END 0x83800000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
||||
|
||||
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ |
||||
|
||||
/* The following #defines are needed to get flash environment right */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (192 << 10) |
||||
|
||||
#define CFG_INIT_SP_OFFSET 0x4000000 |
||||
|
||||
/* We boot from this flash, selected with dip switch */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_2 |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CFG_ENV_IS_NOWHERE 1 |
||||
|
||||
/* Address and size of Primary Environment Sector */ |
||||
#define CFG_ENV_ADDR 0xB0030000 |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
|
||||
#define CONFIG_FLASH_16BIT |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 2 |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
|
||||
#define CONFIG_MEMSIZE_IN_BYTES |
||||
|
||||
|
||||
/*---USB -------------------------------------------*/ |
||||
#if 0 |
||||
#define CONFIG_USB_OHCI |
||||
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_DOS_PARTITION |
||||
#else |
||||
#define ADD_USB_CMD 0 |
||||
#endif |
||||
|
||||
/*---ATA PCMCIA ------------------------------------*/ |
||||
#if 0 |
||||
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
||||
#define CFG_PCMCIA_MEM_ADDR 0x20000000 |
||||
#define CONFIG_PCMCIA_SLOT_A |
||||
|
||||
#define CONFIG_ATAPI 1 |
||||
#define CONFIG_MAC_PARTITION 1 |
||||
|
||||
/* We run CF in "true ide" mode or a harddrive via pcmcia */ |
||||
#define CONFIG_IDE_PCMCIA 1 |
||||
|
||||
/* We only support one slot for now */ |
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET 8 |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET 0 |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 |
||||
#define CFG_ICACHE_SIZE 16384 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
|
||||
#define CONFIG_COMMANDS \ |
||||
(((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
|
||||
CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
|
||||
CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue