This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>master
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/*
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* From Coreboot |
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* |
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* Copyright (C) 2007-2010 coresystems GmbH |
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* Copyright (C) 2011 Google Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <asm/io.h> |
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#include <asm/pci.h> |
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#include <asm/arch/pch.h> |
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#include <asm/arch/sandybridge.h> |
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static void sandybridge_setup_northbridge_bars(struct udevice *dev) |
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{ |
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/* Set up all hardcoded northbridge BARs */ |
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debug("Setting up static registers\n"); |
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dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); |
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dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); |
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dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1); |
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dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); |
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/* 64MB - busses 0-63 */ |
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dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); |
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dm_pci_write_config32(dev, PCIEXBAR + 4, |
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(0LL + DEFAULT_PCIEXBAR) >> 32); |
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dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); |
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dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); |
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/* Set C0000-FFFFF to access RAM on both reads and writes */ |
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dm_pci_write_config8(dev, PAM0, 0x30); |
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dm_pci_write_config8(dev, PAM1, 0x33); |
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dm_pci_write_config8(dev, PAM2, 0x33); |
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dm_pci_write_config8(dev, PAM3, 0x33); |
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dm_pci_write_config8(dev, PAM4, 0x33); |
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dm_pci_write_config8(dev, PAM5, 0x33); |
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dm_pci_write_config8(dev, PAM6, 0x33); |
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} |
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static int bd82x6x_northbridge_probe(struct udevice *dev) |
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{ |
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const int chipset_type = SANDYBRIDGE_MOBILE; |
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u32 capid0_a; |
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u8 reg8; |
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if (gd->flags & GD_FLG_RELOC) |
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return 0; |
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/* Device ID Override Enable should be done very early */ |
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dm_pci_read_config32(dev, 0xe4, &capid0_a); |
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if (capid0_a & (1 << 10)) { |
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dm_pci_read_config8(dev, 0xf3, ®8); |
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reg8 &= ~7; /* Clear 2:0 */ |
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if (chipset_type == SANDYBRIDGE_MOBILE) |
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reg8 |= 1; /* Set bit 0 */ |
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dm_pci_write_config8(dev, 0xf3, reg8); |
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} |
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sandybridge_setup_northbridge_bars(dev); |
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/* Device Enable */ |
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dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); |
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return 0; |
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} |
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static const struct udevice_id bd82x6x_northbridge_ids[] = { |
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{ .compatible = "intel,bd82x6x-northbridge" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(bd82x6x_northbridge_drv) = { |
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.name = "bd82x6x_northbridge", |
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.id = UCLASS_NORTHBRIDGE, |
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.of_match = bd82x6x_northbridge_ids, |
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.probe = bd82x6x_northbridge_probe, |
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}; |
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