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pm9263 converted to at91 soc access

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Signed-off-by: Asen Dimov <dimov@ronetix.at>
master
Asen Dimov 15 years ago committed by trix
parent 000b6dc6ed
commit 28897f9072
3 changed files with 152 additions and 145 deletions
  1. 15
      board/ronetix/pm9263/led.c
  2. 195
      board/ronetix/pm9263/pm9263.c
  3. 87
      include/configs/pm9263.h

15
board/ronetix/pm9263/led.c
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@ -26,18 +26,19 @@
#include <common.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/io.h>
void coloured_LED_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB |
1 << AT91SAM9263_ID_PIOCDE);
writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_pio_output(CONFIG_RED_LED, 1);
at91_set_pio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_pio_value(CONFIG_RED_LED, 0);
at91_set_pio_value(CONFIG_GREEN_LED, 1);
}

195
board/ronetix/pm9263/pm9263.c
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@ -27,13 +27,13 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
@ -55,52 +55,59 @@ DECLARE_GLOBAL_DATA_PTR;
static void pm9263_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 */
csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
at91_sys_write(AT91_MATRIX_EBI0CSA,
csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_TDF_(2));
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void pm9263_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@ -110,19 +117,15 @@ static void pm9263_macb_hw_init(void)
*
* PHY has internal pull-down
*/
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PC25),
pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
writel(pin_to_mask(AT91_PIN_PE25) |
pin_to_mask(AT91_PIN_PE26),
pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
at91_macb_hw_init();
}
@ -148,17 +151,17 @@ vidinfo_t panel_info = {
void lcd_enable(void)
{
at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
}
void lcd_disable(void)
{
at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
}
#ifdef CONFIG_LCD_IN_PSRAM
#define PSRAM_CRE_PIN AT91_PIN_PB29
#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
/* Initialize the PSRAM memory */
@ -166,31 +169,34 @@ static int pm9263_lcd_hw_psram_init(void)
{
volatile uint16_t x;
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE;
at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 3.3v, no pull-ups */
csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
at91_sys_write(AT91_MATRIX_EBI1CSA,
csa | AT91_MATRIX_EBI1_DBPUC |
AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
writel(csa, &matrix->csa[1]);
/* Configure SMC1 CS0 for PSRAM - 16-bit */
at91_sys_write(AT91_SMC1_SETUP(0),
AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
at91_sys_write(AT91_SMC1_PULSE(0),
AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
at91_sys_write(AT91_SMC1_CYCLE(0),
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
at91_sys_write(AT91_SMC1_MODE(0),
AT91_SMC_DBW_16 |
AT91_SMC_PMEN |
AT91_SMC_PS_32);
writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[0].setup);
writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
&smc->cs[0].pulse);
writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
&smc->cs[0].cycle);
writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
&smc->cs[0].mode);
/* setup PB29 as output */
at91_set_gpio_output(PSRAM_CRE_PIN, 1);
at91_set_pio_output(PSRAM_CRE_PIN, 1);
at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
/* PSRAM: write BCR */
x = readw(PSRAM_CTRL_REG);
@ -216,7 +222,7 @@ static int pm9263_lcd_hw_psram_init(void)
/* test if the chip is MT45W2M16B */
if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
/* try with CRE=1 (MT45W2M16A) */
at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
/* write RCR of the PSRAM */
x = readw(PSRAM_CTRL_REG);
@ -229,17 +235,14 @@ static int pm9263_lcd_hw_psram_init(void)
writew(0x1234, PHYS_PSRAM);
writew(0x5678, PHYS_PSRAM+2);
if ((readw(PHYS_PSRAM) != 0x1234)
|| (readw(PHYS_PSRAM + 2) != 0x5678))
|| (readw(PHYS_PSRAM + 2) != 0x5678))
return 1;
}
/* Bus matrix */
at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
AT91_MATRIX_DEFMSTR_TYPE_FIXED |
(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
return 0;
}
@ -247,35 +250,37 @@ static int pm9263_lcd_hw_psram_init(void)
static void pm9263_lcd_hw_init(void)
{
at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
/* Power Control */
at91_set_gpio_output(AT91_PIN_PA22, 1);
at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
#ifdef CONFIG_LCD_IN_PSRAM
/* initialize te PSRAM */
@ -337,13 +342,15 @@ void lcd_show_board_info(void)
int board_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable Ctrlc */
console_init_f();
at91_sys_write(AT91_PMC_PCER,
(1 << AT91SAM9263_ID_PIOA) |
(1 << AT91SAM9263_ID_PIOCDE) |
(1 << AT91SAM9263_ID_PIOB));
writel((1 << AT91SAM9263_ID_PIOA) |
(1 << AT91SAM9263_ID_PIOCDE) |
(1 << AT91SAM9263_ID_PIOB),
&pmc->pcer);
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9263;
@ -394,7 +401,7 @@ int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
#endif
return rc;
}

87
include/configs/pm9263.h
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@ -28,8 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@ -49,41 +47,37 @@
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(AT91_PMC_MOR_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
AT91_PMC_PLLXR_OUT(3) | \
AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91RM9200_PMC_MDIV_3 | \
AT91_PMC_PDIV_1)
(AT91_PMC_MCKR_CSS_SLOW | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91RM9200_PMC_MDIV_3 | \
AT91_PMC_PDIV_1)
(AT91_PMC_MCKR_CSS_PLLA | \
AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_4)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
@ -91,8 +85,8 @@
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
AT91_MATRIX_EBI0_CS1A_SDRAMC)
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
@ -135,32 +129,32 @@
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | \
AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \
AT91_RSTC_RSTTYP_WATCHDOG)
AT91_RSTC_CR_PROCRST | \
AT91_RSTC_MR_ERSTL(1) | \
AT91_RSTC_MR_ERSTL(2))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
AT91_WDT_WDV | \
AT91_WDT_WDDIS | \
AT91_WDT_WDD)
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
AT91_WDT_MR_WDD(0xfff))
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
@ -196,8 +190,8 @@
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */
#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */
#define CONFIG_BOOTDELAY 3
@ -258,8 +252,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
#endif
@ -273,6 +267,11 @@
/* PSRAM */
#define PHYS_PSRAM 0x70000000
#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
/* Slave EBI1, PSRAM connected */
#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
AT91_MATRIX_SCFG_SLOT_CYCLE(255))
/* Ethernet */
#define CONFIG_MACB 1

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