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@ -440,6 +440,7 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) |
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struct armdfec_device *darmdfec = to_darmdfec(dev); |
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struct armdfec_reg *regs = darmdfec->regs; |
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int phy_adr; |
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u32 temp; |
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armdfec_init_rx_desc_ring(darmdfec); |
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@ -479,9 +480,12 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd) |
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update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); |
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/* Update TX and RX queue descriptor register */ |
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writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]); |
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writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]); |
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writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]); |
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temp = (u32)®s->txcdp[TXQ]; |
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writel((u32)darmdfec->p_txdesc, temp); |
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temp = (u32)®s->rxfdp[RXQ]; |
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writel((u32)darmdfec->p_rxdesc, temp); |
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temp = (u32)®s->rxcdp[RXQ]; |
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writel((u32)darmdfec->p_rxdesc_curr, temp); |
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/* Enable Interrupts */ |
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writel(ALL_INTS, ®s->im); |
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@ -614,6 +618,7 @@ static int armdfec_recv(struct eth_device *dev) |
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struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; |
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u32 cmd_sts; |
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u32 timeout = 0; |
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u32 temp; |
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/* wait untill rx packet available or timeout */ |
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do { |
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@ -667,7 +672,8 @@ static int armdfec_recv(struct eth_device *dev) |
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p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; |
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p_rxdesc_curr->byte_cnt = 0; |
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writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr); |
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temp = (u32)&darmdfec->p_rxdesc_curr; |
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writel((u32)p_rxdesc_curr->nxtdesc_p, temp); |
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return 0; |
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} |
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