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@ -29,57 +29,109 @@ |
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#define IBR_HDR_UART_ID 0x69 |
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#define IBR_DEF_ATTRIB 0x00 |
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enum kwbimage_cmd { |
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CMD_INVALID, |
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CMD_BOOT_FROM, |
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CMD_NAND_ECC_MODE, |
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CMD_NAND_PAGE_SIZE, |
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CMD_SATA_PIO_MODE, |
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CMD_DDR_INIT_DELAY, |
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CMD_DATA |
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}; |
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#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1)) |
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enum kwbimage_cmd_types { |
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CFG_INVALID = -1, |
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CFG_COMMAND, |
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CFG_DATA0, |
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CFG_DATA1 |
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}; |
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/* typedefs */ |
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typedef struct bhr_t { |
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uint8_t blockid; /*0 */ |
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uint8_t nandeccmode; /*1 */ |
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/* Structure of the main header, version 0 (Kirkwood, Dove) */ |
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struct main_hdr_v0 { |
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uint8_t blockid; /*0 */ |
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uint8_t nandeccmode; /*1 */ |
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uint16_t nandpagesize; /*2-3 */ |
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uint32_t blocksize; /*4-7 */ |
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uint32_t rsvd1; /*8-11 */ |
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uint32_t srcaddr; /*12-15 */ |
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uint32_t destaddr; /*16-19 */ |
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uint32_t execaddr; /*20-23 */ |
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uint8_t satapiomode; /*24 */ |
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uint8_t rsvd3; /*25 */ |
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uint8_t satapiomode; /*24 */ |
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uint8_t rsvd3; /*25 */ |
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uint16_t ddrinitdelay; /*26-27 */ |
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uint16_t rsvd2; /*28-29 */ |
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uint8_t ext; /*30 */ |
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uint8_t checkSum; /*31 */ |
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} bhr_t, *pbhr_t; |
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uint8_t ext; /*30 */ |
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uint8_t checksum; /*31 */ |
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}; |
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struct reg_config { |
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struct ext_hdr_v0_reg { |
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uint32_t raddr; |
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uint32_t rdata; |
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}; |
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typedef struct extbhr_t { |
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uint32_t dramregsoffs; |
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uint8_t rsrvd1[0x20 - sizeof(uint32_t)]; |
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struct reg_config rcfg[KWBIMAGE_MAX_CONFIG]; |
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uint8_t rsrvd2[7]; |
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uint8_t checkSum; |
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} extbhr_t, *pextbhr_t; |
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#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) |
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struct ext_hdr_v0 { |
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uint32_t offset; |
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uint8_t reserved[0x20 - sizeof(uint32_t)]; |
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struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; |
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uint8_t reserved2[7]; |
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uint8_t checksum; |
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}; |
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struct kwb_header { |
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bhr_t kwb_hdr; |
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extbhr_t kwb_exthdr; |
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struct main_hdr_v0 kwb_hdr; |
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struct ext_hdr_v0 kwb_exthdr; |
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}; |
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/* Structure of the main header, version 1 (Armada 370, Armada XP) */ |
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struct main_hdr_v1 { |
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uint8_t blockid; /* 0 */ |
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uint8_t reserved1; /* 1 */ |
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uint16_t reserved2; /* 2-3 */ |
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uint32_t blocksize; /* 4-7 */ |
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uint8_t version; /* 8 */ |
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uint8_t headersz_msb; /* 9 */ |
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uint16_t headersz_lsb; /* A-B */ |
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uint32_t srcaddr; /* C-F */ |
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uint32_t destaddr; /* 10-13 */ |
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uint32_t execaddr; /* 14-17 */ |
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uint8_t reserved3; /* 18 */ |
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uint8_t nandblocksize; /* 19 */ |
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uint8_t nandbadblklocation; /* 1A */ |
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uint8_t reserved4; /* 1B */ |
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uint16_t reserved5; /* 1C-1D */ |
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uint8_t ext; /* 1E */ |
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uint8_t checksum; /* 1F */ |
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}; |
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/*
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* Header for the optional headers, version 1 (Armada 370, Armada XP) |
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*/ |
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struct opt_hdr_v1 { |
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uint8_t headertype; |
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uint8_t headersz_msb; |
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uint16_t headersz_lsb; |
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char data[0]; |
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}; |
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/*
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* Various values for the opt_hdr_v1->headertype field, describing the |
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* different types of optional headers. The "secure" header contains |
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* informations related to secure boot (encryption keys, etc.). The |
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* "binary" header contains ARM binary code to be executed prior to |
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* executing the main payload (usually the bootloader). This is |
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* typically used to execute DDR3 training code. The "register" header |
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* allows to describe a set of (address, value) tuples that are |
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* generally used to configure the DRAM controller. |
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*/ |
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#define OPT_HDR_V1_SECURE_TYPE 0x1 |
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#define OPT_HDR_V1_BINARY_TYPE 0x2 |
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#define OPT_HDR_V1_REGISTER_TYPE 0x3 |
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#define KWBHEADER_V1_SIZE(hdr) \ |
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(((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb) |
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enum kwbimage_cmd { |
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CMD_INVALID, |
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CMD_BOOT_FROM, |
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CMD_NAND_ECC_MODE, |
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CMD_NAND_PAGE_SIZE, |
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CMD_SATA_PIO_MODE, |
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CMD_DDR_INIT_DELAY, |
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CMD_DATA |
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}; |
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enum kwbimage_cmd_types { |
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CFG_INVALID = -1, |
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CFG_COMMAND, |
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CFG_DATA0, |
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CFG_DATA1 |
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}; |
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/*
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@ -87,4 +139,15 @@ struct kwb_header { |
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*/ |
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void init_kwb_image_type (void); |
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/*
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* Byte 8 of the image header contains the version number. In the v0 |
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* header, byte 8 was reserved, and always set to 0. In the v1 header, |
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* byte 8 has been changed to a proper field, set to 1. |
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*/ |
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static inline unsigned int image_version(void *header) |
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{ |
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unsigned char *ptr = header; |
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return ptr[8]; |
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} |
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#endif /* _KWBIMAGE_H_ */ |
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