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@ -10,6 +10,7 @@ |
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#include <asm/io.h> |
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#include <common.h> |
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#include <asm/arch/ddr3.h> |
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#include <asm/arch/psc_defs.h> |
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void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) |
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{ |
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@ -86,3 +87,77 @@ void ddr3_reset_ddrphy(void) |
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tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; |
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__raw_writel(tmp, KS2_DDR3APLLCTL1); |
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} |
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#ifdef CONFIG_SOC_K2HK |
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/**
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* ddr3_reset_workaround - reset workaround in case if leveling error |
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* detected for PG 1.0 and 1.1 k2hk SoCs |
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*/ |
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void ddr3_err_reset_workaround(void) |
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{ |
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unsigned int tmp; |
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unsigned int tmp_a; |
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unsigned int tmp_b; |
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/*
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* Check for PGSR0 error bits of DDR3 PHY. |
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* Check for WLERR, QSGERR, WLAERR, |
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* RDERR, WDERR, REERR, WEERR error to see if they are set or not |
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*/ |
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tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); |
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tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); |
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if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) { |
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printf("DDR Leveling Error Detected!\n"); |
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printf("DDR3A PGSR0 = 0x%x\n", tmp_a); |
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printf("DDR3B PGSR0 = 0x%x\n", tmp_b); |
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/*
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* Write Keys to KICK registers to enable writes to registers |
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* in boot config space |
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*/ |
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__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); |
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__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); |
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/*
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* Move DDR3A Module out of reset isolation by setting |
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* MDCTL23[12] = 0 |
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*/ |
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tmp_a = __raw_readl(KS2_PSC_BASE + |
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); |
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tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0); |
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__raw_writel(tmp_a, KS2_PSC_BASE + |
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); |
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/*
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* Move DDR3B Module out of reset isolation by setting |
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* MDCTL24[12] = 0 |
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*/ |
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tmp_b = __raw_readl(KS2_PSC_BASE + |
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); |
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tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0); |
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__raw_writel(tmp_b, KS2_PSC_BASE + |
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PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); |
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/*
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* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes |
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* to RSTCTRL and RSTCFG |
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*/ |
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tmp = __raw_readl(KS2_RSTCTRL); |
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tmp &= KS2_RSTCTRL_MASK; |
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tmp |= KS2_RSTCTRL_KEY; |
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__raw_writel(tmp, KS2_RSTCTRL); |
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/*
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* Set PLL Controller to drive hard reset on SW trigger by |
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* setting RSTCFG[13] = 0 |
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*/ |
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tmp = __raw_readl(KS2_RSTCTRL_RSCFG); |
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tmp &= ~KS2_RSTYPE_PLL_SOFT; |
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__raw_writel(tmp, KS2_RSTCTRL_RSCFG); |
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reset_cpu(0); |
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} |
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} |
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#endif |
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