RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core from Rockchip. It is designed for varies application scenario such as car DVR, sports DV, secure camera and UAV camera. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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if ROCKCHIP_RV1108 |
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config SYS_SOC |
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default "rockchip" |
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config SYS_MALLOC_F_LEN |
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default 0x400 |
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endif |
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#
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# (C) Copyright 2016 Rockchip Electronics Co., Ltd
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifndef CONFIG_SPL_BUILD |
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obj-y += syscon_rv1108.o
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endif |
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obj-y += rv1108.o
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obj-y += clk_rv1108.o
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <syscon.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rv1108.h> |
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int rockchip_get_clk(struct udevice **devp) |
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{ |
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return uclass_get_device_by_driver(UCLASS_CLK, |
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DM_GET_DRIVER(clk_rv1108), devp); |
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} |
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void *rockchip_get_cru(void) |
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{ |
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struct rv1108_clk_priv *priv; |
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struct udevice *dev; |
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int ret; |
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ret = rockchip_get_clk(&dev); |
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if (ret) |
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return ERR_PTR(ret); |
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priv = dev_get_priv(dev); |
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return priv->cru; |
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} |
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#ifndef CONFIG_SYS_DCACHE_OFF |
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void enable_caches(void) |
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{ |
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/* Enable D-cache. I-cache is already enabled in start.S */ |
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dcache_enable(); |
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} |
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#endif |
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <syscon.h> |
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#include <asm/arch/clock.h> |
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static const struct udevice_id rv1108_syscon_ids[] = { |
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{ .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF }, |
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{ } |
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}; |
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U_BOOT_DRIVER(syscon_rv1108) = { |
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.name = "rv1108_syscon", |
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.id = UCLASS_SYSCON, |
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.of_match = rv1108_syscon_ids, |
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}; |
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd |
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* Author: Andy Yan <andy.yan@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <sysreset.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rv1108.h> |
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#include <asm/arch/hardware.h> |
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#include <linux/err.h> |
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int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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struct rv1108_cru *cru = rockchip_get_cru(); |
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if (IS_ERR(cru)) |
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return PTR_ERR(cru); |
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switch (type) { |
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case SYSRESET_WARM: |
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writel(0xeca8, &cru->glb_srst_snd_val); |
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break; |
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case SYSRESET_COLD: |
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writel(0xfdb9, &cru->glb_srst_fst_val); |
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break; |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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return -EINPROGRESS; |
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} |
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static struct sysreset_ops rv1108_sysreset = { |
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.request = rv1108_sysreset_request, |
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}; |
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U_BOOT_DRIVER(sysreset_rv1108) = { |
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.name = "rv1108_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &rv1108_sysreset, |
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}; |
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_RV1108_COMMON_H |
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#define __CONFIG_RV1108_COMMON_H |
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#include <asm/arch/hardware.h> |
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#include "rockchip-common.h" |
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#define CONFIG_ENV_IS_NOWHERE |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_MALLOC_LEN (32 << 20) |
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#define CONFIG_SYS_CBSIZE 1024 |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) |
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/* TIMER1,initialized by ddr initialize code */ |
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#define CONFIG_SYS_TIMER_BASE 0x10350020 |
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_MEM32 |
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#define CONFIG_SYS_SDRAM_BASE 0x60000000 |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) |
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) |
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#endif |
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