* Make 5200 reset command _really_ reset the board, without running any other code after it * Fix flash mapping and display on P3G4 board * Patch by Kyle Harris, 15 Jul 2003: - add support for Intel IXP425 CPU - add support for IXDP425 eval boardmaster
parent
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commit
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#
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# (C) Copyright 2000, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := ixdp425.o flash.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,2 @@ |
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#TEXT_BASE = 0x00100000
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TEXT_BASE = 0x00f00000
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@ -0,0 +1,427 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) x |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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|
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info); |
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static int write_data (flash_info_t * info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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void inline spin_wheel (void); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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break; |
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default: |
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panic ("configured to many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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/* Protect monitor and environment sectors
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*/ |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + _armboot_end_data - _armboot_start, |
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&flash_info[0]); |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F128J3A: |
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printf ("28F128J3A\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) INTEL_ID_28F128J3A: |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x02000000; |
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break; /* => 16 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
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} else { |
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printf ("\n"); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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*addr = (FPW) 0x00200020; /* erase setup */ |
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*addr = (FPW) 0x00D000D0; /* erase confirm */ |
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while (((status = |
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*addr) & (FPW) 0x00800080) != |
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(FPW) 0x00800080) { |
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if (get_timer_masked () > |
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CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = (FPW) 0x00B000B0; /* suspend erase */ |
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */ |
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rcode = 1; |
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break; |
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} |
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} |
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*addr = (FPW) 0x00500050; /* clear status register cmd. */ |
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*addr = (FPW) 0x00FF00FF; /* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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for (; i < port_width && cnt > 0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i = 0; i < port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) { |
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spin_wheel (); |
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count = 0; |
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} |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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return (write_data (info, wp, SWAP (data))); |
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} |
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|
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t * info, ulong dest, FPW data) |
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{ |
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FPWV *addr = (FPWV *) dest; |
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ulong status; |
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int flag; |
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|
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf ("not erased at %08lx (%lx)\n", (ulong) addr, |
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(ulong) * addr); |
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return (2); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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*addr = (FPW) 0x00400040; /* write setup */ |
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*addr = data; |
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|
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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|
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/* wait while polling the status register */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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|
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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|
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return (0); |
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} |
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|
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void inline spin_wheel (void) |
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{ |
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static int p = 0; |
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static char w[] = "\\/-"; |
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|
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printf ("\010%c", w[p]); |
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(++p == 3) ? (p = 0) : 0; |
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} |
@ -0,0 +1,76 @@ |
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/*
|
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* (C) Copyright 2002 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <asm/arch/ixp425.h> |
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#include <common.h> |
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|
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/* ------------------------------------------------------------------------- */ |
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|
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|
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/* local prototypes */ |
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|
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|
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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|
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int |
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/**********************************************************/ |
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board_post_init (void) |
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/**********************************************************/ |
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{ |
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return (0); |
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} |
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|
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int |
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/**********************************************************/ |
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board_init (void) |
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/**********************************************************/ |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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|
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/* arch number of IXDP */ |
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gd->bd->bi_arch_number = 245; |
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|
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0x00000100; |
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|
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return 0; |
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} |
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|
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int |
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/**********************************************************/ |
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dram_init (void) |
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/**********************************************************/ |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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|
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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|
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return (0); |
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} |
@ -0,0 +1,55 @@ |
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/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/ixp/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
armboot_end_data = .; |
||||
|
||||
. = ALIGN(4); |
||||
bss_start = .; |
||||
.bss : { *(.bss) } |
||||
bss_end = .; |
||||
|
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2000, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = serial.o interrupts.o cpu.o timer.o
|
||||
|
||||
all: .depend $(START) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,30 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
BIG_ENDIAN = y
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float -mbig-endian
|
||||
|
||||
PLATFORM_CPPFLAGS += -mbig-endian -mapcs-32 -march=armv4 -mtune=strongarm1100
|
@ -0,0 +1,160 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
int cpu_init (void) |
||||
{ |
||||
/*
|
||||
* setup up stack if necessary |
||||
*/ |
||||
/*
|
||||
|
||||
FIXME: the stack is _below_ the uboot code!! |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
IRQ_STACK_START = _armboot_end + |
||||
CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; |
||||
FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; |
||||
_armboot_real_end = FIQ_STACK_START + 4; |
||||
#else |
||||
_armboot_real_end = _armboot_end + CONFIG_STACKSIZE; |
||||
#endif |
||||
*/ |
||||
pci_init(); |
||||
return 0; |
||||
} |
||||
|
||||
int cleanup_before_linux (void) |
||||
{ |
||||
/*
|
||||
* this function is called just before we call linux |
||||
* it prepares the processor for linux |
||||
* |
||||
* just disable everything that can disturb booting linux |
||||
*/ |
||||
|
||||
unsigned long i; |
||||
|
||||
disable_interrupts (); |
||||
|
||||
/* turn off I-cache */ |
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||
i &= ~0x1000; |
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
||||
|
||||
/* flush I-cache */ |
||||
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
extern void reset_cpu (ulong addr); |
||||
|
||||
printf ("reseting ...\n"); |
||||
|
||||
udelay (50000); /* wait 50 ms */ |
||||
disable_interrupts (); |
||||
reset_cpu (0); |
||||
|
||||
/*NOTREACHED*/ |
||||
return (0); |
||||
} |
||||
|
||||
/* taken from blob */ |
||||
void icache_enable (void) |
||||
{ |
||||
register u32 i; |
||||
|
||||
/* read control register */ |
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||
|
||||
/* set i-cache */ |
||||
i |= 0x1000; |
||||
|
||||
/* write back to control register */ |
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
register u32 i; |
||||
|
||||
/* read control register */ |
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||
|
||||
/* clear i-cache */ |
||||
i &= ~0x1000; |
||||
|
||||
/* write back to control register */ |
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
||||
|
||||
/* flush i-cache */ |
||||
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
register u32 i; |
||||
|
||||
/* read control register */ |
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||
|
||||
/* return bit */ |
||||
return (i & 0x1000); |
||||
} |
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */ |
||||
void dcache_enable (void) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
void dcache_disable (void) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
int dcache_status (void) |
||||
{ |
||||
return 0; /* always off */ |
||||
} |
||||
|
||||
/* FIXME */ |
||||
void pci_init(void) |
||||
{ |
||||
return; |
||||
} |
@ -0,0 +1,161 @@ |
||||
/* vi: set ts=8 sw=8 noet: */ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
extern void reset_cpu (ulong addr); |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* enable IRQ/FIQ interrupts */ |
||||
void enable_interrupts (void) |
||||
{ |
||||
#error: interrupts not implemented yet |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts |
||||
* returns true if interrupts had been enabled before we disabled them |
||||
*/ |
||||
int disable_interrupts (void) |
||||
{ |
||||
#error: interrupts not implemented yet |
||||
} |
||||
#else |
||||
void enable_interrupts (void) |
||||
{ |
||||
return; |
||||
} |
||||
int disable_interrupts (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
|
||||
void bad_mode (void) |
||||
{ |
||||
panic ("Resetting CPU ...\n"); |
||||
reset_cpu (0); |
||||
} |
||||
|
||||
void show_regs (struct pt_regs *regs) |
||||
{ |
||||
unsigned long flags; |
||||
const char *processor_modes[] = { |
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26", |
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26", |
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26", |
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26", |
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32", |
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32", |
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32", |
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32" |
||||
}; |
||||
|
||||
flags = condition_codes (regs); |
||||
|
||||
printf ("pc : [<%08lx>] lr : [<%08lx>]\n" |
||||
"sp : %08lx ip : %08lx fp : %08lx\n", |
||||
instruction_pointer (regs), |
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); |
||||
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", |
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); |
||||
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); |
||||
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); |
||||
printf ("Flags: %c%c%c%c", |
||||
flags & CC_N_BIT ? 'N' : 'n', |
||||
flags & CC_Z_BIT ? 'Z' : 'z', |
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); |
||||
printf (" IRQs %s FIQs %s Mode %s%s\n", |
||||
interrupts_enabled (regs) ? "on" : "off", |
||||
fast_interrupts_enabled (regs) ? "on" : "off", |
||||
processor_modes[processor_mode (regs)], |
||||
thumb_mode (regs) ? " (T)" : ""); |
||||
} |
||||
|
||||
void do_undefined_instruction (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("undefined instruction\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_software_interrupt (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("software interrupt\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_prefetch_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("prefetch abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_data_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("data abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_not_used (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("not used\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_fiq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("fast interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_irq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
|
||||
int interrupt_init (void) |
||||
{ |
||||
/* nothing happens here - we don't setup any IRQs */ |
||||
return (0); |
||||
} |
@ -0,0 +1,125 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
void serial_setbrg (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
unsigned int quot = 0; |
||||
int uart = CFG_IXP425_CONSOLE; |
||||
|
||||
if (gd->baudrate == 1200) |
||||
quot = 192; |
||||
else if (gd->baudrate == 9600) |
||||
quot = 96; |
||||
else if (gd->baudrate == 19200) |
||||
quot = 48; |
||||
else if (gd->baudrate == 38400) |
||||
quot = 24; |
||||
else if (gd->baudrate == 57600) |
||||
quot = 16; |
||||
else if (gd->baudrate == 115200) |
||||
quot = 8; |
||||
else |
||||
hang (); |
||||
|
||||
IER(uart) = 0; /* Disable for now */ |
||||
FCR(uart) = 0; /* No fifos enabled */ |
||||
|
||||
/* set baud rate */ |
||||
LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; |
||||
DLL(uart) = quot & 0xff; |
||||
DLH(uart) = quot >> 8; |
||||
LCR(uart) = LCR_WLS0 | LCR_WLS1; |
||||
|
||||
IER(uart) = IER_UUE; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
* |
||||
*/ |
||||
int serial_init (void) |
||||
{ |
||||
serial_setbrg (); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
void serial_putc (const char c) |
||||
{ |
||||
/* wait for room in the tx FIFO on UART */ |
||||
while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0); |
||||
|
||||
THR(CFG_IXP425_CONSOLE) = c; |
||||
|
||||
/* If \n, also do \r */ |
||||
if (c == '\n') |
||||
serial_putc ('\r'); |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
int serial_tstc (void) |
||||
{ |
||||
return LSR(CFG_IXP425_CONSOLE) & LSR_DR; |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
int serial_getc (void) |
||||
{ |
||||
while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR)); |
||||
|
||||
return (char) RBR(CFG_IXP425_CONSOLE) & 0xff; |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) { |
||||
serial_putc (*s++); |
||||
} |
||||
} |
@ -0,0 +1,527 @@ |
||||
/* vi: set ts=8 sw=8 noet: */ |
||||
/* |
||||
* u-boot - Startup Code for XScale IXP |
||||
* |
||||
* Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
|
||||
* |
||||
* Based on startup code example contained in the |
||||
* Intel IXP4xx Programmer's Guide and past u-boot Start.S |
||||
* samples. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
#define MMU_Control_M 0x001 // Enable MMU |
||||
#define MMU_Control_A 0x002 // Enable address alignment faults |
||||
#define MMU_Control_C 0x004 // Enable cache |
||||
#define MMU_Control_W 0x008 // Enable write-buffer |
||||
#define MMU_Control_P 0x010 // Compatability: 32 bit code |
||||
#define MMU_Control_D 0x020 // Compatability: 32 bit data |
||||
#define MMU_Control_L 0x040 // Compatability: |
||||
#define MMU_Control_B 0x080 // Enable Big-Endian |
||||
#define MMU_Control_S 0x100 // Enable system protection |
||||
#define MMU_Control_R 0x200 // Enable ROM protection |
||||
#define MMU_Control_I 0x1000 // Enable Instruction cache |
||||
#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000 |
||||
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) |
||||
|
||||
|
||||
/* |
||||
* Macro definitions |
||||
*/ |
||||
// Delay a bit |
||||
.macro DELAY_FOR cycles, reg0 |
||||
ldr \reg0, =\cycles |
||||
subs \reg0, \reg0, #1 |
||||
subne pc, pc, #0xc |
||||
.endm |
||||
|
||||
// wait for coprocessor write complete |
||||
.macro CPWAIT reg |
||||
mrc p15,0,\reg,c2,c0,0 |
||||
mov \reg,\reg |
||||
sub pc,pc,#4 |
||||
.endm |
||||
|
||||
.globl _start
|
||||
_start: b reset |
||||
ldr pc, _undefined_instruction |
||||
ldr pc, _software_interrupt |
||||
ldr pc, _prefetch_abort |
||||
ldr pc, _data_abort |
||||
ldr pc, _not_used |
||||
ldr pc, _irq |
||||
ldr pc, _fiq |
||||
|
||||
_undefined_instruction: .word undefined_instruction |
||||
_software_interrupt: .word software_interrupt |
||||
_prefetch_abort: .word prefetch_abort |
||||
_data_abort: .word data_abort |
||||
_not_used: .word not_used |
||||
_irq: .word irq |
||||
_fiq: .word fiq |
||||
|
||||
.balignl 16,0xdeadbeef |
||||
|
||||
|
||||
/* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* do important init only if we don't start from memory! |
||||
* - relocate armboot to ram |
||||
* - setup stack |
||||
* - jump to second stage |
||||
*/ |
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start: |
||||
.word _start
|
||||
|
||||
/* |
||||
* Note: _armboot_end_data and _armboot_end are defined |
||||
* by the (board-dependent) linker script. |
||||
* _armboot_end_data is the first usable FLASH address after armboot |
||||
*/ |
||||
.globl _armboot_end_data
|
||||
_armboot_end_data: |
||||
.word armboot_end_data
|
||||
.globl _armboot_end
|
||||
_armboot_end: |
||||
.word armboot_end
|
||||
|
||||
/* |
||||
* This is defined in the board specific linker script |
||||
*/ |
||||
.globl _bss_start
|
||||
_bss_start: |
||||
.word bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end: |
||||
.word bss_end
|
||||
|
||||
/* |
||||
* _armboot_real_end is the first usable RAM address behind armboot |
||||
* and the various stacks |
||||
*/ |
||||
.globl _armboot_real_end
|
||||
_armboot_real_end: |
||||
.word 0x0badc0de
|
||||
|
||||
/* |
||||
* We relocate uboot to this address (end of RAM - 128 KiB) |
||||
*/ |
||||
.globl _uboot_reloc
|
||||
_uboot_reloc: |
||||
.word TEXT_BASE
|
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
#endif |
||||
|
||||
/****************************************************************************/ |
||||
/* */ |
||||
/* the actual reset code */ |
||||
/* */ |
||||
/****************************************************************************/ |
||||
|
||||
reset: |
||||
/* disable mmu, set big-endian */ |
||||
mov r0, #0xf8 |
||||
mcr p15, 0, r0, c1, c0, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* invalidate I & D caches & BTB */ |
||||
mcr p15, 0, r0, c7, c7, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* invalidate I & Data TLB */ |
||||
mcr p15, 0, r0, c8, c7, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* drain write and fill buffers */ |
||||
mcr p15, 0, r0, c7, c10, 4 |
||||
CPWAIT r0 |
||||
|
||||
/* disable write buffer coalescing */ |
||||
mrc p15, 0, r0, c1, c0, 1 |
||||
orr r0, r0, #1 |
||||
mcr p15, 0, r0, c1, c0, 1 |
||||
CPWAIT r0 |
||||
|
||||
/* set EXP CS0 to the optimum timing */ |
||||
ldr r1, =CFG_EXP_CS0 |
||||
ldr r2, =IXP425_EXP_CS0 |
||||
str r1, [r2] |
||||
|
||||
/* make sure flash is visible at 0 */ |
||||
ldr r2, =IXP425_EXP_CFG0 |
||||
ldr r1, [r2] |
||||
orr r1, r1, #0x80000000 |
||||
str r1, [r2] |
||||
|
||||
mov r1, #CFG_SDR_CONFIG |
||||
ldr r2, =IXP425_SDR_CONFIG |
||||
str r1, [r2] |
||||
|
||||
/* disable refresh cycles */ |
||||
mov r1, #0 |
||||
ldr r3, =IXP425_SDR_REFRESH |
||||
str r1, [r3] |
||||
|
||||
/* send nop command */ |
||||
mov r1, #3 |
||||
ldr r4, =IXP425_SDR_IR |
||||
str r1, [r4] |
||||
DELAY_FOR 0x4000, r0 |
||||
|
||||
/* set SDRAM internal refresh val */ |
||||
ldr r1, =CFG_SDRAM_REFRESH_CNT |
||||
str r1, [r3] |
||||
DELAY_FOR 0x4000, r0 |
||||
|
||||
/* send precharge-all command to close all open banks */ |
||||
mov r1, #2 |
||||
str r1, [r4] |
||||
DELAY_FOR 0x4000, r0 |
||||
|
||||
/* provide 8 auto-refresh cycles */ |
||||
mov r1, #4 |
||||
mov r5, #8 |
||||
111: str r1, [r4] |
||||
DELAY_FOR 0x100, r0 |
||||
subs r5, r5, #1 |
||||
bne 111b |
||||
|
||||
/* set mode register in sdram */ |
||||
mov r1, #1 |
||||
str r1, [r4] |
||||
DELAY_FOR 0x4000, r0 |
||||
|
||||
/* send normal operation command */ |
||||
mov r1, #6 |
||||
str r1, [r4] |
||||
DELAY_FOR 0x4000, r0 |
||||
|
||||
/* copy */ |
||||
mov r0, #0 |
||||
mov r4, r0 |
||||
add r2, r0, #0x40000 |
||||
mov r1, #0x10000000 |
||||
mov r5, r1 |
||||
|
||||
30: |
||||
ldr r3, [r0], #4 |
||||
str r3, [r1], #4 |
||||
cmp r0, r2 |
||||
bne 30b |
||||
|
||||
/* invalidate I & D caches & BTB */ |
||||
mcr p15, 0, r0, c7, c7, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* invalidate I & Data TLB */ |
||||
mcr p15, 0, r0, c8, c7, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* drain write and fill buffers */ |
||||
mcr p15, 0, r0, c7, c10, 4 |
||||
CPWAIT r0 |
||||
|
||||
/* move flash to 0x50000000 */ |
||||
ldr r2, =IXP425_EXP_CFG0 |
||||
ldr r1, [r2] |
||||
bic r1, r1, #0x80000000 |
||||
str r1, [r2] |
||||
|
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
/* invalidate I & Data TLB */ |
||||
mcr p15, 0, r0, c8, c7, 0 |
||||
CPWAIT r0 |
||||
|
||||
/* enable I cache */ |
||||
mrc p15, 0, r0, c1, c0, 0 |
||||
orr r0, r0, #MMU_Control_I |
||||
mcr p15, 0, r0, c1, c0, 0 |
||||
CPWAIT r0 |
||||
|
||||
mrs r0,cpsr /* set the cpu to SVC32 mode */ |
||||
bic r0,r0,#0x1f /* (superviser mode, M=10011) */ |
||||
orr r0,r0,#0x13 |
||||
msr cpsr,r0 |
||||
|
||||
relocate: /* relocate U-Boot to RAM */ |
||||
adr r0, _start /* r0 <- current position of code */ |
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ |
||||
cmp r0, r1 /* don't reloc during debug */ |
||||
beq stack_setup |
||||
|
||||
ldr r2, _armboot_start |
||||
ldr r3, _armboot_end |
||||
sub r2, r3, r2 /* r2 <- size of armboot */ |
||||
add r2, r0, r2 /* r2 <- source end address */ |
||||
|
||||
copy_loop: |
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */ |
||||
cmp r0, r2 /* until source end addreee [r2] */ |
||||
ble copy_loop |
||||
|
||||
/* Set up the stack */ |
||||
|
||||
stack_setup: |
||||
|
||||
ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */ |
||||
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ |
||||
/* FIXME: bdinfo should be here */ |
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */ |
||||
|
||||
clear_bss: |
||||
|
||||
ldr r0, _bss_start /* find start of bss segment */ |
||||
add r0, r0, #4 /* start at first byte of bss */ |
||||
ldr r1, _bss_end /* stop here */ |
||||
mov r2, #0x00000000 /* clear */ |
||||
|
||||
clbss_l:str r2, [r0] /* clear loop... */ |
||||
add r0, r0, #4 |
||||
cmp r0, r1 |
||||
bne clbss_l |
||||
|
||||
|
||||
ldr pc, _start_armboot |
||||
|
||||
_start_armboot: .word start_armboot |
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************/ |
||||
/* */ |
||||
/* Interrupt handling */ |
||||
/* */ |
||||
/****************************************************************************/ |
||||
|
||||
/* IRQ stack frame */ |
||||
|
||||
#define S_FRAME_SIZE 72 |
||||
|
||||
#define S_OLD_R0 68 |
||||
#define S_PSR 64 |
||||
#define S_PC 60 |
||||
#define S_LR 56 |
||||
#define S_SP 52 |
||||
|
||||
#define S_IP 48 |
||||
#define S_FP 44 |
||||
#define S_R10 40 |
||||
#define S_R9 36 |
||||
#define S_R8 32 |
||||
#define S_R7 28 |
||||
#define S_R6 24 |
||||
#define S_R5 20 |
||||
#define S_R4 16 |
||||
#define S_R3 12 |
||||
#define S_R2 8 |
||||
#define S_R1 4 |
||||
#define S_R0 0 |
||||
|
||||
#define MODE_SVC 0x13 |
||||
|
||||
/* use bad_save_user_regs for abort/prefetch/undef/swi ... */ |
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} /* Calling r0-r12 */ |
||||
add r8, sp, #S_PC |
||||
|
||||
ldr r2, _armboot_end |
||||
add r2, r2, #CONFIG_STACKSIZE |
||||
sub r2, r2, #8 |
||||
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ |
||||
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ |
||||
|
||||
add r5, sp, #S_SP |
||||
mov r1, lr |
||||
stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ |
||||
mov r0, sp |
||||
.endm |
||||
|
||||
|
||||
/* use irq_save_user_regs / irq_restore_user_regs for */ |
||||
/* IRQ/FIQ handling */ |
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} /* Calling r0-r12 */ |
||||
add r8, sp, #S_PC |
||||
stmdb r8, {sp, lr}^ /* Calling SP, LR */ |
||||
str lr, [r8, #0] /* Save calling PC */ |
||||
mrs r6, spsr |
||||
str r6, [r8, #4] /* Save CPSR */ |
||||
str r0, [r8, #8] /* Save OLD_R0 */ |
||||
mov r0, sp |
||||
.endm |
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0 |
||||
ldr lr, [sp, #S_PC] @ Get PC |
||||
add sp, sp, #S_FRAME_SIZE |
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm |
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_end @ setup our mode stack
|
||||
add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack |
||||
sub r13, r13, #8 |
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr |
||||
str lr, [r13, #4] |
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||
msr spsr_c, r13 |
||||
mov lr, pc |
||||
movs pc, lr |
||||
.endm |
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START |
||||
.endm |
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START |
||||
.endm |
||||
|
||||
|
||||
/****************************************************************************/ |
||||
/* */ |
||||
/* exception handlers */ |
||||
/* */ |
||||
/****************************************************************************/ |
||||
|
||||
.align 5
|
||||
undefined_instruction: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_undefined_instruction |
||||
|
||||
.align 5
|
||||
software_interrupt: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_software_interrupt |
||||
|
||||
.align 5
|
||||
prefetch_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_prefetch_abort |
||||
|
||||
.align 5
|
||||
data_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_data_abort |
||||
|
||||
.align 5
|
||||
not_used: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_not_used |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_irq_stack |
||||
irq_save_user_regs |
||||
bl do_irq |
||||
irq_restore_user_regs |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_fiq_stack |
||||
irq_save_user_regs /* someone ought to write a more */ |
||||
bl do_fiq /* effiction fiq_save_user_regs */ |
||||
irq_restore_user_regs |
||||
|
||||
#else |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_irq |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_fiq |
||||
|
||||
#endif |
||||
|
||||
/****************************************************************************/ |
||||
/* */ |
||||
/* Reset function: Use Watchdog to reset */ |
||||
/* */ |
||||
/****************************************************************************/ |
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
|
||||
reset_cpu: |
||||
ldr r1, =0x482e |
||||
ldr r2, =IXP425_OSWK |
||||
str r1, [r2] |
||||
ldr r1, =0x0fff |
||||
ldr r2, =IXP425_OSWT |
||||
str r1, [r2] |
||||
ldr r1, =0x5 |
||||
ldr r2, =IXP425_OSWE |
||||
str r1, [r2] |
||||
b reset_endless |
||||
|
||||
|
||||
reset_endless: |
||||
|
||||
b reset_endless |
@ -0,0 +1,74 @@ |
||||
/* vi: set ts=8 sw=8 noet: */ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
void ixp425_udelay(unsigned long usec) |
||||
{ |
||||
/*
|
||||
* This function has a max usec, but since it is called from udelay |
||||
* we should not have to worry... be happy |
||||
*/ |
||||
unsigned long usecs = CFG_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; |
||||
|
||||
*IXP425_OSST = IXP425_OSST_TIMER_1_PEND; |
||||
usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; |
||||
*IXP425_OSRT1 = usecs; |
||||
while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)); |
||||
} |
||||
|
||||
void udelay (unsigned long usec) |
||||
{ |
||||
while (usec--) ixp425_udelay(1); |
||||
} |
||||
|
||||
static ulong reload_constant = 0xfffffff0; |
||||
|
||||
void reset_timer_masked (void) |
||||
{ |
||||
ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; |
||||
|
||||
*IXP425_OSST = IXP425_OSST_TIMER_1_PEND; |
||||
*IXP425_OSRT1 = reload; |
||||
} |
||||
|
||||
ulong get_timer_masked (void) |
||||
{ |
||||
/*
|
||||
* Note that it is possible for this to wrap! |
||||
* In this case we return max. |
||||
*/ |
||||
ulong current = *IXP425_OST1; |
||||
if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND) |
||||
{ |
||||
return reload_constant; |
||||
} |
||||
return (reload_constant - current); |
||||
} |
@ -0,0 +1,559 @@ |
||||
/*
|
||||
* include/asm-arm/arch-ixp425/ixp425.h
|
||||
* |
||||
* Register definitions for IXP425
|
||||
* |
||||
* Copyright (C) 2002 Intel Corporation. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _ASM_ARM_IXP425_H_ |
||||
#define _ASM_ARM_IXP425_H_ |
||||
|
||||
#define BIT(x) (1<<(x)) |
||||
|
||||
/* FIXME: Only this does work for u-boot... find out why... [RS] */ |
||||
#define UBOOT_REG_FIX 1 |
||||
#ifdef UBOOT_REG_FIX |
||||
# undef io_p2v |
||||
# undef __REG |
||||
# ifndef __ASSEMBLY__ |
||||
# define io_p2v(PhAdd) (PhAdd) |
||||
# define __REG(x) (*((volatile u32 *)io_p2v(x))) |
||||
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) |
||||
# else |
||||
# define __REG(x) (x) |
||||
# endif |
||||
#endif /* UBOOT_REG_FIX */ |
||||
|
||||
/*
|
||||
*
|
||||
* IXP425 Memory map: |
||||
* |
||||
* Phy Phy Size Map Size Virt Description |
||||
* ========================================================================= |
||||
* |
||||
* 0x00000000 0x10000000 SDRAM 1
|
||||
* |
||||
* 0x10000000 0x10000000 SDRAM 2 |
||||
* |
||||
* 0x20000000 0x10000000 SDRAM 3 |
||||
* |
||||
* 0x30000000 0x10000000 SDRAM 4
|
||||
* |
||||
* The above four are aliases to the same memory location (0x00000000) |
||||
* |
||||
* 0x48000000 0x4000000 PCI Memory |
||||
* |
||||
* 0x50000000 0x10000000 Not Mapped EXP BUS |
||||
* |
||||
* 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr |
||||
* |
||||
* 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
|
||||
* |
||||
* 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
|
||||
* |
||||
* 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL |
||||
* |
||||
* 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
|
||||
*/ |
||||
|
||||
/*
|
||||
* SDRAM |
||||
*/ |
||||
#define IXP425_SDRAM_BASE (0x00000000) |
||||
#define IXP425_SDRAM_BASE_ALT (0x10000000) |
||||
|
||||
|
||||
/*
|
||||
* PCI Configuration space |
||||
*/ |
||||
#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) |
||||
#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000) |
||||
#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) |
||||
|
||||
/*
|
||||
* Expansion BUS Configuration registers |
||||
*/ |
||||
#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) |
||||
#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000) |
||||
#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) |
||||
|
||||
/*
|
||||
* Peripheral space |
||||
*/ |
||||
#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) |
||||
#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000) |
||||
#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) |
||||
|
||||
/*
|
||||
* SDRAM configuration registers |
||||
*/ |
||||
#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) |
||||
|
||||
/*
|
||||
* Q Manager space .. not static mapped |
||||
*/ |
||||
#define IXP425_QMGR_BASE_PHYS (0x60000000) |
||||
#define IXP425_QMGR_BASE_VIRT (0xFFFDE000) |
||||
#define IXP425_QMGR_REGION_SIZE (0x00004000) |
||||
|
||||
/*
|
||||
* Expansion BUS |
||||
* |
||||
* Expansion Bus 'lives' at either base1 or base 2 depending on the value of |
||||
* Exp Bus config registers: |
||||
* |
||||
* Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, |
||||
* and The expansion bus to IXP425_EXP_BUS_BASE2 |
||||
*/ |
||||
#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) |
||||
#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) |
||||
#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000) |
||||
|
||||
#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS |
||||
#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT |
||||
|
||||
#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) |
||||
#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) |
||||
|
||||
#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) |
||||
#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) |
||||
#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) |
||||
#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) |
||||
#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) |
||||
#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) |
||||
#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) |
||||
#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) |
||||
|
||||
#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000) |
||||
#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000) |
||||
#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000) |
||||
#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000) |
||||
#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000) |
||||
#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000) |
||||
#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000) |
||||
#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000) |
||||
|
||||
#define IXP425_FLASH_WRITABLE (0x2) |
||||
#define IXP425_FLASH_DEFAULT (0xbcd23c40) |
||||
#define IXP425_FLASH_WRITE (0xbcd23c42) |
||||
|
||||
|
||||
#define IXP425_EXP_CS0_OFFSET 0x00 |
||||
#define IXP425_EXP_CS1_OFFSET 0x04 |
||||
#define IXP425_EXP_CS2_OFFSET 0x08 |
||||
#define IXP425_EXP_CS3_OFFSET 0x0C |
||||
#define IXP425_EXP_CS4_OFFSET 0x10 |
||||
#define IXP425_EXP_CS5_OFFSET 0x14 |
||||
#define IXP425_EXP_CS6_OFFSET 0x18 |
||||
#define IXP425_EXP_CS7_OFFSET 0x1C |
||||
#define IXP425_EXP_CFG0_OFFSET 0x20 |
||||
#define IXP425_EXP_CFG1_OFFSET 0x24 |
||||
#define IXP425_EXP_CFG2_OFFSET 0x28 |
||||
#define IXP425_EXP_CFG3_OFFSET 0x2C |
||||
|
||||
/*
|
||||
* Expansion Bus Controller registers. |
||||
*/ |
||||
#ifndef __ASSEMBLY__ |
||||
#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x))) |
||||
#else |
||||
#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) |
||||
#endif |
||||
|
||||
#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) |
||||
#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) |
||||
#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) |
||||
#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) |
||||
#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) |
||||
#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) |
||||
#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) |
||||
#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) |
||||
|
||||
#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) |
||||
#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) |
||||
#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) |
||||
#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) |
||||
|
||||
/*
|
||||
* SDRAM Controller registers. |
||||
*/ |
||||
#define IXP425_SDR_CONFIG_OFFSET 0x00 |
||||
#define IXP425_SDR_REFRESH_OFFSET 0x04 |
||||
#define IXP425_SDR_IR_OFFSET 0x08 |
||||
|
||||
#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) |
||||
|
||||
#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) |
||||
#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) |
||||
#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) |
||||
|
||||
/*
|
||||
* UART registers |
||||
*/ |
||||
#define IXP425_UART1 0 |
||||
#define IXP425_UART2 0x1000 |
||||
|
||||
#define IXP425_UART_RBR_OFFSET 0x00 |
||||
#define IXP425_UART_THR_OFFSET 0x00 |
||||
#define IXP425_UART_DLL_OFFSET 0x00 |
||||
#define IXP425_UART_IER_OFFSET 0x04 |
||||
#define IXP425_UART_DLH_OFFSET 0x04 |
||||
#define IXP425_UART_IIR_OFFSET 0x08 |
||||
#define IXP425_UART_FCR_OFFSET 0x00 |
||||
#define IXP425_UART_LCR_OFFSET 0x0c |
||||
#define IXP425_UART_MCR_OFFSET 0x10 |
||||
#define IXP425_UART_LSR_OFFSET 0x14 |
||||
#define IXP425_UART_MSR_OFFSET 0x18 |
||||
#define IXP425_UART_SPR_OFFSET 0x1c |
||||
#define IXP425_UART_ISR_OFFSET 0x20 |
||||
|
||||
#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) |
||||
|
||||
#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) |
||||
#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) |
||||
#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) |
||||
#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) |
||||
#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) |
||||
#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) |
||||
#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) |
||||
#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) |
||||
#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) |
||||
#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) |
||||
#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) |
||||
#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) |
||||
#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) |
||||
|
||||
#define IER_DMAE (1 << 7) /* DMA Requests Enable */ |
||||
#define IER_UUE (1 << 6) /* UART Unit Enable */ |
||||
#define IER_NRZE (1 << 5) /* NRZ coding Enable */ |
||||
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ |
||||
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ |
||||
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ |
||||
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ |
||||
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ |
||||
|
||||
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ |
||||
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ |
||||
#define IIR_TOD (1 << 3) /* Time Out Detected */ |
||||
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ |
||||
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ |
||||
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ |
||||
|
||||
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ |
||||
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ |
||||
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ |
||||
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ |
||||
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ |
||||
#define FCR_ITL_1 (0) |
||||
#define FCR_ITL_8 (FCR_ITL1) |
||||
#define FCR_ITL_16 (FCR_ITL2) |
||||
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) |
||||
|
||||
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ |
||||
#define LCR_SB (1 << 6) /* Set Break */ |
||||
#define LCR_STKYP (1 << 5) /* Sticky Parity */ |
||||
#define LCR_EPS (1 << 4) /* Even Parity Select */ |
||||
#define LCR_PEN (1 << 3) /* Parity Enable */ |
||||
#define LCR_STB (1 << 2) /* Stop Bit */ |
||||
#define LCR_WLS1 (1 << 1) /* Word Length Select */ |
||||
#define LCR_WLS0 (1 << 0) /* Word Length Select */ |
||||
|
||||
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ |
||||
#define LSR_TEMT (1 << 6) /* Transmitter Empty */ |
||||
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ |
||||
#define LSR_BI (1 << 4) /* Break Interrupt */ |
||||
#define LSR_FE (1 << 3) /* Framing Error */ |
||||
#define LSR_PE (1 << 2) /* Parity Error */ |
||||
#define LSR_OE (1 << 1) /* Overrun Error */ |
||||
#define LSR_DR (1 << 0) /* Data Ready */ |
||||
|
||||
#define MCR_LOOP (1 << 4) */ |
||||
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ |
||||
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ |
||||
#define MCR_RTS (1 << 1) /* Request to Send */ |
||||
#define MCR_DTR (1 << 0) /* Data Terminal Ready */ |
||||
|
||||
#define MSR_DCD (1 << 7) /* Data Carrier Detect */ |
||||
#define MSR_RI (1 << 6) /* Ring Indicator */ |
||||
#define MSR_DSR (1 << 5) /* Data Set Ready */ |
||||
#define MSR_CTS (1 << 4) /* Clear To Send */ |
||||
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ |
||||
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ |
||||
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ |
||||
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ |
||||
|
||||
#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT |
||||
#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS |
||||
/*
|
||||
* Peripheral Space Registers
|
||||
*/ |
||||
#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) |
||||
#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) |
||||
#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) |
||||
#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) |
||||
#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) |
||||
#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) |
||||
#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) |
||||
#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) |
||||
#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) |
||||
#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) |
||||
#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) |
||||
#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) |
||||
|
||||
#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000) |
||||
#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000) |
||||
#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000) |
||||
#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000) |
||||
#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000) |
||||
#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000) |
||||
#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000) |
||||
#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000) |
||||
#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000) |
||||
#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000) |
||||
#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000) |
||||
#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000) |
||||
|
||||
|
||||
/*
|
||||
* UART Register Definitions , Offsets only as there are 2 UARTS. |
||||
* IXP425_UART1_BASE , IXP425_UART2_BASE. |
||||
*/ |
||||
|
||||
#undef UART_NO_RX_INTERRUPT |
||||
|
||||
#define IXP425_UART_XTAL 14745600 |
||||
|
||||
/*
|
||||
* Constants to make it easy to access Interrupt Controller registers |
||||
*/ |
||||
#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ |
||||
#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ |
||||
#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ |
||||
#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ |
||||
#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ |
||||
#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ |
||||
#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ |
||||
#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ |
||||
|
||||
/*
|
||||
* Interrupt Controller Register Definitions. |
||||
*/ |
||||
#ifndef __ASSEMBLY__ |
||||
#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x))) |
||||
#else |
||||
#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) |
||||
#endif |
||||
|
||||
#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) |
||||
#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) |
||||
#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) |
||||
#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) |
||||
#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) |
||||
#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) |
||||
#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) |
||||
#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) |
||||
|
||||
/*
|
||||
* Constants to make it easy to access GPIO registers |
||||
*/ |
||||
#define IXP425_GPIO_GPOUTR_OFFSET 0x00 |
||||
#define IXP425_GPIO_GPOER_OFFSET 0x04 |
||||
#define IXP425_GPIO_GPINR_OFFSET 0x08 |
||||
#define IXP425_GPIO_GPISR_OFFSET 0x0C |
||||
#define IXP425_GPIO_GPIT1R_OFFSET 0x10 |
||||
#define IXP425_GPIO_GPIT2R_OFFSET 0x14 |
||||
#define IXP425_GPIO_GPCLKR_OFFSET 0x18 |
||||
#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C |
||||
|
||||
/*
|
||||
* GPIO Register Definitions. |
||||
* [Only perform 32bit reads/writes] |
||||
*/ |
||||
#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x))) |
||||
|
||||
#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) |
||||
#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) |
||||
#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) |
||||
#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) |
||||
#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) |
||||
#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) |
||||
#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) |
||||
#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) |
||||
|
||||
/*
|
||||
* Constants to make it easy to access Timer Control/Status registers |
||||
*/ |
||||
#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ |
||||
#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ |
||||
#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ |
||||
#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ |
||||
#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ |
||||
#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ |
||||
#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ |
||||
#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ |
||||
#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ |
||||
|
||||
/*
|
||||
* Operating System Timer Register Definitions. |
||||
*/ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) |
||||
#else |
||||
#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) |
||||
#endif |
||||
|
||||
#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET) |
||||
#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) |
||||
#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) |
||||
#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) |
||||
#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) |
||||
#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) |
||||
#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) |
||||
#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) |
||||
#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) |
||||
|
||||
/*
|
||||
* Timer register values and bit definitions
|
||||
*/ |
||||
#define IXP425_OST_ENABLE BIT(0) |
||||
#define IXP425_OST_ONE_SHOT BIT(1) |
||||
/* Low order bits of reload value ignored */ |
||||
#define IXP425_OST_RELOAD_MASK (0x3) |
||||
#define IXP425_OST_DISABLED (0x0) |
||||
#define IXP425_OSST_TIMER_1_PEND BIT(0) |
||||
#define IXP425_OSST_TIMER_2_PEND BIT(1) |
||||
#define IXP425_OSST_TIMER_TS_PEND BIT(2) |
||||
#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) |
||||
#define IXP425_OSST_TIMER_WARM_RESET BIT(4) |
||||
|
||||
/*
|
||||
* Constants to make it easy to access PCI Control/Status registers |
||||
*/ |
||||
#define PCI_NP_AD_OFFSET 0x00 |
||||
#define PCI_NP_CBE_OFFSET 0x04 |
||||
#define PCI_NP_WDATA_OFFSET 0x08 |
||||
#define PCI_NP_RDATA_OFFSET 0x0c |
||||
#define PCI_CRP_AD_CBE_OFFSET 0x10 |
||||
#define PCI_CRP_WDATA_OFFSET 0x14 |
||||
#define PCI_CRP_RDATA_OFFSET 0x18 |
||||
#define PCI_CSR_OFFSET 0x1c |
||||
#define PCI_ISR_OFFSET 0x20 |
||||
#define PCI_INTEN_OFFSET 0x24 |
||||
#define PCI_DMACTRL_OFFSET 0x28 |
||||
#define PCI_AHBMEMBASE_OFFSET 0x2c |
||||
#define PCI_AHBIOBASE_OFFSET 0x30 |
||||
#define PCI_PCIMEMBASE_OFFSET 0x34 |
||||
#define PCI_AHBDOORBELL_OFFSET 0x38 |
||||
#define PCI_PCIDOORBELL_OFFSET 0x3C |
||||
#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 |
||||
#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 |
||||
#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 |
||||
#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C |
||||
#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 |
||||
#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 |
||||
|
||||
/*
|
||||
* PCI Control/Status Registers |
||||
*/ |
||||
#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x))) |
||||
|
||||
#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) |
||||
#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) |
||||
#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) |
||||
#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) |
||||
#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) |
||||
#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) |
||||
#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) |
||||
#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) |
||||
#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) |
||||
#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) |
||||
#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) |
||||
#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) |
||||
#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) |
||||
#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) |
||||
#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) |
||||
#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) |
||||
#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) |
||||
#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) |
||||
#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) |
||||
#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) |
||||
#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) |
||||
#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) |
||||
|
||||
/*
|
||||
* PCI register values and bit definitions
|
||||
*/ |
||||
|
||||
/* CSR bit definitions */ |
||||
#define PCI_CSR_HOST BIT(0) |
||||
#define PCI_CSR_ARBEN BIT(1) |
||||
#define PCI_CSR_ADS BIT(2) |
||||
#define PCI_CSR_PDS BIT(3) |
||||
#define PCI_CSR_ABE BIT(4) |
||||
#define PCI_CSR_DBT BIT(5) |
||||
#define PCI_CSR_ASE BIT(8) |
||||
#define PCI_CSR_IC BIT(15) |
||||
|
||||
/* ISR (Interrupt status) Register bit definitions */ |
||||
#define PCI_ISR_PSE BIT(0) |
||||
#define PCI_ISR_PFE BIT(1) |
||||
#define PCI_ISR_PPE BIT(2) |
||||
#define PCI_ISR_AHBE BIT(3) |
||||
#define PCI_ISR_APDC BIT(4) |
||||
#define PCI_ISR_PADC BIT(5) |
||||
#define PCI_ISR_ADB BIT(6) |
||||
#define PCI_ISR_PDB BIT(7) |
||||
|
||||
/* INTEN (Interrupt Enable) Register bit definitions */ |
||||
#define PCI_INTEN_PSE BIT(0) |
||||
#define PCI_INTEN_PFE BIT(1) |
||||
#define PCI_INTEN_PPE BIT(2) |
||||
#define PCI_INTEN_AHBE BIT(3) |
||||
#define PCI_INTEN_APDC BIT(4) |
||||
#define PCI_INTEN_PADC BIT(5) |
||||
#define PCI_INTEN_ADB BIT(6) |
||||
#define PCI_INTEN_PDB BIT(7) |
||||
|
||||
/*
|
||||
* Shift value for byte enable on NP cmd/byte enable register |
||||
*/ |
||||
#define IXP425_PCI_NP_CBE_BESL 4 |
||||
|
||||
/*
|
||||
* PCI commands supported by NP access unit |
||||
*/ |
||||
#define NP_CMD_IOREAD 0x2 |
||||
#define NP_CMD_IOWRITE 0x3 |
||||
#define NP_CMD_CONFIGREAD 0xa |
||||
#define NP_CMD_CONFIGWRITE 0xb |
||||
#define NP_CMD_MEMREAD 0x6 |
||||
#define NP_CMD_MEMWRITE 0x7 |
||||
|
||||
#if 0 |
||||
#ifndef __ASSEMBLY__ |
||||
extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); |
||||
extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); |
||||
extern void ixp425_pci_init(void *); |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* Constants for CRP access into local config space |
||||
*/ |
||||
#define CRP_AD_CBE_BESL 20 |
||||
#define CRP_AD_CBE_WRITE BIT(16) |
||||
|
||||
/*
|
||||
* Clock Speed Definitions. |
||||
*/ |
||||
#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ |
||||
|
||||
|
||||
#endif |
@ -0,0 +1,171 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* Configuation settings for the IXDP425 board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ |
||||
#define CONFIG_IXDP425 1 /* on an IXDP425 Board */ |
||||
|
||||
/***************************************************************
|
||||
* U-boot generic defines start here. |
||||
***************************************************************/ |
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram |
||||
* so we MUST NOT initialize critical regs like mem-timing ... |
||||
*/ |
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */ |
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
/* These are u-boot generic parameters */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
#define CONFIG_IPADDR 192.168.0.21 |
||||
#define CONFIG_SERVERIP 192.168.0.250 |
||||
#define CONFIG_BOOTCOMMAND "bootm 50040000" |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" |
||||
#define CONFIG_CMDLINE_TAG |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00010000 /* default load address */ |
||||
|
||||
#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ |
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/***************************************************************
|
||||
* Platform/Board specific defines start here. |
||||
***************************************************************/ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ |
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ |
||||
#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */ |
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ |
||||
|
||||
#define CFG_DRAM_BASE 0x00000000 |
||||
#define CFG_DRAM_SIZE 0x01000000 |
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*
|
||||
* Expansion bus settings |
||||
*/ |
||||
#define CFG_EXP_CS0 0xbcd23c42 |
||||
|
||||
/*
|
||||
* SDRAM settings |
||||
*/ |
||||
#define CFG_SDR_CONFIG 0xd |
||||
#define CFG_SDRAM_REFRESH_CNT 0x81a |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ |
||||
|
||||
/* FIXME */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue