This adds the Gumstix Pepper[1] single-board computer based on the TI AM335x processor. Schematics are available [2]. [1] https://store.gumstix.com/index.php/products/344/ [2] https://pubs.gumstix.com/boards/PEPPER/ Signed-off-by: Ash Charles <ash@gumstix.com> [trini: Move 'cdev' in board.c down to under #ifdef's where it's used] Signed-off-by: Tom Rini <trini@ti.com>master
Ash Charles
10 years ago
committed by
Tom Rini
parent
532d531828
commit
2d92ba8440
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-y += mux.o
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endif |
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obj-y += board.o
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@ -0,0 +1,226 @@ |
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/*
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* Board functions for Gumstix Pepper and AM335x-based boards |
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* |
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* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
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* Based on board/ti/am335x/board.c from Texas Instruments, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <spl.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/omap.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mem.h> |
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#include <asm/io.h> |
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#include <asm/emif.h> |
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#include <asm/gpio.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <cpsw.h> |
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#include <power/tps65217.h> |
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#include <environment.h> |
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#include <watchdog.h> |
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#include "board.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_SPL_BUILD |
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static const struct ddr_data ddr2_data = { |
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.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | |
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(MT47H128M16RT25E_RD_DQS<<20) | |
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(MT47H128M16RT25E_RD_DQS<<10) | |
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(MT47H128M16RT25E_RD_DQS<<0)), |
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.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | |
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(MT47H128M16RT25E_WR_DQS<<20) | |
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(MT47H128M16RT25E_WR_DQS<<10) | |
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(MT47H128M16RT25E_WR_DQS<<0)), |
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.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | |
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(MT47H128M16RT25E_PHY_WRLVL<<20) | |
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(MT47H128M16RT25E_PHY_WRLVL<<10) | |
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(MT47H128M16RT25E_PHY_WRLVL<<0)), |
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.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | |
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(MT47H128M16RT25E_PHY_GATELVL<<20) | |
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(MT47H128M16RT25E_PHY_GATELVL<<10) | |
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(MT47H128M16RT25E_PHY_GATELVL<<0)), |
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.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<20) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<10) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<0)), |
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.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<20) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<10) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<0)), |
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}; |
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static const struct cmd_control ddr2_cmd_ctrl_data = { |
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.cmd0csratio = MT47H128M16RT25E_RATIO, |
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.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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.cmd1csratio = MT47H128M16RT25E_RATIO, |
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.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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.cmd2csratio = MT47H128M16RT25E_RATIO, |
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.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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}; |
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static const struct emif_regs ddr2_emif_reg_data = { |
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
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}; |
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#ifdef CONFIG_SPL_OS_BOOT |
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int spl_start_uboot(void) |
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{ |
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/* break into full u-boot on 'c' */ |
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return serial_tstc() && serial_getc() == 'c'; |
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} |
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#endif |
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#define OSC (V_OSCK/1000000) |
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const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; |
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const struct dpll_params *get_dpll_ddr_params(void) |
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{ |
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return &dpll_ddr; |
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} |
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void set_uart_mux_conf(void) |
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{ |
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enable_uart0_pin_mux(); |
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} |
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void set_mux_conf_regs(void) |
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{ |
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enable_board_pin_mux(); |
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} |
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const struct ctrl_ioregs ioregs = { |
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, |
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}; |
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void sdram_init(void) |
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{ |
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config_ddr(266, &ioregs, &ddr2_data, |
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); |
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} |
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#endif |
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int board_init(void) |
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{ |
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#if defined(CONFIG_HW_WATCHDOG) |
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hw_watchdog_init(); |
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#endif |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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gpmc_init(); |
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return 0; |
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} |
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
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static void cpsw_control(int enabled) |
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{ |
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/* VTP can be added here */ |
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return; |
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} |
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static struct cpsw_slave_data cpsw_slaves[] = { |
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{ |
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.slave_reg_ofs = 0x208, |
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.sliver_reg_ofs = 0xd80, |
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.phy_addr = 0, |
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.phy_if = PHY_INTERFACE_MODE_RGMII, |
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}, |
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}; |
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static struct cpsw_platform_data cpsw_data = { |
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.mdio_base = CPSW_MDIO_BASE, |
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.cpsw_base = CPSW_BASE, |
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.mdio_div = 0xff, |
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.channels = 8, |
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.cpdma_reg_ofs = 0x800, |
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.slaves = 1, |
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.slave_data = cpsw_slaves, |
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.ale_reg_ofs = 0xd00, |
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.ale_entries = 1024, |
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.host_port_reg_ofs = 0x108, |
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.hw_stats_reg_ofs = 0x900, |
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.bd_ram_ofs = 0x2000, |
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.mac_control = (1 << 5), |
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.control = cpsw_control, |
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.host_port_num = 0, |
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.version = CPSW_CTRL_VERSION_2, |
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}; |
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int board_eth_init(bd_t *bis) |
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{ |
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int rv, n = 0; |
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uint8_t mac_addr[6]; |
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uint32_t mac_hi, mac_lo; |
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const char *devname; |
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
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/* try reading mac address from efuse */ |
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mac_lo = readl(&cdev->macid0l); |
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mac_hi = readl(&cdev->macid0h); |
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mac_addr[0] = mac_hi & 0xFF; |
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mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
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mac_addr[4] = mac_lo & 0xFF; |
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mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
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if (is_valid_ether_addr(mac_addr)) |
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eth_setenv_enetaddr("ethaddr", mac_addr); |
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} |
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writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
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rv = cpsw_register(&cpsw_data); |
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if (rv < 0) |
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printf("Error %d registering CPSW switch\n", rv); |
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else |
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n += rv; |
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/*
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* |
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* CPSW RGMII Internal Delay Mode is not supported in all PVT |
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* operating points. So we must set the TX clock delay feature |
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* in the KSZ9021 PHY. Since we only support a single ethernet |
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* device in U-Boot, we only do this for the current instance. |
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*/ |
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devname = miiphy_get_current_dev(); |
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/* max rx/tx clock delay, min rx/tx control delay */ |
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miiphy_write(devname, 0x0, 0x0b, 0x8104); |
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miiphy_write(devname, 0x0, 0xc, 0xa0a0); |
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/* min rx data delay */ |
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miiphy_write(devname, 0x0, 0x0b, 0x8105); |
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miiphy_write(devname, 0x0, 0x0c, 0x0000); |
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/* min tx data delay */ |
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miiphy_write(devname, 0x0, 0x0b, 0x8106); |
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miiphy_write(devname, 0x0, 0x0c, 0x0000); |
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return n; |
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} |
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#endif |
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@ -0,0 +1,19 @@ |
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/*
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* Gumstix Pepper and AM335x-based boards information header |
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* |
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* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _BOARD_H_ |
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#define _BOARD_H_ |
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/*
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* We must be able to enable uart0, for initial output. We then have a |
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* main pinmux function that can be overridden to enable all other pinmux that |
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* is required on the board. |
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*/ |
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void enable_uart0_pin_mux(void); |
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void enable_board_pin_mux(void); |
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#endif |
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@ -0,0 +1,78 @@ |
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/*
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* Muxing for Gumstix Pepper and AM335x-based boards |
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* |
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* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/mux.h> |
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#include <asm/io.h> |
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#include <i2c.h> |
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#include "board.h" |
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static struct module_pin_mux uart0_pin_mux[] = { |
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ |
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ |
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{-1}, |
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}; |
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static struct module_pin_mux mmc0_pin_mux[] = { |
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ |
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ |
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ |
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ |
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ |
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ |
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ |
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{-1}, |
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}; |
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static struct module_pin_mux i2c0_pin_mux[] = { |
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/* I2C_DATA */ |
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
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/* I2C_SCLK */ |
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, |
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{-1}, |
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}; |
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static struct module_pin_mux rgmii1_pin_mux[] = { |
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ |
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ |
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ |
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ |
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ |
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ |
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ |
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ |
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ |
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ |
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ |
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ |
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ |
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
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{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ |
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{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ |
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{OFFSET(xdma_event_intr1), MODE(3)}, |
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{-1}, |
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}; |
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void enable_uart0_pin_mux(void) |
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{ |
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configure_module_pin_mux(uart0_pin_mux); |
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} |
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/*
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* Do board-specific muxes. |
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*/ |
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void enable_board_pin_mux(void) |
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{ |
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/* I2C0 */ |
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configure_module_pin_mux(i2c0_pin_mux); |
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/* SD Card */ |
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configure_module_pin_mux(mmc0_pin_mux); |
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/* Ethernet pinmux. */ |
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configure_module_pin_mux(rgmii1_pin_mux); |
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} |
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@ -0,0 +1,99 @@ |
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/*
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* Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_PEPPER_H |
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#define __CONFIG_PEPPER_H |
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#define CONFIG_MMC |
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#include <configs/ti_am335x_common.h> |
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#undef CONFIG_BOARD_LATE_INIT |
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#undef CONFIG_SPL_OS_BOOT |
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/* Clock defines */ |
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#define V_OSCK 24000000 /* Clock output from T2 */ |
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#define V_SCLK (V_OSCK) |
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#undef CONFIG_SYS_PROMPT |
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#define CONFIG_SYS_PROMPT "pepper# " |
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/* Mach type */ |
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#define MACH_TYPE_PEPPER 4207 /* Until the next sync */ |
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#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER |
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
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#define CONFIG_ENV_IS_NOWHERE |
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/* Display cpuinfo */ |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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DEFAULT_LINUX_BOOT_ENV \
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"bootdir=/boot\0" \
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"bootfile=zImage\0" \
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"fdtfile=am335x-pepper.dtb\0" \
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"console=ttyO0,115200n8\0" \
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"optargs=\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"${optargs} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"bootenv=uEnv.txt\0" \
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"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
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"importbootenv=echo Importing environment from mmc ...; " \
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"env import -t ${loadaddr} ${filesize}\0" \
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"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
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"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
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"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
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"uimageboot=echo Booting from mmc${mmcdev} ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootz ${loadaddr} - ${fdtaddr}\0" \
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"ubiboot=echo Booting from nand (ubifs) ...; " \
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"run ubiargs; run ubiload; " \
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"bootz ${loadaddr} - ${fdtaddr}\0" \
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#define CONFIG_BOOTCOMMAND \ |
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"echo SD/MMC found on device ${mmcdev};" \
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"if run loadbootenv; then " \
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"echo Loaded environment from ${bootenv};" \
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"run importbootenv;" \
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"fi;" \
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"if test -n $uenvcmd; then " \
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"echo Running uenvcmd ...;" \
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"run uenvcmd;" \
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"fi;" \
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"if run mmcload; then " \
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"run mmcboot;" \
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"fi;" \
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"if run loaduimage; then " \
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"run uimageboot;" \
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"fi;" \
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"fi;" \
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/* Serial console configuration */ |
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#define CONFIG_CONS_INDEX 1 /* UART0 */ |
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#define CONFIG_SERIAL1 1 |
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#define CONFIG_SYS_NS16550_COM1 0x44e09000 |
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/* Ethernet support */ |
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#define CONFIG_PHY_GIGE |
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#define CONFIG_PHYLIB |
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#define CONFIG_PHY_ADDR 0 |
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#define CONFIG_PHY_MICREL |
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#define CONFIG_PHY_MICREL_KSZ9021 |
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#define CONFIG_PHY_RESET_DELAY 1000 |
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/* SPL */ |
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" |
||||
|
||||
#endif /* __CONFIG_PEPPER_H */ |
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Reference in new issue