@ -775,7 +775,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
# endif
# define CONFIG_SYS_FSL_NUM_CC_PLLS 2
# define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
# define CONFIG_SYS_SDHC_CLOCK 0
# define CONFIG_SYS_FSL_NUM_LAWS 16
# define CONFIG_SYS_FSL_SRDS_1
# define CONFIG_SYS_FSL_SEC_COMPAT 5
@ -791,6 +790,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
# define CONFIG_SYS_FMAN_V3
# define CONFIG_FM_PLAT_CLK_DIV 1
# define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
# define CONFIG_SYS_SDHC_CLK 0 / * Select SDHC CLK begining from PLL1
per rcw field value */
# define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
# define CONFIG_SYS_FM_MURAM_SIZE 0x30000
# define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
# define CONFIG_SYS_FSL_TBCLK_DIV 16
@ -823,7 +825,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
# endif
# define CONFIG_SYS_FSL_NUM_CC_PLL 2
# define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
# define CONFIG_SYS_SDHC_CLOCK 0
# define CONFIG_SYS_FSL_NUM_LAWS 16
# define CONFIG_SYS_FSL_SRDS_1
# define CONFIG_SYS_FSL_SEC_COMPAT 5
@ -836,6 +837,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
# define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
# define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
# define CONFIG_SYS_FM1_CLK 0
# define CONFIG_SYS_SDHC_CLK 0 / * Select SDHC CLK begining from PLL1
per rcw field value */
# define CONFIG_QBMAN_CLK_DIV 1
# define CONFIG_SYS_FM_MURAM_SIZE 0x30000
# define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
@ -883,6 +886,9 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
# define CONFIG_PME_PLAT_CLK_DIV 1
# define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
# define CONFIG_SYS_FM1_CLK 0
# define CONFIG_SYS_SDHC_CLK 1 / * Select SDHC CLK begining from PLL2
per rcw field value */
# define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
# define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
# define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
# define CONFIG_SYS_FMAN_V3