Adding the correct configurations required for dplls, clocks, for omap5 Soc. Also changes are done to retain some part of the code common for OMAP4/5 and move only the remaining to the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
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/*
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* |
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* Clock initialization for OMAP4 |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* |
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* Based on previous work by: |
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* Santosh Shilimkar <santosh.shilimkar@ti.com> |
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* Rajendra Nayak <rnayak@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/omap_common.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/clocks.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/utils.h> |
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#include <asm/omap_gpio.h> |
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#ifndef CONFIG_SPL_BUILD |
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/*
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* printing to console doesn't work unless |
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* this code is executed from SPL |
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*/ |
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#define printf(fmt, args...) |
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#define puts(s) |
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#endif |
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#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) |
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struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; |
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const u32 sys_clk_array[8] = { |
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12000000, /* 12 MHz */ |
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13000000, /* 13 MHz */ |
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16800000, /* 16.8 MHz */ |
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19200000, /* 19.2 MHz */ |
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26000000, /* 26 MHz */ |
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27000000, /* 27 MHz */ |
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38400000, /* 38.4 MHz */ |
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}; |
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/*
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* The M & N values in the following tables are created using the |
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* following tool: |
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* tools/omap/clocks_get_m_n.c |
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* Please use this tool for creating the table for any new frequency. |
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*/ |
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/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ |
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static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { |
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{230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ |
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
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{200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ |
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { |
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{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
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{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { |
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{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params |
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { |
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{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { |
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{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ |
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{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ |
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{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ |
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{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ |
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{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ |
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{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ |
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{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { |
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{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ |
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{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ |
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{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ |
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{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ |
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{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ |
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{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ |
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{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ |
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}; |
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/* ABE M & N values with sys_clk as source */ |
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static const struct dpll_params |
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
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{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ |
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{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ |
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{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ |
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{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ |
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{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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/* ABE M & N values with 32K clock as source */ |
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static const struct dpll_params abe_dpll_params_32k_196608khz = { |
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750, 0, 1, 1, -1, -1, -1, -1 |
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}; |
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
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{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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void setup_post_dividers(u32 *const base, const struct dpll_params *params) |
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{ |
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
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/* Setup post-dividers */ |
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if (params->m2 >= 0) |
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writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
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if (params->m3 >= 0) |
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writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
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if (params->m4 >= 0) |
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writel(params->m4, &dpll_regs->cm_div_m4_dpll); |
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if (params->m5 >= 0) |
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writel(params->m5, &dpll_regs->cm_div_m5_dpll); |
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if (params->m6 >= 0) |
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writel(params->m6, &dpll_regs->cm_div_m6_dpll); |
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if (params->m7 >= 0) |
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writel(params->m7, &dpll_regs->cm_div_m7_dpll); |
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} |
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/*
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* Lock MPU dpll |
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* |
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* Resulting MPU frequencies: |
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* 4430 ES1.0 : 600 MHz |
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* 4430 ES2.x : 792 MHz (OPP Turbo) |
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* 4460 : 920 MHz (OPP Turbo) - DCC disabled |
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*/ |
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const struct dpll_params *get_mpu_dpll_params(void) |
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{ |
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u32 omap_rev, sysclk_ind; |
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omap_rev = omap_revision(); |
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sysclk_ind = get_sys_clk_index(); |
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if (omap_rev == OMAP4430_ES1_0) |
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return &mpu_dpll_params_1200mhz[sysclk_ind]; |
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else if (omap_rev < OMAP4460_ES1_0) |
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return &mpu_dpll_params_1600mhz[sysclk_ind]; |
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else |
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return &mpu_dpll_params_1840mhz[sysclk_ind]; |
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} |
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const struct dpll_params *get_core_dpll_params(void) |
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{ |
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u32 sysclk_ind = get_sys_clk_index(); |
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switch (omap_revision()) { |
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case OMAP4430_ES1_0: |
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return &core_dpll_params_es1_1524mhz[sysclk_ind]; |
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case OMAP4430_ES2_0: |
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case OMAP4430_SILICON_ID_INVALID: |
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/* safest */ |
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return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; |
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default: |
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return &core_dpll_params_1600mhz[sysclk_ind]; |
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} |
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} |
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const struct dpll_params *get_per_dpll_params(void) |
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{ |
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u32 sysclk_ind = get_sys_clk_index(); |
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return &per_dpll_params_1536mhz[sysclk_ind]; |
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} |
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const struct dpll_params *get_iva_dpll_params(void) |
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{ |
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u32 sysclk_ind = get_sys_clk_index(); |
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return &iva_dpll_params_1862mhz[sysclk_ind]; |
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} |
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const struct dpll_params *get_usb_dpll_params(void) |
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{ |
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u32 sysclk_ind = get_sys_clk_index(); |
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return &usb_dpll_params_1920mhz[sysclk_ind]; |
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} |
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const struct dpll_params *get_abe_dpll_params(void) |
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{ |
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
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u32 sysclk_ind = get_sys_clk_index(); |
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return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; |
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#else |
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return &abe_dpll_params_32k_196608khz; |
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#endif |
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} |
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
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* We set the maximum voltages allowed here because Smart-Reflex is not |
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* enabled in bootloader. Voltage initialization in the kernel will set |
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* these to the nominal values after enabling Smart-Reflex |
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*/ |
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void scale_vcores(void) |
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{ |
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u32 volt, omap_rev; |
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setup_sri2c(); |
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omap_rev = omap_revision(); |
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/* TPS - supplies vdd_mpu on 4460 */ |
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if (omap_rev >= OMAP4460_ES1_0) { |
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volt = 1313; |
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do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); |
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} |
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/*
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* VCORE 1 |
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* |
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* 4430 : supplies vdd_mpu |
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* Setting a high voltage for Nitro mode as smart reflex is not enabled. |
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* We use the maximum possible value in the AVS range because the next |
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* higher voltage in the discrete range (code >= 0b111010) is way too |
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* high |
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* |
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* 4460 : supplies vdd_core |
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*/ |
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if (omap_rev < OMAP4460_ES1_0) { |
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volt = 1325; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
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} else { |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
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} |
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/* VCORE 2 - supplies vdd_iva */ |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
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/*
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* VCORE 3 |
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* 4430 : supplies vdd_core |
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* 4460 : not connected |
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*/ |
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if (omap_rev < OMAP4460_ES1_0) { |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); |
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} |
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} |
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/*
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* Enable essential clock domains, modules and |
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* do some additional special settings needed |
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*/ |
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void enable_basic_clocks(void) |
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{ |
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u32 *const clk_domains_essential[] = { |
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&prcm->cm_l4per_clkstctrl, |
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&prcm->cm_l3init_clkstctrl, |
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&prcm->cm_memif_clkstctrl, |
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&prcm->cm_l4cfg_clkstctrl, |
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0 |
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}; |
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u32 *const clk_modules_hw_auto_essential[] = { |
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&prcm->cm_wkup_gpio1_clkctrl, |
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&prcm->cm_l4per_gpio2_clkctrl, |
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&prcm->cm_l4per_gpio3_clkctrl, |
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&prcm->cm_l4per_gpio4_clkctrl, |
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&prcm->cm_l4per_gpio5_clkctrl, |
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&prcm->cm_l4per_gpio6_clkctrl, |
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&prcm->cm_memif_emif_1_clkctrl, |
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&prcm->cm_memif_emif_2_clkctrl, |
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&prcm->cm_l3init_hsusbotg_clkctrl, |
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&prcm->cm_l3init_usbphy_clkctrl, |
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&prcm->cm_l4cfg_l4_cfg_clkctrl, |
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0 |
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}; |
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u32 *const clk_modules_explicit_en_essential[] = { |
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&prcm->cm_l4per_gptimer2_clkctrl, |
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&prcm->cm_l3init_hsmmc1_clkctrl, |
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&prcm->cm_l3init_hsmmc2_clkctrl, |
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&prcm->cm_l4per_mcspi1_clkctrl, |
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&prcm->cm_wkup_gptimer1_clkctrl, |
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&prcm->cm_l4per_i2c1_clkctrl, |
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&prcm->cm_l4per_i2c2_clkctrl, |
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&prcm->cm_l4per_i2c3_clkctrl, |
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&prcm->cm_l4per_i2c4_clkctrl, |
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&prcm->cm_wkup_wdtimer2_clkctrl, |
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&prcm->cm_l4per_uart3_clkctrl, |
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0 |
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}; |
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/* Enable optional additional functional clock for GPIO4 */ |
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setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, |
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GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
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/* Enable 96 MHz clock for MMC1 & MMC2 */ |
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setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, |
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HSMMC_CLKCTRL_CLKSEL_MASK); |
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setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, |
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HSMMC_CLKCTRL_CLKSEL_MASK); |
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/* Select 32KHz clock as the source of GPTIMER1 */ |
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setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, |
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GPTIMER1_CLKCTRL_CLKSEL_MASK); |
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/* Enable optional 48M functional clock for USB PHY */ |
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setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, |
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USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); |
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do_enable_clocks(clk_domains_essential, |
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clk_modules_hw_auto_essential, |
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clk_modules_explicit_en_essential, |
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1); |
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} |
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/*
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* Enable non-essential clock domains, modules and |
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* do some additional special settings needed |
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*/ |
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void enable_non_essential_clocks(void) |
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{ |
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u32 *const clk_domains_non_essential[] = { |
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&prcm->cm_mpu_m3_clkstctrl, |
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&prcm->cm_ivahd_clkstctrl, |
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&prcm->cm_dsp_clkstctrl, |
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&prcm->cm_dss_clkstctrl, |
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&prcm->cm_sgx_clkstctrl, |
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&prcm->cm1_abe_clkstctrl, |
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&prcm->cm_c2c_clkstctrl, |
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&prcm->cm_cam_clkstctrl, |
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&prcm->cm_dss_clkstctrl, |
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&prcm->cm_sdma_clkstctrl, |
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0 |
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}; |
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u32 *const clk_modules_hw_auto_non_essential[] = { |
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&prcm->cm_mpu_m3_mpu_m3_clkctrl, |
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&prcm->cm_ivahd_ivahd_clkctrl, |
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&prcm->cm_ivahd_sl2_clkctrl, |
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&prcm->cm_dsp_dsp_clkctrl, |
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&prcm->cm_l3_2_gpmc_clkctrl, |
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&prcm->cm_l3instr_l3_3_clkctrl, |
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&prcm->cm_l3instr_l3_instr_clkctrl, |
||||
&prcm->cm_l3instr_intrconn_wp1_clkctrl, |
||||
&prcm->cm_l3init_hsi_clkctrl, |
||||
&prcm->cm_l3init_hsusbtll_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_explicit_en_non_essential[] = { |
||||
&prcm->cm1_abe_aess_clkctrl, |
||||
&prcm->cm1_abe_pdm_clkctrl, |
||||
&prcm->cm1_abe_dmic_clkctrl, |
||||
&prcm->cm1_abe_mcasp_clkctrl, |
||||
&prcm->cm1_abe_mcbsp1_clkctrl, |
||||
&prcm->cm1_abe_mcbsp2_clkctrl, |
||||
&prcm->cm1_abe_mcbsp3_clkctrl, |
||||
&prcm->cm1_abe_slimbus_clkctrl, |
||||
&prcm->cm1_abe_timer5_clkctrl, |
||||
&prcm->cm1_abe_timer6_clkctrl, |
||||
&prcm->cm1_abe_timer7_clkctrl, |
||||
&prcm->cm1_abe_timer8_clkctrl, |
||||
&prcm->cm1_abe_wdt3_clkctrl, |
||||
&prcm->cm_l4per_gptimer9_clkctrl, |
||||
&prcm->cm_l4per_gptimer10_clkctrl, |
||||
&prcm->cm_l4per_gptimer11_clkctrl, |
||||
&prcm->cm_l4per_gptimer3_clkctrl, |
||||
&prcm->cm_l4per_gptimer4_clkctrl, |
||||
&prcm->cm_l4per_hdq1w_clkctrl, |
||||
&prcm->cm_l4per_mcbsp4_clkctrl, |
||||
&prcm->cm_l4per_mcspi2_clkctrl, |
||||
&prcm->cm_l4per_mcspi3_clkctrl, |
||||
&prcm->cm_l4per_mcspi4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd3_clkctrl, |
||||
&prcm->cm_l4per_mmcsd4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd5_clkctrl, |
||||
&prcm->cm_l4per_uart1_clkctrl, |
||||
&prcm->cm_l4per_uart2_clkctrl, |
||||
&prcm->cm_l4per_uart4_clkctrl, |
||||
&prcm->cm_wkup_keyboard_clkctrl, |
||||
&prcm->cm_wkup_wdtimer2_clkctrl, |
||||
&prcm->cm_cam_iss_clkctrl, |
||||
&prcm->cm_cam_fdif_clkctrl, |
||||
&prcm->cm_dss_dss_clkctrl, |
||||
&prcm->cm_sgx_sgx_clkctrl, |
||||
&prcm->cm_l3init_hsusbhost_clkctrl, |
||||
&prcm->cm_l3init_fsusb_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
/* Enable optional functional clock for ISS */ |
||||
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
/* Enable all optional functional clocks of DSS */ |
||||
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
do_enable_clocks(clk_domains_non_essential, |
||||
clk_modules_hw_auto_non_essential, |
||||
clk_modules_explicit_en_non_essential, |
||||
0); |
||||
|
||||
/* Put camera module in no sleep mode */ |
||||
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, |
||||
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << |
||||
MODULE_CLKCTRL_MODULEMODE_SHIFT); |
||||
} |
@ -0,0 +1,412 @@ |
||||
/*
|
||||
* |
||||
* Clock initialization for OMAP5 |
||||
* |
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Aneesh V <aneesh@ti.com> |
||||
* Sricharan R <r.sricharan@ti.com> |
||||
* |
||||
* Based on previous work by: |
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com> |
||||
* Rajendra Nayak <rnayak@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/omap_common.h> |
||||
#include <asm/arch/clocks.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/utils.h> |
||||
#include <asm/omap_gpio.h> |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
/*
|
||||
* printing to console doesn't work unless |
||||
* this code is executed from SPL |
||||
*/ |
||||
#define printf(fmt, args...) |
||||
#define puts(s) |
||||
#endif |
||||
|
||||
struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100; |
||||
|
||||
const u32 sys_clk_array[8] = { |
||||
12000000, /* 12 MHz */ |
||||
0, /* NA */ |
||||
16800000, /* 16.8 MHz */ |
||||
19200000, /* 19.2 MHz */ |
||||
26000000, /* 26 MHz */ |
||||
0, /* NA */ |
||||
38400000, /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { |
||||
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { |
||||
{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { |
||||
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { |
||||
{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params |
||||
core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { |
||||
{266, 2, 1, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{570, 8, 1, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ |
||||
{665, 11, 1, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ |
||||
{532, 12, 1, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{665, 23, 1, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params |
||||
core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { |
||||
{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ |
||||
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ |
||||
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { |
||||
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ |
||||
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ |
||||
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ |
||||
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { |
||||
{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ |
||||
{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ |
||||
{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ |
||||
{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ |
||||
{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ |
||||
{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ |
||||
{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
/* ABE M & N values with sys_clk as source */ |
||||
static const struct dpll_params |
||||
abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
||||
{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
/* ABE M & N values with 32K clock as source */ |
||||
static const struct dpll_params abe_dpll_params_32k_196608khz = { |
||||
750, 0, 1, 1, -1, -1, -1, -1 |
||||
}; |
||||
|
||||
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
||||
{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ |
||||
{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ |
||||
{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
||||
{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
||||
{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ |
||||
{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ |
||||
{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
||||
}; |
||||
|
||||
void setup_post_dividers(u32 *const base, const struct dpll_params *params) |
||||
{ |
||||
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
||||
|
||||
/* Setup post-dividers */ |
||||
if (params->m2 >= 0) |
||||
writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
||||
if (params->m3 >= 0) |
||||
writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
||||
if (params->h11 >= 0) |
||||
writel(params->h11, &dpll_regs->cm_div_h11_dpll); |
||||
if (params->h12 >= 0) |
||||
writel(params->h12, &dpll_regs->cm_div_h12_dpll); |
||||
if (params->h13 >= 0) |
||||
writel(params->h13, &dpll_regs->cm_div_h13_dpll); |
||||
if (params->h14 >= 0) |
||||
writel(params->h14, &dpll_regs->cm_div_h14_dpll); |
||||
if (params->h22 >= 0) |
||||
writel(params->h22, &dpll_regs->cm_div_h22_dpll); |
||||
if (params->h23 >= 0) |
||||
writel(params->h23, &dpll_regs->cm_div_h23_dpll); |
||||
} |
||||
|
||||
const struct dpll_params *get_mpu_dpll_params(void) |
||||
{ |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
return &mpu_dpll_params_1100mhz[sysclk_ind]; |
||||
} |
||||
|
||||
const struct dpll_params *get_core_dpll_params(void) |
||||
{ |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
|
||||
/* Configuring the DDR to be at 532mhz */ |
||||
return &core_dpll_params_2128mhz_ddr266[sysclk_ind]; |
||||
|
||||
} |
||||
|
||||
const struct dpll_params *get_per_dpll_params(void) |
||||
{ |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
return &per_dpll_params_768mhz[sysclk_ind]; |
||||
} |
||||
|
||||
const struct dpll_params *get_iva_dpll_params(void) |
||||
{ |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
return &iva_dpll_params_2330mhz[sysclk_ind]; |
||||
} |
||||
|
||||
const struct dpll_params *get_usb_dpll_params(void) |
||||
{ |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
return &usb_dpll_params_1920mhz[sysclk_ind]; |
||||
} |
||||
|
||||
const struct dpll_params *get_abe_dpll_params(void) |
||||
{ |
||||
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
||||
u32 sysclk_ind = get_sys_clk_index(); |
||||
return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; |
||||
#else |
||||
return &abe_dpll_params_32k_196608khz; |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
||||
* We set the maximum voltages allowed here because Smart-Reflex is not |
||||
* enabled in bootloader. Voltage initialization in the kernel will set |
||||
* these to the nominal values after enabling Smart-Reflex |
||||
*/ |
||||
void scale_vcores(void) |
||||
{ |
||||
u32 volt; |
||||
|
||||
setup_sri2c(); |
||||
|
||||
/* Enable 1.22V from TPS for vdd_mpu */ |
||||
volt = 1220; |
||||
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt); |
||||
|
||||
/* VCORE 1 - for vdd_core */ |
||||
volt = 1000; |
||||
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
||||
|
||||
/* VCORE 2 - for vdd_MM */ |
||||
volt = 1125; |
||||
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
||||
} |
||||
|
||||
/*
|
||||
* Enable essential clock domains, modules and |
||||
* do some additional special settings needed |
||||
*/ |
||||
void enable_basic_clocks(void) |
||||
{ |
||||
u32 *const clk_domains_essential[] = { |
||||
&prcm->cm_l4per_clkstctrl, |
||||
&prcm->cm_l3init_clkstctrl, |
||||
&prcm->cm_memif_clkstctrl, |
||||
&prcm->cm_l4cfg_clkstctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_hw_auto_essential[] = { |
||||
&prcm->cm_wkup_gpio1_clkctrl, |
||||
&prcm->cm_l4per_gpio2_clkctrl, |
||||
&prcm->cm_l4per_gpio3_clkctrl, |
||||
&prcm->cm_l4per_gpio4_clkctrl, |
||||
&prcm->cm_l4per_gpio5_clkctrl, |
||||
&prcm->cm_l4per_gpio6_clkctrl, |
||||
&prcm->cm_memif_emif_1_clkctrl, |
||||
&prcm->cm_memif_emif_2_clkctrl, |
||||
&prcm->cm_l4cfg_l4_cfg_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_explicit_en_essential[] = { |
||||
&prcm->cm_l4per_gptimer2_clkctrl, |
||||
&prcm->cm_l3init_hsmmc1_clkctrl, |
||||
&prcm->cm_l3init_hsmmc2_clkctrl, |
||||
&prcm->cm_l4per_mcspi1_clkctrl, |
||||
&prcm->cm_wkup_gptimer1_clkctrl, |
||||
&prcm->cm_l4per_i2c1_clkctrl, |
||||
&prcm->cm_l4per_i2c2_clkctrl, |
||||
&prcm->cm_l4per_i2c3_clkctrl, |
||||
&prcm->cm_l4per_i2c4_clkctrl, |
||||
&prcm->cm_wkup_wdtimer2_clkctrl, |
||||
&prcm->cm_l4per_uart3_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
/* Enable optional additional functional clock for GPIO4 */ |
||||
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, |
||||
GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
/* Enable 96 MHz clock for MMC1 & MMC2 */ |
||||
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, |
||||
HSMMC_CLKCTRL_CLKSEL_MASK); |
||||
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, |
||||
HSMMC_CLKCTRL_CLKSEL_MASK); |
||||
|
||||
/* Select 32KHz clock as the source of GPTIMER1 */ |
||||
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, |
||||
GPTIMER1_CLKCTRL_CLKSEL_MASK); |
||||
|
||||
do_enable_clocks(clk_domains_essential, |
||||
clk_modules_hw_auto_essential, |
||||
clk_modules_explicit_en_essential, |
||||
1); |
||||
} |
||||
|
||||
/*
|
||||
* Enable non-essential clock domains, modules and |
||||
* do some additional special settings needed |
||||
*/ |
||||
void enable_non_essential_clocks(void) |
||||
{ |
||||
u32 *const clk_domains_non_essential[] = { |
||||
&prcm->cm_mpu_m3_clkstctrl, |
||||
&prcm->cm_ivahd_clkstctrl, |
||||
&prcm->cm_dsp_clkstctrl, |
||||
&prcm->cm_dss_clkstctrl, |
||||
&prcm->cm_sgx_clkstctrl, |
||||
&prcm->cm1_abe_clkstctrl, |
||||
&prcm->cm_c2c_clkstctrl, |
||||
&prcm->cm_cam_clkstctrl, |
||||
&prcm->cm_dss_clkstctrl, |
||||
&prcm->cm_sdma_clkstctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_hw_auto_non_essential[] = { |
||||
&prcm->cm_mpu_m3_mpu_m3_clkctrl, |
||||
&prcm->cm_ivahd_ivahd_clkctrl, |
||||
&prcm->cm_ivahd_sl2_clkctrl, |
||||
&prcm->cm_dsp_dsp_clkctrl, |
||||
&prcm->cm_l3_2_gpmc_clkctrl, |
||||
&prcm->cm_l3instr_l3_3_clkctrl, |
||||
&prcm->cm_l3instr_l3_instr_clkctrl, |
||||
&prcm->cm_l3instr_intrconn_wp1_clkctrl, |
||||
&prcm->cm_l3init_hsi_clkctrl, |
||||
&prcm->cm_l3init_hsusbtll_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_explicit_en_non_essential[] = { |
||||
&prcm->cm1_abe_aess_clkctrl, |
||||
&prcm->cm1_abe_pdm_clkctrl, |
||||
&prcm->cm1_abe_dmic_clkctrl, |
||||
&prcm->cm1_abe_mcasp_clkctrl, |
||||
&prcm->cm1_abe_mcbsp1_clkctrl, |
||||
&prcm->cm1_abe_mcbsp2_clkctrl, |
||||
&prcm->cm1_abe_mcbsp3_clkctrl, |
||||
&prcm->cm1_abe_slimbus_clkctrl, |
||||
&prcm->cm1_abe_timer5_clkctrl, |
||||
&prcm->cm1_abe_timer6_clkctrl, |
||||
&prcm->cm1_abe_timer7_clkctrl, |
||||
&prcm->cm1_abe_timer8_clkctrl, |
||||
&prcm->cm1_abe_wdt3_clkctrl, |
||||
&prcm->cm_l4per_gptimer9_clkctrl, |
||||
&prcm->cm_l4per_gptimer10_clkctrl, |
||||
&prcm->cm_l4per_gptimer11_clkctrl, |
||||
&prcm->cm_l4per_gptimer3_clkctrl, |
||||
&prcm->cm_l4per_gptimer4_clkctrl, |
||||
&prcm->cm_l4per_hdq1w_clkctrl, |
||||
&prcm->cm_l4per_mcspi2_clkctrl, |
||||
&prcm->cm_l4per_mcspi3_clkctrl, |
||||
&prcm->cm_l4per_mcspi4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd3_clkctrl, |
||||
&prcm->cm_l4per_mmcsd4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd5_clkctrl, |
||||
&prcm->cm_l4per_uart1_clkctrl, |
||||
&prcm->cm_l4per_uart2_clkctrl, |
||||
&prcm->cm_l4per_uart4_clkctrl, |
||||
&prcm->cm_wkup_keyboard_clkctrl, |
||||
&prcm->cm_wkup_wdtimer2_clkctrl, |
||||
&prcm->cm_cam_iss_clkctrl, |
||||
&prcm->cm_cam_fdif_clkctrl, |
||||
&prcm->cm_dss_dss_clkctrl, |
||||
&prcm->cm_sgx_sgx_clkctrl, |
||||
&prcm->cm_l3init_hsusbhost_clkctrl, |
||||
&prcm->cm_l3init_fsusb_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
/* Enable optional functional clock for ISS */ |
||||
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
/* Enable all optional functional clocks of DSS */ |
||||
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
do_enable_clocks(clk_domains_non_essential, |
||||
clk_modules_hw_auto_non_essential, |
||||
clk_modules_explicit_en_non_essential, |
||||
0); |
||||
|
||||
/* Put camera module in no sleep mode */ |
||||
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, |
||||
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << |
||||
MODULE_CLKCTRL_MODULEMODE_SHIFT); |
||||
} |
@ -0,0 +1,721 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Aneesh V <aneesh@ti.com> |
||||
* Sricharan R <r.sricharan@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _CLOCKS_OMAP5_H_ |
||||
#define _CLOCKS_OMAP5_H_ |
||||
#include <common.h> |
||||
|
||||
/*
|
||||
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per |
||||
* loop, allow for a minimum of 2 ms wait (in reality the wait will be |
||||
* much more than that) |
||||
*/ |
||||
#define LDELAY 1000000 |
||||
|
||||
#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120) |
||||
#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140) |
||||
#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) |
||||
#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) |
||||
|
||||
struct omap5_prcm_regs { |
||||
/* cm1.ckgen */ |
||||
u32 cm_clksel_core; /* 4a004100 */ |
||||
u32 pad001[1]; /* 4a004104 */ |
||||
u32 cm_clksel_abe; /* 4a004108 */ |
||||
u32 pad002[1]; /* 4a00410c */ |
||||
u32 cm_dll_ctrl; /* 4a004110 */ |
||||
u32 pad003[3]; /* 4a004114 */ |
||||
u32 cm_clkmode_dpll_core; /* 4a004120 */ |
||||
u32 cm_idlest_dpll_core; /* 4a004124 */ |
||||
u32 cm_autoidle_dpll_core; /* 4a004128 */ |
||||
u32 cm_clksel_dpll_core; /* 4a00412c */ |
||||
u32 cm_div_m2_dpll_core; /* 4a004130 */ |
||||
u32 cm_div_m3_dpll_core; /* 4a004134 */ |
||||
u32 cm_div_h11_dpll_core; /* 4a004138 */ |
||||
u32 cm_div_h12_dpll_core; /* 4a00413c */ |
||||
u32 cm_div_h13_dpll_core; /* 4a004140 */ |
||||
u32 cm_div_h14_dpll_core; /* 4a004144 */ |
||||
u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */ |
||||
u32 cm_emu_override_dpll_core; /* 4a004150 */ |
||||
|
||||
u32 cm_div_h22_dpllcore; /* 4a004154 */ |
||||
u32 cm_div_h23_dpll_core; /* 4a004158 */ |
||||
u32 pad0041[1]; /* 4a00415c */ |
||||
u32 cm_clkmode_dpll_mpu; /* 4a004160 */ |
||||
u32 cm_idlest_dpll_mpu; /* 4a004164 */ |
||||
u32 cm_autoidle_dpll_mpu; /* 4a004168 */ |
||||
u32 cm_clksel_dpll_mpu; /* 4a00416c */ |
||||
u32 cm_div_m2_dpll_mpu; /* 4a004170 */ |
||||
u32 pad005[5]; /* 4a004174 */ |
||||
u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */ |
||||
u32 pad006[3]; /* 4a004190 */ |
||||
u32 cm_bypclk_dpll_mpu; /* 4a00419c */ |
||||
u32 cm_clkmode_dpll_iva; /* 4a0041a0 */ |
||||
u32 cm_idlest_dpll_iva; /* 4a0041a4 */ |
||||
u32 cm_autoidle_dpll_iva; /* 4a0041a8 */ |
||||
u32 cm_clksel_dpll_iva; /* 4a0041ac */ |
||||
u32 pad007[2]; /* 4a0041b0 */ |
||||
u32 cm_div_h11_dpll_iva; /* 4a0041b8 */ |
||||
u32 cm_div_h12_dpll_iva; /* 4a0041bc */ |
||||
u32 pad008[2]; /* 4a0041c0 */ |
||||
u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */ |
||||
u32 pad009[3]; /* 4a0041d0 */ |
||||
u32 cm_bypclk_dpll_iva; /* 4a0041dc */ |
||||
u32 cm_clkmode_dpll_abe; /* 4a0041e0 */ |
||||
u32 cm_idlest_dpll_abe; /* 4a0041e4 */ |
||||
u32 cm_autoidle_dpll_abe; /* 4a0041e8 */ |
||||
u32 cm_clksel_dpll_abe; /* 4a0041ec */ |
||||
u32 cm_div_m2_dpll_abe; /* 4a0041f0 */ |
||||
u32 cm_div_m3_dpll_abe; /* 4a0041f4 */ |
||||
u32 pad010[4]; /* 4a0041f8 */ |
||||
u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */ |
||||
u32 pad011[4]; /* 4a004210 */ |
||||
u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */ |
||||
u32 cm_idlest_dpll_ddrphy; /* 4a004224 */ |
||||
u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */ |
||||
u32 cm_clksel_dpll_ddrphy; /* 4a00422c */ |
||||
u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */ |
||||
u32 pad012[1]; /* 4a004234 */ |
||||
u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */ |
||||
u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */ |
||||
u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */ |
||||
u32 pad013[1]; /* 4a004244 */ |
||||
u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */ |
||||
u32 pad014[5]; /* 4a00424c */ |
||||
u32 cm_shadow_freq_config1; /* 4a004260 */ |
||||
u32 pad0141[47]; /* 4a004264 */ |
||||
u32 cm_mpu_mpu_clkctrl; /* 4a004320 */ |
||||
|
||||
|
||||
/* cm1.dsp */ |
||||
u32 pad015[55]; /* 4a004324 */ |
||||
u32 cm_dsp_clkstctrl; /* 4a004400 */ |
||||
u32 pad016[7]; /* 4a004404 */ |
||||
u32 cm_dsp_dsp_clkctrl; /* 4a004420 */ |
||||
|
||||
/* cm1.abe */ |
||||
u32 pad017[55]; /* 4a004424 */ |
||||
u32 cm1_abe_clkstctrl; /* 4a004500 */ |
||||
u32 pad018[7]; /* 4a004504 */ |
||||
u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */ |
||||
u32 pad019[1]; /* 4a004524 */ |
||||
u32 cm1_abe_aess_clkctrl; /* 4a004528 */ |
||||
u32 pad020[1]; /* 4a00452c */ |
||||
u32 cm1_abe_pdm_clkctrl; /* 4a004530 */ |
||||
u32 pad021[1]; /* 4a004534 */ |
||||
u32 cm1_abe_dmic_clkctrl; /* 4a004538 */ |
||||
u32 pad022[1]; /* 4a00453c */ |
||||
u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */ |
||||
u32 pad023[1]; /* 4a004544 */ |
||||
u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */ |
||||
u32 pad024[1]; /* 4a00454c */ |
||||
u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */ |
||||
u32 pad025[1]; /* 4a004554 */ |
||||
u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */ |
||||
u32 pad026[1]; /* 4a00455c */ |
||||
u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */ |
||||
u32 pad027[1]; /* 4a004564 */ |
||||
u32 cm1_abe_timer5_clkctrl; /* 4a004568 */ |
||||
u32 pad028[1]; /* 4a00456c */ |
||||
u32 cm1_abe_timer6_clkctrl; /* 4a004570 */ |
||||
u32 pad029[1]; /* 4a004574 */ |
||||
u32 cm1_abe_timer7_clkctrl; /* 4a004578 */ |
||||
u32 pad030[1]; /* 4a00457c */ |
||||
u32 cm1_abe_timer8_clkctrl; /* 4a004580 */ |
||||
u32 pad031[1]; /* 4a004584 */ |
||||
u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */ |
||||
|
||||
/* cm2.ckgen */ |
||||
u32 pad032[3805]; /* 4a00458c */ |
||||
u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */ |
||||
u32 cm_clksel_usb_60mhz; /* 4a008104 */ |
||||
u32 cm_scale_fclk; /* 4a008108 */ |
||||
u32 pad033[1]; /* 4a00810c */ |
||||
u32 cm_core_dvfs_perf1; /* 4a008110 */ |
||||
u32 cm_core_dvfs_perf2; /* 4a008114 */ |
||||
u32 cm_core_dvfs_perf3; /* 4a008118 */ |
||||
u32 cm_core_dvfs_perf4; /* 4a00811c */ |
||||
u32 pad034[1]; /* 4a008120 */ |
||||
u32 cm_core_dvfs_current; /* 4a008124 */ |
||||
u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */ |
||||
u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */ |
||||
u32 cm_iva_dvfs_perf_abe; /* 4a008130 */ |
||||
u32 pad035[1]; /* 4a008134 */ |
||||
u32 cm_iva_dvfs_current; /* 4a008138 */ |
||||
u32 pad036[1]; /* 4a00813c */ |
||||
u32 cm_clkmode_dpll_per; /* 4a008140 */ |
||||
u32 cm_idlest_dpll_per; /* 4a008144 */ |
||||
u32 cm_autoidle_dpll_per; /* 4a008148 */ |
||||
u32 cm_clksel_dpll_per; /* 4a00814c */ |
||||
u32 cm_div_m2_dpll_per; /* 4a008150 */ |
||||
u32 cm_div_m3_dpll_per; /* 4a008154 */ |
||||
u32 cm_div_h11_dpll_per; /* 4a008158 */ |
||||
u32 cm_div_h12_dpll_per; /* 4a00815c */ |
||||
u32 pad0361[1]; /* 4a008160 */ |
||||
u32 cm_div_h14_dpll_per; /* 4a008164 */ |
||||
u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */ |
||||
u32 cm_emu_override_dpll_per; /* 4a008170 */ |
||||
u32 pad037[3]; /* 4a008174 */ |
||||
u32 cm_clkmode_dpll_usb; /* 4a008180 */ |
||||
u32 cm_idlest_dpll_usb; /* 4a008184 */ |
||||
u32 cm_autoidle_dpll_usb; /* 4a008188 */ |
||||
u32 cm_clksel_dpll_usb; /* 4a00818c */ |
||||
u32 cm_div_m2_dpll_usb; /* 4a008190 */ |
||||
u32 pad038[5]; /* 4a008194 */ |
||||
u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */ |
||||
u32 pad039[1]; /* 4a0081b0 */ |
||||
u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */ |
||||
u32 pad040[2]; /* 4a0081b8 */ |
||||
u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */ |
||||
u32 cm_idlest_dpll_unipro; /* 4a0081c4 */ |
||||
u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */ |
||||
u32 cm_clksel_dpll_unipro; /* 4a0081cc */ |
||||
u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */ |
||||
u32 pad041[5]; /* 4a0081d4 */ |
||||
u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */ |
||||
u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */ |
||||
|
||||
/* cm2.core */ |
||||
u32 pad0411[324]; /* 4a0081f0 */ |
||||
u32 cm_l3_1_clkstctrl; /* 4a008700 */ |
||||
u32 pad042[1]; /* 4a008704 */ |
||||
u32 cm_l3_1_dynamicdep; /* 4a008708 */ |
||||
u32 pad043[5]; /* 4a00870c */ |
||||
u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */ |
||||
u32 pad044[55]; /* 4a008724 */ |
||||
u32 cm_l3_2_clkstctrl; /* 4a008800 */ |
||||
u32 pad045[1]; /* 4a008804 */ |
||||
u32 cm_l3_2_dynamicdep; /* 4a008808 */ |
||||
u32 pad046[5]; /* 4a00880c */ |
||||
u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */ |
||||
u32 pad047[1]; /* 4a008824 */ |
||||
u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */ |
||||
u32 pad048[1]; /* 4a00882c */ |
||||
u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */ |
||||
u32 pad049[51]; /* 4a008834 */ |
||||
u32 cm_mpu_m3_clkstctrl; /* 4a008900 */ |
||||
u32 cm_mpu_m3_staticdep; /* 4a008904 */ |
||||
u32 cm_mpu_m3_dynamicdep; /* 4a008908 */ |
||||
u32 pad050[5]; /* 4a00890c */ |
||||
u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */ |
||||
u32 pad051[55]; /* 4a008924 */ |
||||
u32 cm_sdma_clkstctrl; /* 4a008a00 */ |
||||
u32 cm_sdma_staticdep; /* 4a008a04 */ |
||||
u32 cm_sdma_dynamicdep; /* 4a008a08 */ |
||||
u32 pad052[5]; /* 4a008a0c */ |
||||
u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */ |
||||
u32 pad053[55]; /* 4a008a24 */ |
||||
u32 cm_memif_clkstctrl; /* 4a008b00 */ |
||||
u32 pad054[7]; /* 4a008b04 */ |
||||
u32 cm_memif_dmm_clkctrl; /* 4a008b20 */ |
||||
u32 pad055[1]; /* 4a008b24 */ |
||||
u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */ |
||||
u32 pad056[1]; /* 4a008b2c */ |
||||
u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */ |
||||
u32 pad057[1]; /* 4a008b34 */ |
||||
u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */ |
||||
u32 pad058[1]; /* 4a008b3c */ |
||||
u32 cm_memif_dll_clkctrl; /* 4a008b40 */ |
||||
u32 pad059[3]; /* 4a008b44 */ |
||||
u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */ |
||||
u32 pad060[1]; /* 4a008b54 */ |
||||
u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */ |
||||
u32 pad061[1]; /* 4a008b5c */ |
||||
u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */ |
||||
u32 pad062[39]; /* 4a008b64 */ |
||||
u32 cm_c2c_clkstctrl; /* 4a008c00 */ |
||||
u32 cm_c2c_staticdep; /* 4a008c04 */ |
||||
u32 cm_c2c_dynamicdep; /* 4a008c08 */ |
||||
u32 pad063[5]; /* 4a008c0c */ |
||||
u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */ |
||||
u32 pad064[1]; /* 4a008c24 */ |
||||
u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */ |
||||
u32 pad065[1]; /* 4a008c2c */ |
||||
u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */ |
||||
u32 pad066[51]; /* 4a008c34 */ |
||||
u32 cm_l4cfg_clkstctrl; /* 4a008d00 */ |
||||
u32 pad067[1]; /* 4a008d04 */ |
||||
u32 cm_l4cfg_dynamicdep; /* 4a008d08 */ |
||||
u32 pad068[5]; /* 4a008d0c */ |
||||
u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */ |
||||
u32 pad069[1]; /* 4a008d24 */ |
||||
u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */ |
||||
u32 pad070[1]; /* 4a008d2c */ |
||||
u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */ |
||||
u32 pad071[1]; /* 4a008d34 */ |
||||
u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */ |
||||
u32 pad072[49]; /* 4a008d3c */ |
||||
u32 cm_l3instr_clkstctrl; /* 4a008e00 */ |
||||
u32 pad073[7]; /* 4a008e04 */ |
||||
u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */ |
||||
u32 pad074[1]; /* 4a008e24 */ |
||||
u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */ |
||||
u32 pad075[5]; /* 4a008e2c */ |
||||
u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */ |
||||
|
||||
|
||||
/* cm2.ivahd */ |
||||
u32 pad076[47]; /* 4a008e44 */ |
||||
u32 cm_ivahd_clkstctrl; /* 4a008f00 */ |
||||
u32 pad077[7]; /* 4a008f04 */ |
||||
u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */ |
||||
u32 pad078[1]; /* 4a008f24 */ |
||||
u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */ |
||||
|
||||
/* cm2.cam */ |
||||
u32 pad079[53]; /* 4a008f2c */ |
||||
u32 cm_cam_clkstctrl; /* 4a009000 */ |
||||
u32 pad080[7]; /* 4a009004 */ |
||||
u32 cm_cam_iss_clkctrl; /* 4a009020 */ |
||||
u32 pad081[1]; /* 4a009024 */ |
||||
u32 cm_cam_fdif_clkctrl; /* 4a009028 */ |
||||
|
||||
/* cm2.dss */ |
||||
u32 pad082[53]; /* 4a00902c */ |
||||
u32 cm_dss_clkstctrl; /* 4a009100 */ |
||||
u32 pad083[7]; /* 4a009104 */ |
||||
u32 cm_dss_dss_clkctrl; /* 4a009120 */ |
||||
|
||||
/* cm2.sgx */ |
||||
u32 pad084[55]; /* 4a009124 */ |
||||
u32 cm_sgx_clkstctrl; /* 4a009200 */ |
||||
u32 pad085[7]; /* 4a009204 */ |
||||
u32 cm_sgx_sgx_clkctrl; /* 4a009220 */ |
||||
|
||||
/* cm2.l3init */ |
||||
u32 pad086[55]; /* 4a009224 */ |
||||
u32 cm_l3init_clkstctrl; /* 4a009300 */ |
||||
|
||||
/* cm2.l3init */ |
||||
u32 pad087[9]; /* 4a009304 */ |
||||
u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */ |
||||
u32 pad088[1]; /* 4a00932c */ |
||||
u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */ |
||||
u32 pad089[1]; /* 4a009334 */ |
||||
u32 cm_l3init_hsi_clkctrl; /* 4a009338 */ |
||||
u32 pad090[7]; /* 4a00933c */ |
||||
u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */ |
||||
u32 pad091[1]; /* 4a00935c */ |
||||
u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */ |
||||
u32 pad092[1]; /* 4a009364 */ |
||||
u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */ |
||||
u32 pad093[3]; /* 4a00936c */ |
||||
u32 cm_l3init_p1500_clkctrl; /* 4a009378 */ |
||||
u32 pad094[21]; /* 4a00937c */ |
||||
u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */ |
||||
u32 pad095[3]; /* 4a0093d4 */ |
||||
u32 cm_l3init_ocp2scp1_clkctrl; |
||||
|
||||
/* cm2.l4per */ |
||||
u32 pad096[7]; /* 4a0093e4 */ |
||||
u32 cm_l4per_clkstctrl; /* 4a009400 */ |
||||
u32 pad097[1]; /* 4a009404 */ |
||||
u32 cm_l4per_dynamicdep; /* 4a009408 */ |
||||
u32 pad098[5]; /* 4a00940c */ |
||||
u32 cm_l4per_adc_clkctrl; /* 4a009420 */ |
||||
u32 pad100[1]; /* 4a009424 */ |
||||
u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */ |
||||
u32 pad101[1]; /* 4a00942c */ |
||||
u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */ |
||||
u32 pad102[1]; /* 4a009434 */ |
||||
u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */ |
||||
u32 pad103[1]; /* 4a00943c */ |
||||
u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */ |
||||
u32 pad104[1]; /* 4a009444 */ |
||||
u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */ |
||||
u32 pad105[1]; /* 4a00944c */ |
||||
u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */ |
||||
u32 pad106[1]; /* 4a009454 */ |
||||
u32 cm_l4per_elm_clkctrl; /* 4a009458 */ |
||||
u32 pad107[1]; /* 4a00945c */ |
||||
u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */ |
||||
u32 pad108[1]; /* 4a009464 */ |
||||
u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */ |
||||
u32 pad109[1]; /* 4a00946c */ |
||||
u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */ |
||||
u32 pad110[1]; /* 4a009474 */ |
||||
u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */ |
||||
u32 pad111[1]; /* 4a00947c */ |
||||
u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */ |
||||
u32 pad112[1]; /* 4a009484 */ |
||||
u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */ |
||||
u32 pad113[1]; /* 4a00948c */ |
||||
u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */ |
||||
u32 pad114[1]; /* 4a009494 */ |
||||
u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */ |
||||
u32 pad115[1]; /* 4a00949c */ |
||||
u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */ |
||||
u32 pad116[1]; /* 4a0094a4 */ |
||||
u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */ |
||||
u32 pad117[1]; /* 4a0094ac */ |
||||
u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */ |
||||
u32 pad118[1]; /* 4a0094b4 */ |
||||
u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */ |
||||
u32 pad119[1]; /* 4a0094bc */ |
||||
u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */ |
||||
u32 pad1191[3]; /* 4a0094c4 */ |
||||
u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */ |
||||
u32 pad120[1]; /* 4a0094d4 */ |
||||
u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */ |
||||
u32 pad121[3]; /* 4a0094dc */ |
||||
u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */ |
||||
u32 pad123[1]; /* 4a0094ec */ |
||||
u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */ |
||||
u32 pad124[1]; /* 4a0094f4 */ |
||||
u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */ |
||||
u32 pad125[1]; /* 4a0094fc */ |
||||
u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */ |
||||
u32 pad126[1]; /* 4a009504 */ |
||||
u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */ |
||||
u32 pad127[1]; /* 4a00950c */ |
||||
u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */ |
||||
u32 pad1271[1]; /* 4a009514 */ |
||||
u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */ |
||||
u32 pad1272[1]; /* 4a00951c */ |
||||
u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */ |
||||
u32 pad128[1]; /* 4a009524 */ |
||||
u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */ |
||||
u32 pad129[1]; /* 4a00952c */ |
||||
u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */ |
||||
u32 pad130[1]; /* 4a009534 */ |
||||
u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */ |
||||
u32 pad131[1]; /* 4a00953c */ |
||||
u32 cm_l4per_uart1_clkctrl; /* 4a009540 */ |
||||
u32 pad132[1]; /* 4a009544 */ |
||||
u32 cm_l4per_uart2_clkctrl; /* 4a009548 */ |
||||
u32 pad133[1]; /* 4a00954c */ |
||||
u32 cm_l4per_uart3_clkctrl; /* 4a009550 */ |
||||
u32 pad134[1]; /* 4a009554 */ |
||||
u32 cm_l4per_uart4_clkctrl; /* 4a009558 */ |
||||
u32 pad135[1]; /* 4a00955c */ |
||||
u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */ |
||||
u32 pad136[1]; /* 4a009564 */ |
||||
u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */ |
||||
u32 pad1371[1]; /* 4a00956c */ |
||||
u32 cm_l4per_uart5_clkctrl; /* 4a009570 */ |
||||
u32 pad1372[1]; /* 4a009574 */ |
||||
u32 cm_l4per_uart6_clkctrl; /* 4a009578 */ |
||||
u32 pad1374[1]; /* 4a00957c */ |
||||
u32 cm_l4sec_clkstctrl; /* 4a009580 */ |
||||
u32 cm_l4sec_staticdep; /* 4a009584 */ |
||||
u32 cm_l4sec_dynamicdep; /* 4a009588 */ |
||||
u32 pad138[5]; /* 4a00958c */ |
||||
u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */ |
||||
u32 pad139[1]; /* 4a0095a4 */ |
||||
u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */ |
||||
u32 pad140[1]; /* 4a0095ac */ |
||||
u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */ |
||||
u32 pad141[1]; /* 4a0095b4 */ |
||||
u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */ |
||||
u32 pad142[1]; /* 4a0095bc */ |
||||
u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */ |
||||
u32 pad143[1]; /* 4a0095c4 */ |
||||
u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */ |
||||
u32 pad144[3]; /* 4a0095cc */ |
||||
u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */ |
||||
u32 pad145[3660425]; /* 4a0095dc */ |
||||
|
||||
/* l4 wkup regs */ |
||||
u32 pad201[6211]; /* 4ae00000 */ |
||||
u32 cm_abe_pll_ref_clksel; /* 4ae0610c */ |
||||
u32 cm_sys_clksel; /* 4ae06110 */ |
||||
u32 pad202[1467]; /* 4ae06114 */ |
||||
u32 cm_wkup_clkstctrl; /* 4ae07800 */ |
||||
u32 pad203[7]; /* 4ae07804 */ |
||||
u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */ |
||||
u32 pad204; /* 4ae07824 */ |
||||
u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */ |
||||
u32 pad205; /* 4ae0782c */ |
||||
u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */ |
||||
u32 pad206; /* 4ae07834 */ |
||||
u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */ |
||||
u32 pad207; /* 4ae0783c */ |
||||
u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */ |
||||
u32 pad208; /* 4ae07844 */ |
||||
u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */ |
||||
u32 pad209; /* 4ae0784c */ |
||||
u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */ |
||||
u32 pad210; /* 4ae07854 */ |
||||
u32 cm_wkup_usim_clkctrl; /* 4ae07858 */ |
||||
u32 pad211; /* 4ae0785c */ |
||||
u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */ |
||||
u32 pad212[5]; /* 4ae07864 */ |
||||
u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */ |
||||
u32 pad213; /* 4ae0787c */ |
||||
u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ |
||||
u32 pad214; /* 4ae07884 */ |
||||
u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ |
||||
u32 pad215[197]; /* 4ae0788c */ |
||||
u32 prm_vc_val_bypass; /* 4ae07ba0 */ |
||||
u32 pad216[4]; |
||||
u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ |
||||
u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ |
||||
}; |
||||
|
||||
/* DPLL register offsets */ |
||||
#define CM_CLKMODE_DPLL 0 |
||||
#define CM_IDLEST_DPLL 0x4 |
||||
#define CM_AUTOIDLE_DPLL 0x8 |
||||
#define CM_CLKSEL_DPLL 0xC |
||||
|
||||
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ |
||||
|
||||
/* CM_CLKMODE_DPLL */ |
||||
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 |
||||
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) |
||||
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 |
||||
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) |
||||
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 |
||||
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) |
||||
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 |
||||
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
||||
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 |
||||
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) |
||||
#define CM_CLKMODE_DPLL_EN_SHIFT 0 |
||||
#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) |
||||
|
||||
#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 |
||||
#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 |
||||
|
||||
#define DPLL_EN_STOP 1 |
||||
#define DPLL_EN_MN_BYPASS 4 |
||||
#define DPLL_EN_LOW_POWER_BYPASS 5 |
||||
#define DPLL_EN_FAST_RELOCK_BYPASS 6 |
||||
#define DPLL_EN_LOCK 7 |
||||
|
||||
/* CM_IDLEST_DPLL fields */ |
||||
#define ST_DPLL_CLK_MASK 1 |
||||
|
||||
/* CM_CLKSEL_DPLL */ |
||||
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 |
||||
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) |
||||
#define CM_CLKSEL_DPLL_M_SHIFT 8 |
||||
#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) |
||||
#define CM_CLKSEL_DPLL_N_SHIFT 0 |
||||
#define CM_CLKSEL_DPLL_N_MASK 0x7F |
||||
#define CM_CLKSEL_DCC_EN_SHIFT 22 |
||||
#define CM_CLKSEL_DCC_EN_MASK (1 << 22) |
||||
|
||||
#define OMAP4_DPLL_MAX_N 127 |
||||
|
||||
/* CM_SYS_CLKSEL */ |
||||
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 |
||||
|
||||
/* CM_CLKSEL_CORE */ |
||||
#define CLKSEL_CORE_SHIFT 0 |
||||
#define CLKSEL_L3_SHIFT 4 |
||||
#define CLKSEL_L4_SHIFT 8 |
||||
|
||||
#define CLKSEL_CORE_X2_DIV_1 0 |
||||
#define CLKSEL_L3_CORE_DIV_2 1 |
||||
#define CLKSEL_L4_L3_DIV_2 1 |
||||
|
||||
/* CM_ABE_PLL_REF_CLKSEL */ |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 |
||||
|
||||
/* CM_BYPCLK_DPLL_IVA */ |
||||
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 |
||||
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 |
||||
|
||||
#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 |
||||
|
||||
/* CM_SHADOW_FREQ_CONFIG1 */ |
||||
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 |
||||
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 |
||||
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 |
||||
|
||||
#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 |
||||
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) |
||||
|
||||
#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 |
||||
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) |
||||
|
||||
/*CM_<clock_domain>__CLKCTRL */ |
||||
#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 |
||||
#define CD_CLKCTRL_CLKTRCTRL_MASK 3 |
||||
|
||||
#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 |
||||
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 |
||||
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 |
||||
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 |
||||
|
||||
|
||||
/* CM_<clock_domain>_<module>_CLKCTRL */ |
||||
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 |
||||
#define MODULE_CLKCTRL_MODULEMODE_MASK 3 |
||||
#define MODULE_CLKCTRL_IDLEST_SHIFT 16 |
||||
#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) |
||||
|
||||
#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 |
||||
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 |
||||
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 |
||||
|
||||
#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 |
||||
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 |
||||
#define MODULE_CLKCTRL_IDLEST_IDLE 2 |
||||
#define MODULE_CLKCTRL_IDLEST_DISABLED 3 |
||||
|
||||
/* CM_L4PER_GPIO4_CLKCTRL */ |
||||
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) |
||||
|
||||
/* CM_L3INIT_HSMMCn_CLKCTRL */ |
||||
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) |
||||
|
||||
/* CM_WKUP_GPTIMER1_CLKCTRL */ |
||||
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) |
||||
|
||||
/* CM_CAM_ISS_CLKCTRL */ |
||||
#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) |
||||
|
||||
/* CM_DSS_DSS_CLKCTRL */ |
||||
#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 |
||||
|
||||
/* CM_L3INIT_USBPHY_CLKCTRL */ |
||||
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 |
||||
|
||||
/* CM_MPU_MPU_CLKCTRL */ |
||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 |
||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) |
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 |
||||
#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) |
||||
|
||||
/* Clock frequencies */ |
||||
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 |
||||
#define OMAP_SYS_CLK_IND_38_4_MHZ 6 |
||||
#define OMAP_32K_CLK_FREQ 32768 |
||||
|
||||
/* PRM_VC_CFG_I2C_CLK */ |
||||
#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 |
||||
#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF |
||||
#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 |
||||
#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) |
||||
|
||||
/* PRM_VC_VAL_BYPASS */ |
||||
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 |
||||
|
||||
#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 |
||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 |
||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F |
||||
#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 |
||||
#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF |
||||
#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 |
||||
#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF |
||||
|
||||
/* SMPS */ |
||||
#define SMPS_I2C_SLAVE_ADDR 0x12 |
||||
#define SMPS_REG_ADDR_VCORE1 0x55 |
||||
#define SMPS_REG_ADDR_VCORE2 0x5B |
||||
#define SMPS_REG_ADDR_VCORE3 0x61 |
||||
|
||||
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 |
||||
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 |
||||
|
||||
/* TPS */ |
||||
#define TPS62361_I2C_SLAVE_ADDR 0x60 |
||||
#define TPS62361_REG_ADDR_SET0 0x0 |
||||
#define TPS62361_REG_ADDR_SET1 0x1 |
||||
#define TPS62361_REG_ADDR_SET2 0x2 |
||||
#define TPS62361_REG_ADDR_SET3 0x3 |
||||
#define TPS62361_REG_ADDR_CTRL 0x4 |
||||
#define TPS62361_REG_ADDR_TEMP 0x5 |
||||
#define TPS62361_REG_ADDR_RMP_CTRL 0x6 |
||||
#define TPS62361_REG_ADDR_CHIP_ID 0x8 |
||||
#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 |
||||
|
||||
#define TPS62361_BASE_VOLT_MV 500 |
||||
#define TPS62361_VSEL0_GPIO 7 |
||||
|
||||
/* Defines for DPLL setup */ |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 |
||||
|
||||
#define DPLL_NO_LOCK 0 |
||||
#define DPLL_LOCK 1 |
||||
|
||||
#define NUM_SYS_CLKS 7 |
||||
|
||||
struct dpll_regs { |
||||
u32 cm_clkmode_dpll; |
||||
u32 cm_idlest_dpll; |
||||
u32 cm_autoidle_dpll; |
||||
u32 cm_clksel_dpll; |
||||
u32 cm_div_m2_dpll; |
||||
u32 cm_div_m3_dpll; |
||||
u32 cm_div_h11_dpll; |
||||
u32 cm_div_h12_dpll; |
||||
u32 cm_div_h13_dpll; |
||||
u32 cm_div_h14_dpll; |
||||
u32 reserved[2]; |
||||
u32 cm_div_h22_dpll; |
||||
u32 cm_div_h23_dpll; |
||||
}; |
||||
|
||||
/* DPLL parameter table */ |
||||
struct dpll_params { |
||||
u32 m; |
||||
u32 n; |
||||
u8 m2; |
||||
u8 m3; |
||||
u8 h11; |
||||
u8 h12; |
||||
u8 h13; |
||||
u8 h14; |
||||
u8 h22; |
||||
u8 h23; |
||||
}; |
||||
|
||||
extern struct omap5_prcm_regs *const prcm; |
||||
extern const u32 sys_clk_array[8]; |
||||
|
||||
void scale_vcores(void); |
||||
void do_scale_tps62361(u32 reg, u32 volt_mv); |
||||
u32 omap_ddr_clk(void); |
||||
void do_scale_vcore(u32 vcore_reg, u32 volt_mv); |
||||
void setup_sri2c(void); |
||||
void setup_post_dividers(u32 *const base, const struct dpll_params *params); |
||||
u32 get_sys_clk_index(void); |
||||
void enable_basic_clocks(void); |
||||
void enable_non_essential_clocks(void); |
||||
void do_enable_clocks(u32 *const *clk_domains, |
||||
u32 *const *clk_modules_hw_auto, |
||||
u32 *const *clk_modules_explicit_en, |
||||
u8 wait_for_enable); |
||||
const struct dpll_params *get_mpu_dpll_params(void); |
||||
const struct dpll_params *get_core_dpll_params(void); |
||||
const struct dpll_params *get_per_dpll_params(void); |
||||
const struct dpll_params *get_iva_dpll_params(void); |
||||
const struct dpll_params *get_usb_dpll_params(void); |
||||
const struct dpll_params *get_abe_dpll_params(void); |
||||
#endif /* _CLOCKS_OMAP5_H_ */ |
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Reference in new issue