Tom Rini
6 years ago
commit
2f4c9de3d0
@ -1,48 +0,0 @@ |
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/*
|
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* Copyright (C) 2016 Amarula Solutions B.V. |
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* Copyright (C) 2016 Engicam S.r.l. |
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* Author: Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifdef CONFIG_ENV_IS_IN_MMC |
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int board_mmc_get_env_dev(int devno) |
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{ |
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return devno - 1; |
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} |
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#endif |
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#ifdef CONFIG_SPL_BUILD |
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#include <spl.h> |
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#ifdef CONFIG_ENV_IS_IN_MMC |
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void board_boot_order(u32 *spl_boot_list) |
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{ |
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u32 bmode = imx6_src_get_boot_mode(); |
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u8 boot_dev = BOOT_DEVICE_MMC1; |
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switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { |
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case IMX6_BMODE_SD: |
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case IMX6_BMODE_ESD: |
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/* SD/eSD - BOOT_DEVICE_MMC1 */ |
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break; |
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case IMX6_BMODE_MMC: |
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case IMX6_BMODE_EMMC: |
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/* MMC/eMMC */ |
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boot_dev = BOOT_DEVICE_MMC2; |
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break; |
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default: |
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/* Default - BOOT_DEVICE_MMC1 */ |
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printf("Wrong board boot order\n"); |
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break; |
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} |
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spl_boot_list[0] = boot_dev; |
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} |
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#endif |
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#endif /* CONFIG_SPL_BUILD */ |
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@ -0,0 +1,235 @@ |
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if TARGET_MX6MEMCAL |
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config SYS_BOARD |
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default "mx6memcal" |
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config SYS_VENDOR |
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default "freescale" |
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config SYS_CONFIG_NAME |
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default "mx6memcal" |
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menu "mx6memcal specifics" |
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choice |
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prompt "Serial console" |
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help |
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Either UART1 or UART2 will be used as the console for |
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displaying the calibration values or errors. |
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|
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config SERIAL_CONSOLE_UART1 |
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bool "UART1" |
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help |
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Select this if your board uses UART1 for its' console. |
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|
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config SERIAL_CONSOLE_UART2 |
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bool "UART2" |
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help |
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Select this if your board uses UART2 for its' console. |
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endchoice |
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choice |
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prompt "UART pads" |
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help |
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Select the RX and TX pads used for your serial console. |
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The choices below reflect the most commonly used options |
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for your UART. |
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config UART2_EIM_D26_27 |
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bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" |
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depends on SERIAL_CONSOLE_UART2 |
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help |
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Choose this configuration if you're using pads |
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EIM_D26 and D27 for a console on UART2. |
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This is typical for designs that are based on the |
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NXP SABRELite. |
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config UART1_CSI0_DAT10_11 |
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bool "UART1 on CSI0_DAT10/11 (Wand)" |
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depends on SERIAL_CONSOLE_UART1 |
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help |
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Choose this configuration if you're using pads |
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CSI0_DAT10 and DAT11 for a console on UART1 as |
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is done on the i.MX6 Wand board. |
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|
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config UART1_SD3_DAT6_7 |
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bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)" |
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depends on SERIAL_CONSOLE_UART1 |
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help |
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Choose this configuration if you're using pads |
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SD3_DAT6 and DAT7 for a console on UART1 as is |
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done on the NXP SABRESD or SABREAUTO designs. |
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config UART1_UART1 |
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bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" |
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depends on SERIAL_CONSOLE_UART1 |
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help |
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Choose this configuration if you're using pads |
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UART1_TXD/RXD for a console on UART1 as is done |
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on most i.MX6SL designs. |
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endchoice |
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config IMXIMAGE_OUTPUT |
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bool "Include output for imximage .cfg files" |
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default y |
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help |
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Say "Y" if you want output formatted for use in non-SPL |
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(DCD-style) configuration files. |
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|
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config DDRWIDTH |
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int "DDR bus width" |
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default 64 |
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help |
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Select either 32 or 64 to reflect the DDR bus width. |
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config DDRCS |
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int "DDR chip selects" |
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default 2 |
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range 1 2 |
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help |
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Select the number of chip selects used in your board design |
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choice |
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prompt "Memory type" |
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help |
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Select the type of DDR (DDR3 or LPDDR2) used on your design |
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config DDR3 |
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bool "DDR3" |
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help |
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Select this if your board design uses DDR3. |
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config LPDDR2 |
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bool "LPDDR2" |
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help |
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Select this if your board design uses LPDDR2. |
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endchoice |
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choice |
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prompt "Memory device" |
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config MT41K512M16TNA |
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bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)" |
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depends on DDR3 |
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config MT41K128M16JT |
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bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)" |
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depends on DDR3 |
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config H5TQ4G63AFR |
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bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)" |
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depends on DDR3 |
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config H5TQ2G63DFR |
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bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)" |
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depends on DDR3 |
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config MT42L256M32D2LG |
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bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)" |
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depends on LPDDR2 |
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config MT29PZZZ4D4BKESK |
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bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC" |
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depends on LPDDR2 |
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endchoice |
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config DDR_ODT |
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int "DDR On-die-termination" |
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default 2 |
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range 0 7 |
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help |
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Enter the on-die termination value as an index defined for |
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IOMUX settings for PAD_DRAM_SDCLK0_P and others. |
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0 == Disabled |
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1 == 120 Ohm |
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2 == 60 Ohm |
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3 == 40 Ohm |
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4 == 30 Ohm |
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5 == 24 Ohm |
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6 == 20 Ohm |
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7 == 17 Ohm |
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Value will be applied to all clock and data lines |
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config DRAM_DRIVE_STRENGTH |
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int "DRAM Drive strength" |
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default 6 |
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range 0 7 |
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help |
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Enter drive strength as an index defined for IOMUX settings |
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for GRP_B1DS and others. |
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0 == Hi Z |
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6 == 40 Ohm (default) |
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7 == 34 Ohm |
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Value will be applied to all clock and data lines |
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config RTT_NOM |
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int "RTT_NOM" |
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default 1 |
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range 1 2 |
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help |
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Enter the RTT_NOM selector |
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1 == RZQ/4 (60ohm) |
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2 == RZQ/2 (120ohm) |
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config RTT_WR |
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int "RTT_WR" |
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default 1 |
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range 0 2 |
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help |
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Enter the RTT_WR selector for MR2 |
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0 == Dynamic ODT disabled |
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1 == RZQ/4 (60ohm) |
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2 == RZQ/2 (120ohm) |
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config RALAT |
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int "Read additional latency" |
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default 5 |
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range 0 7 |
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help |
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Enter a latency in number of cycles. This will be added to |
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CAS and internal delays for which the MMDC will retrieve the |
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read data from the internal FIFO. |
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This is used to compensate for board/chip delays. |
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config WALAT |
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int "Write additional latency" |
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default 0 |
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range 0 7 |
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help |
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Enter a latency in number of cycles. This will be added to |
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CAS and internal delays for which the MMDC will retrieve the |
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read data from the internal FIFO |
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This is used to compensate for board/chip delays. |
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config REFSEL |
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int "Refresh period" |
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range 0 3 |
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default 1 |
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help |
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Select the DDR refresh period. |
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See the description of bitfield REF_SEL in the reference manual |
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for details. |
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0 == disabled |
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1 == 32 kHz |
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2 == 64 kHz |
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3 == fast counter |
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config REFR |
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int "Number of refreshes" |
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range 0 7 |
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default 7 |
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help |
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This selects the number of refreshes (-1) during each period. |
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i.e.: |
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0 == 1 refresh (tRFC) |
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7 == 8 refreshes (tRFC*8) |
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See the description of MDREF[REFR] in the reference manual for |
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details. |
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endmenu |
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endif |
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@ -0,0 +1,7 @@ |
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MX6MEMCAL BOARD |
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M: Eric Nelson <eric@nelint.com> |
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S: Maintained |
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F: board/freescale/mx6memcal/ |
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F: include/configs/mx6memcal.h |
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F: configs/mx6memcal_defconfig |
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@ -0,0 +1,13 @@ |
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-y := spl.o
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else |
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obj-y := mx6memcal.o
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endif |
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@ -0,0 +1,49 @@ |
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mx6memcal - a tool for calibrating DDR on i.MX6 boards. |
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The mx6memcal board isn't a real board, but a tool for use in bring-up of |
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new i.MX6 board designs. |
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It provides a similar function to the tool from NXP([1]) with a number |
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of advantages: |
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1. It's open-source, so it's easier to change if needed. |
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Typical reasons for needing to change include the use of alternate |
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UARTs and PMIC initialization. |
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2. It produces an image that's directly loadable with imx_usb [2] or |
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SB_LOADER.exe [3]. |
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The NXP tool requires either a cumbersome JTAG connection that |
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makes running the DDR very slow or a working U-Boot image that |
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suffers from a chicken-and-egg problem (i.e. where do you get the |
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DDR parameters for U-Boot?). |
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3. It doesn't prompt for parameters, so it's much faster to gather |
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data from multiple boards. |
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4. Parameters to the calibration process can be chosen through |
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'make menuconfig'. |
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When booted, the mx6memcal board will run the DDR calibration |
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routines and display the result in a form suitable for cut and |
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paste into struct mx6_mmdc_calibration. It can also optionally |
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produce output in a form usable in a DCD-style .cfg file. |
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Selections in Kconfig allow most system design settings to be chosen: |
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1. The UART number and pad configuration for the UART. Options |
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include support for the most frequent reference designs on |
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i.MX6DQ/SDL (SABRE Lite and SABRESD designs). |
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2. The memory bus width (64 and 32-bit) |
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3. The number of chip-selects in use |
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4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support |
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is incomplete as of this writing. |
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5. The type of DDR chips in use. This selection allows re-use of common |
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parts and four DDR3 and two LPDDR2 parts are currently defined |
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6. The On-die termination value for the DRAM lines |
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7. The DRAM drive strength |
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8. The RTT_NOM and RTT_WR termination settings |
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9. RALAT/WALAT latency values |
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References: |
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[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652 |
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[2] - Boundary Devices imx_usb_loader |
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https://github.com/boundarydevices/imx_usb_loader |
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[3] - Use of SB_Loader.exe |
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https://boundarydevices.com/windows-users-and-unbricking |
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@ -0,0 +1,32 @@ |
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/*
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* mx6memcal board support - provides a minimal, UART-only |
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* U-Boot that's capable of running a memory test. |
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* |
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* Copyright (C) 2016 Nelson Integration, LLC |
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* Author: Eric Nelson <eric@nelint.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: mx6memcal\n"); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = imx_ddr_size(); |
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return 0; |
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} |
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@ -0,0 +1,456 @@ |
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/*
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* Copyright (C) 2016 Nelson Integration, LLC |
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* Author: Eric Nelson <eric@nelint.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mx6-ddr.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <spl.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const uart_pads[] = { |
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#ifdef CONFIG_UART2_EIM_D26_27 |
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IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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#elif defined(CONFIG_UART1_CSI0_DAT10_11) |
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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#elif defined(CONFIG_UART1_SD3_DAT6_7) |
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IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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#elif defined(CONFIG_UART1_UART1) |
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MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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#else |
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#error select UART console pads |
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#endif |
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}; |
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|
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#ifdef CONFIG_DDR3 |
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#define GRP_DDRTYPE 0x000C0000 |
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#else |
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#define GRP_DDRTYPE 0x00080000 |
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#endif |
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|
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/* all existing designs have this disabled */ |
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#define DDR_PKE 0 |
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|
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/* use Kconfig for ODT and DRIVE_STRENGTH */ |
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#define DDR_ODT \ |
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(CONFIG_DDR_ODT << 8) |
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#define DRAM_DRIVE_STRENGTH \ |
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(CONFIG_DRAM_DRIVE_STRENGTH << 3) |
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|
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/* configure MX6Q/DUAL mmdc DDR io registers */ |
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static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = { |
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
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.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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/* SDCKE[0:1]: 100k pull-up */ |
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.dram_sdcke0 = 0x00003000, |
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.dram_sdcke1 = 0x00003000, |
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/* SDBA2: pull-up disabled */ |
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.dram_sdba2 = 0x00000000, |
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/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
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.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, |
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.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, |
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/* SDQS[0:7]: Differential input, 40 ohm */ |
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.dram_sdqs0 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs1 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs2 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs3 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs4 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs5 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs6 = DRAM_DRIVE_STRENGTH, |
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.dram_sdqs7 = DRAM_DRIVE_STRENGTH, |
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|
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/* DQM[0:7]: Differential input, 40 ohm */ |
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.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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}; |
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|
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/* configure MX6Q/DUAL mmdc GRP io registers */ |
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static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = { |
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/* DDR3 */ |
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.grp_ddr_type = GRP_DDRTYPE, |
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.grp_ddrmode_ctl = DDR_ODT, |
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/* disable DDR pullups */ |
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.grp_ddrpke = DDR_PKE, |
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
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.grp_addds = DRAM_DRIVE_STRENGTH, |
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
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.grp_ctlds = DRAM_DRIVE_STRENGTH, |
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/* DATA[00:63]: Differential input, 40 ohm */ |
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.grp_ddrmode = DDR_ODT, |
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.grp_b0ds = DRAM_DRIVE_STRENGTH, |
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.grp_b1ds = DRAM_DRIVE_STRENGTH, |
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.grp_b2ds = DRAM_DRIVE_STRENGTH, |
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.grp_b3ds = DRAM_DRIVE_STRENGTH, |
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.grp_b4ds = DRAM_DRIVE_STRENGTH, |
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.grp_b5ds = DRAM_DRIVE_STRENGTH, |
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.grp_b6ds = DRAM_DRIVE_STRENGTH, |
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.grp_b7ds = DRAM_DRIVE_STRENGTH, |
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}; |
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|
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static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = { |
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
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.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
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.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
/* SDCKE[0:1]: 100k pull-up */ |
||||
.dram_sdcke0 = 0x00003000, |
||||
.dram_sdcke1 = 0x00003000, |
||||
/* SDBA2: pull-up disabled */ |
||||
.dram_sdba2 = 0x00000000, |
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
||||
.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, |
||||
.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.dram_sdqs0 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs4 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs5 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs6 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs7 = DRAM_DRIVE_STRENGTH, |
||||
|
||||
/* DQM[0:7]: Differential input, 40 ohm */ |
||||
.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
||||
static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = { |
||||
/* DDR3 */ |
||||
.grp_ddr_type = GRP_DDRTYPE, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.grp_ddrmode_ctl = DDR_ODT, |
||||
/* disable DDR pullups */ |
||||
.grp_ddrpke = DDR_PKE, |
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
||||
.grp_addds = DRAM_DRIVE_STRENGTH, |
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
||||
.grp_ctlds = DRAM_DRIVE_STRENGTH, |
||||
/* DATA[00:63]: Differential input, 40 ohm */ |
||||
.grp_ddrmode = DDR_ODT, |
||||
.grp_b0ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b1ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b2ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b3ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b4ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b5ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b6ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b7ds = DRAM_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = { |
||||
.dram_sdqs0 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm0 = DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm1 = DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm2 = DRAM_DRIVE_STRENGTH, |
||||
.dram_dqm3 = DRAM_DRIVE_STRENGTH, |
||||
.dram_cas = DRAM_DRIVE_STRENGTH, |
||||
.dram_ras = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdclk_0 = DRAM_DRIVE_STRENGTH, |
||||
.dram_reset = DRAM_DRIVE_STRENGTH, |
||||
.dram_sdba2 = 0x00020000, |
||||
.dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH, |
||||
.dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = { |
||||
.grp_b0ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b1ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b2ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_b3ds = DRAM_DRIVE_STRENGTH, |
||||
.grp_addds = DRAM_DRIVE_STRENGTH, |
||||
.grp_ctlds = DRAM_DRIVE_STRENGTH, |
||||
.grp_ddrmode_ctl = DDR_ODT, |
||||
.grp_ddrpke = DDR_PKE, |
||||
.grp_ddrmode = DDR_ODT, |
||||
.grp_ddr_type = GRP_DDRTYPE, |
||||
}; |
||||
|
||||
static struct mx6_ddr_sysinfo const sysinfo = { |
||||
/* width of data bus:0=16,1=32,2=64 */ |
||||
#if CONFIG_DDRWIDTH == 32 |
||||
.dsize = 1, |
||||
#elif CONFIG_DDRWIDTH == 64 |
||||
.dsize = 2, |
||||
#else |
||||
#error missing CONFIG_DDRWIDTH |
||||
#endif |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, /* 32Gb per CS */ |
||||
|
||||
/* # of chip selects */ |
||||
.ncs = CONFIG_DDRCS, |
||||
.cs1_mirror = 0, |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.rtt_nom = CONFIG_RTT_NOM, |
||||
.rtt_wr = CONFIG_RTT_WR, |
||||
.ralat = CONFIG_RALAT, /* Read additional latency */ |
||||
.walat = CONFIG_WALAT, /* Write additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
#ifdef CONFIG_DDR3 |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
.sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */ |
||||
.pd_fast_exit = 0, /* immaterial for calibration */ |
||||
.ddr_type = DDR_TYPE_DDR3, |
||||
#else |
||||
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ |
||||
.sde_to_rst = 0, /* LPDDR2 does not need this field */ |
||||
.pd_fast_exit = 0, /* immaterial for calibration */ |
||||
.ddr_type = DDR_TYPE_LPDDR2, |
||||
#endif |
||||
.refsel = CONFIG_REFSEL, |
||||
.refr = CONFIG_REFR, |
||||
}; |
||||
|
||||
#ifdef CONFIG_MT41K512M16TNA |
||||
/* Micron MT41K512M16TNA-125 */ |
||||
static struct mx6_ddr3_cfg const ddrtype = { |
||||
.mem_speed = 1600, |
||||
.density = 8, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 15, |
||||
.coladdr = 10, |
||||
.pagesz = 1, |
||||
.trcd = 1375, |
||||
.trcmin = 5062, |
||||
.trasmin = 3750, |
||||
}; |
||||
#elif defined(CONFIG_MT41K128M16JT) |
||||
/* Micron MT41K128M16JT-125 */ |
||||
static struct mx6_ddr3_cfg const ddrtype = { |
||||
.mem_speed = 1600, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
#elif defined(CONFIG_H5TQ4G63AFR) |
||||
/* Hynix H5TQ4G63AFR */ |
||||
static struct mx6_ddr3_cfg const ddrtype = { |
||||
.mem_speed = 1600, |
||||
.density = 4, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 15, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
#elif defined CONFIG_H5TQ2G63DFR |
||||
/* Hynix H5TQ2G63DFR */ |
||||
static struct mx6_ddr3_cfg const ddrtype = { |
||||
.mem_speed = 1333, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1350, |
||||
.trcmin = 4950, |
||||
.trasmin = 3600, |
||||
}; |
||||
#elif defined(CONFIG_MT42L256M32D2LG) |
||||
/* Micron MT42L256M32D2LG */ |
||||
static struct mx6_lpddr2_cfg ddrtype = { |
||||
.mem_speed = 800, |
||||
.density = 4, |
||||
.width = 32, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.trcd_lp = 2000, |
||||
.trppb_lp = 2000, |
||||
.trpab_lp = 2250, |
||||
.trasmin = 4200, |
||||
}; |
||||
#elif defined(CONFIG_MT29PZZZ4D4BKESK) |
||||
/* Micron MT29PZZZ4D4BKESK */ |
||||
static struct mx6_lpddr2_cfg ddrtype = { |
||||
.mem_speed = 800, |
||||
.density = 4, |
||||
.width = 32, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.trcd_lp = 2000, |
||||
.trppb_lp = 2000, |
||||
.trpab_lp = 2250, |
||||
.trasmin = 4200, |
||||
}; |
||||
#else |
||||
#error please select DDR type using menuconfig |
||||
#endif |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
/* FIXME: these should probably be checked, especially
|
||||
* for i.MX6SL, UL, ULL |
||||
*/ |
||||
writel(0x00C03F3F, &ccm->CCGR0); |
||||
writel(0x0030FC03, &ccm->CCGR1); |
||||
writel(0x0FFFC000, &ccm->CCGR2); |
||||
writel(0x3FF00000, &ccm->CCGR3); |
||||
writel(0x00FFF300, &ccm->CCGR4); |
||||
writel(0x0F0000C3, &ccm->CCGR5); |
||||
writel(0x000003FF, &ccm->CCGR6); |
||||
} |
||||
|
||||
static void display_calibration(struct mx6_mmdc_calibration *calib) |
||||
{ |
||||
printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0); |
||||
printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1); |
||||
printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl); |
||||
printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl); |
||||
printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0); |
||||
printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1); |
||||
if (sysinfo.dsize == 2) { |
||||
printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0); |
||||
printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1); |
||||
printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl); |
||||
printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl); |
||||
printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0); |
||||
printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1); |
||||
} |
||||
#ifdef CONFIG_IMXIMAGE_OUTPUT |
||||
printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0); |
||||
printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1); |
||||
printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl); |
||||
printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl); |
||||
printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n", |
||||
calib->p0_mpwldectrl0); |
||||
printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n", |
||||
calib->p0_mpwldectrl1); |
||||
if (sysinfo.dsize == 2) { |
||||
printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n", |
||||
calib->p1_mpdgctrl0); |
||||
printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n", |
||||
calib->p1_mpdgctrl1); |
||||
printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n", |
||||
calib->p1_mprddlctl); |
||||
printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n", |
||||
calib->p1_mpwrdlctl); |
||||
printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n", |
||||
calib->p1_mpwldectrl0); |
||||
printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n", |
||||
calib->p1_mpwldectrl1); |
||||
} |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* called from C runtime startup code (arch/arm/lib/crt0.S:_main) |
||||
* - we have a stack and a place to store GD, both in SRAM |
||||
* - no variable global data is available |
||||
*/ |
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
int errs; |
||||
struct mx6_mmdc_calibration calibration = {0}; |
||||
|
||||
memset((void *)gd, 0, sizeof(struct global_data)); |
||||
|
||||
/* write leveling calibration defaults */ |
||||
calibration.p0_mpwrdlctl = 0x40404040; |
||||
calibration.p1_mpwrdlctl = 0x40404040; |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
ccgr_init(); |
||||
|
||||
SETUP_IOMUX_PADS(uart_pads); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
if (sysinfo.dsize != 1) { |
||||
if (is_cpu_type(MXC_CPU_MX6SX) || |
||||
is_cpu_type(MXC_CPU_MX6UL) || |
||||
is_cpu_type(MXC_CPU_MX6SL)) { |
||||
printf("cpu type 0x%x doesn't support 64-bit bus\n", |
||||
get_cpu_type()); |
||||
reset_cpu(0); |
||||
} |
||||
} |
||||
#ifdef CONFIG_MX6SL |
||||
mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs, |
||||
&mx6sl_grp_ioregs); |
||||
#else |
||||
if (is_cpu_type(MXC_CPU_MX6Q)) { |
||||
mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs, |
||||
&mx6dq_grp_ioregs); |
||||
} else { |
||||
mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs, |
||||
&mx6sdl_grp_ioregs); |
||||
} |
||||
#endif |
||||
mx6_dram_cfg(&sysinfo, &calibration, &ddrtype); |
||||
|
||||
errs = mmdc_do_write_level_calibration(&sysinfo); |
||||
if (errs) { |
||||
printf("error %d from write level calibration\n", errs); |
||||
} else { |
||||
errs = mmdc_do_dqs_calibration(&sysinfo); |
||||
if (errs) { |
||||
printf("error %d from write level calibration\n", errs); |
||||
} else { |
||||
printf("completed successfully\n"); |
||||
mmdc_read_calibration(&sysinfo, &calibration); |
||||
display_calibration(&calibration); |
||||
} |
||||
} |
||||
reset_cpu(0); |
||||
} |
||||
@ -0,0 +1,33 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_MX6_DDRCAL=y |
||||
CONFIG_TARGET_MX6MEMCAL=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL" |
||||
CONFIG_SPL=y |
||||
CONFIG_HUSH_PARSER=y |
||||
# CONFIG_MMC is not set |
||||
# CONFIG_CMD_BOOTD is not set |
||||
# CONFIG_CMD_BOOTM is not set |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_EXPORTENV is not set |
||||
# CONFIG_CMD_IMPORTENV is not set |
||||
# CONFIG_CMD_EDITENV is not set |
||||
# CONFIG_CMD_SAVEENV is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MEMINFO=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_CMD_NET is not set |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_REGEX=y |
||||
@ -0,0 +1,59 @@ |
||||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Boundary Devices Nitrogen6X |
||||
* and Freescale i.MX6Q Sabre Lite boards. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* SPL */ |
||||
|
||||
#include "mx6_common.h" |
||||
#include "imx6_spl.h" |
||||
|
||||
#undef CONFIG_FSL_ESDHC |
||||
#undef CONFIG_MMC |
||||
#undef CONFIG_SPL_MMC_SUPPORT |
||||
#undef CONFIG_GENERIC_MMC |
||||
#undef CONFIG_CMD_FUSE |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x20000000 |
||||
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#ifdef CONFIG_SERIAL_CONSOLE_UART1 |
||||
#if defined(CONFIG_MX6SL) |
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR |
||||
#else |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
#endif |
||||
#elif defined(CONFIG_SERIAL_CONSOLE_UART2) |
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
#else |
||||
#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) |
||||
#endif |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue