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@ -1770,7 +1770,7 @@ typedef struct ccsr_gur { |
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#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 |
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#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 |
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#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 |
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#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) |
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#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_PPC_B4420) |
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 |
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 |
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#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 |
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@ -2883,7 +2883,7 @@ struct ccsr_pman { |
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#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 |
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#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 |
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#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 |
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#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ |
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#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860)\ |
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&& !defined(CONFIG_PPC_B4420) |
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#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 |
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#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 |
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