Add SPL support for rk3399, default with of-platdata enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <debug_uart.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <led.h> |
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#include <malloc.h> |
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#include <ram.h> |
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#include <spl.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/periph.h> |
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#include <asm/arch/sdram.h> |
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#include <asm/arch/timer.h> |
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#include <dm/pinctrl.h> |
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#include <dm/root.h> |
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#include <dm/test.h> |
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#include <dm/util.h> |
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#include <power/regulator.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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u32 spl_boot_device(void) |
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{ |
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return BOOT_DEVICE_MMC1; |
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} |
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u32 spl_boot_mode(const u32 boot_device) |
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{ |
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return MMCSD_MODE_RAW; |
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} |
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#define TIMER_CHN10_BASE 0xff8680a0 |
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#define TIMER_END_COUNT_L 0x00 |
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#define TIMER_END_COUNT_H 0x04 |
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#define TIMER_INIT_COUNT_L 0x10 |
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#define TIMER_INIT_COUNT_H 0x14 |
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#define TIMER_CONTROL_REG 0x1c |
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#define TIMER_EN 0x1 |
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#define TIMER_FMODE (0 << 1) |
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#define TIMER_RMODE (1 << 1) |
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void secure_timer_init(void) |
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{ |
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); |
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); |
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); |
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); |
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writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); |
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} |
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#define GRF_EMMCCORE_CON11 0xff77f02c |
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void board_init_f(ulong dummy) |
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{ |
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struct udevice *pinctrl; |
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struct udevice *dev; |
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int ret; |
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/* Example code showing how to enable the debug UART on RK3288 */ |
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#include <asm/arch/grf_rk3399.h> |
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/* Enable early UART2 channel C on the RK3399 */ |
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#define GRF_BASE 0xff770000 |
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE; |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C3_SEL_MASK, |
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GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C4_SEL_MASK, |
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GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); |
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/* Set channel C as UART2 input */ |
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rk_clrsetreg(&grf->soc_con7, |
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GRF_UART_DBG_SEL_MASK, |
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GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); |
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#define EARLY_UART |
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#ifdef EARLY_UART |
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/*
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* Debug UART can be used from here if required: |
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* |
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* debug_uart_init(); |
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* printch('a'); |
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* printhex8(0x1234); |
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* printascii("string"); |
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*/ |
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debug_uart_init(); |
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printascii("U-Boot SPL board init"); |
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#endif |
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/* Emmc clock generator: disable the clock multipilier */ |
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rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); |
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ret = spl_init(); |
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if (ret) { |
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debug("spl_init() failed: %d\n", ret); |
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hang(); |
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} |
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secure_timer_init(); |
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); |
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if (ret) { |
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debug("Pinctrl init failed: %d\n", ret); |
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return; |
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} |
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ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
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if (ret) { |
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debug("DRAM init failed: %d\n", ret); |
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return; |
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} |
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} |
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void spl_board_init(void) |
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{ |
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struct udevice *pinctrl; |
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int ret; |
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); |
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if (ret) { |
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debug("%s: Cannot find pinctrl device\n", __func__); |
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goto err; |
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} |
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/* Enable debug UART */ |
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); |
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if (ret) { |
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debug("%s: Failed to set up console UART\n", __func__); |
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goto err; |
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} |
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preloader_console_init(); |
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#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM |
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back_to_bootrom(); |
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#endif |
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return; |
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err: |
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printf("spl_board_init: Error %d\n", ret); |
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/* No way to report error here */ |
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hang(); |
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} |
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#ifdef CONFIG_SPL_LOAD_FIT |
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int board_fit_config_name_match(const char *name) |
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{ |
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/* Just empty function now - can't decide what to choose */ |
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debug("%s: %s\n", __func__, name); |
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return 0; |
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} |
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#endif |
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