commit
307367eaff
@ -0,0 +1,162 @@ |
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/*
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* Copyright (C) 2015, Bachmann electronic GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <asm/arch/mx6-ddr.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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/* Configure MX6Q/DUAL mmdc DDR io registers */ |
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static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { |
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ |
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.dram_sdclk_0 = 0x00000028, |
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.dram_sdclk_1 = 0x00000028, |
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.dram_cas = 0x00000028, |
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.dram_ras = 0x00000028, |
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.dram_reset = 0x00000028, |
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/* SDCKE[0:1]: 100k pull-up */ |
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.dram_sdcke0 = 0x00003000, |
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.dram_sdcke1 = 0x00003000, |
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/* SDBA2: pull-up disabled */ |
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.dram_sdba2 = 0x00000000, |
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/* SDODT[0:1]: 100k pull-up, 48 ohm */ |
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.dram_sdodt0 = 0x00000028, |
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.dram_sdodt1 = 0x00000028, |
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/* SDQS[0:7]: Differential input, 48 ohm */ |
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.dram_sdqs0 = 0x00000028, |
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.dram_sdqs1 = 0x00000028, |
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.dram_sdqs2 = 0x00000028, |
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.dram_sdqs3 = 0x00000028, |
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.dram_sdqs4 = 0x00000028, |
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.dram_sdqs5 = 0x00000028, |
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.dram_sdqs6 = 0x00000028, |
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.dram_sdqs7 = 0x00000028, |
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/* DQM[0:7]: Differential input, 48 ohm */ |
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.dram_dqm0 = 0x00000028, |
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.dram_dqm1 = 0x00000028, |
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.dram_dqm2 = 0x00000028, |
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.dram_dqm3 = 0x00000028, |
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.dram_dqm4 = 0x00000028, |
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.dram_dqm5 = 0x00000028, |
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.dram_dqm6 = 0x00000028, |
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.dram_dqm7 = 0x00000028, |
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}; |
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/* Configure MX6Q/DUAL mmdc GRP io registers */ |
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static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = { |
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/* DDR3 */ |
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.grp_ddr_type = 0x000c0000, |
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.grp_ddrmode_ctl = 0x00020000, |
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/* Disable DDR pullups */ |
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.grp_ddrpke = 0x00000000, |
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/* ADDR[00:16], SDBA[0:1]: 48 ohm */ |
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.grp_addds = 0x00000028, |
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */ |
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.grp_ctlds = 0x00000028, |
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/* DATA[00:63]: Differential input, 48 ohm */ |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = 0x00000028, |
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.grp_b1ds = 0x00000028, |
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.grp_b2ds = 0x00000028, |
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.grp_b3ds = 0x00000028, |
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.grp_b4ds = 0x00000028, |
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.grp_b5ds = 0x00000028, |
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.grp_b6ds = 0x00000028, |
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.grp_b7ds = 0x00000028, |
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}; |
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static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { |
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/* Width of data bus: 0=16, 1=32, 2=64 */ |
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.dsize = 2, |
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/* config for full 4GB range so that get_mem_size() works */ |
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.cs_density = 32, /* 32Gb per CS */ |
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/* Single chip select */ |
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.ncs = 1, |
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.cs1_mirror = 0, /* war 0 */ |
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.rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */ |
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.rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */ |
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.walat = 1, /* Write additional latency */ |
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.ralat = 5, /* Read additional latency */ |
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.mif3_mode = 3, /* Command prediction working mode */ |
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.bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ |
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
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}; |
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/* MT41K128M16JT-125 */ |
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static struct mx6_ddr3_cfg micron_2gib_1600 = { |
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.mem_speed = 1600, |
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.density = 2, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 14, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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.SRT = 1, |
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}; |
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static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = { |
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/* write leveling calibration determine */ |
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.p0_mpwldectrl0 = 0x00260025, |
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.p0_mpwldectrl1 = 0x00270021, |
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.p1_mpwldectrl0 = 0x00180034, |
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.p1_mpwldectrl1 = 0x00180024, |
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/* Read DQS Gating calibration */ |
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.p0_mpdgctrl0 = 0x04380344, |
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.p0_mpdgctrl1 = 0x0330032C, |
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.p1_mpdgctrl0 = 0x0338033C, |
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.p1_mpdgctrl1 = 0x032C0300, |
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/* Read Calibration: DQS delay relative to DQ read access */ |
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.p0_mprddlctl = 0x3C2E3238, |
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.p1_mprddlctl = 0x3A2E303C, |
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/* Write Calibration: DQ/DM delay relative to DQS write access */ |
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.p0_mpwrdlctl = 0x36384036, |
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.p1_mpwrdlctl = 0x442E4438, |
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}; |
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static void ot1200_spl_dram_init(void) |
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{ |
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mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs); |
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mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib, |
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µn_2gib_1600); |
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} |
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/*
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* called from C runtime startup code (arch/arm/lib/crt0.S:_main) |
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* - we have a stack and a place to store GD, both in SRAM |
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* - no variable global data is available |
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*/ |
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void board_init_f(ulong dummy) |
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{ |
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/* setup AIPS and disable watchdog */ |
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arch_cpu_init(); |
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/* iomux and setup of i2c */ |
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board_early_init_f(); |
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/* setup GP timer */ |
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timer_init(); |
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/* UART clocks enabled and gd valid - init serial console */ |
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preloader_console_init(); |
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/* configure MMDC for SDRAM width/size and per-model calibration */ |
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ot1200_spl_dram_init(); |
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/* Clear the BSS. */ |
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memset(__bss_start, 0, __bss_end - __bss_start); |
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/* load/boot image from boot device */ |
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board_init_r(NULL, 0); |
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} |
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void reset_cpu(ulong addr) |
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{ |
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} |
@ -0,0 +1,37 @@ |
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if TARGET_PLATINUM_PICON |
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config SYS_CPU |
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default "armv7" |
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config SYS_VENDOR |
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default "barco" |
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config SYS_SOC |
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default "mx6" |
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config SYS_BOARD |
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default "platinum" |
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config SYS_CONFIG_NAME |
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default "platinum_picon" |
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endif |
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if TARGET_PLATINUM_TITANIUM |
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config SYS_CPU |
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default "armv7" |
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config SYS_VENDOR |
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default "barco" |
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config SYS_SOC |
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default "mx6" |
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config SYS_BOARD |
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default "platinum" |
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config SYS_CONFIG_NAME |
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default "platinum_titanium" |
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endif |
@ -0,0 +1,7 @@ |
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PLATINUM BOARD |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/barco/platinum/ |
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F: include/configs/platinum.h |
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F: configs/platinum_picon_defconfig |
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F: configs/platinum_titanium_defconfig |
@ -0,0 +1,14 @@ |
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#
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# Copyright (C) 2014, Barco (www.barco.com)
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := platinum.o
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obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o
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obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o
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ifneq ($(CONFIG_SPL_BUILD),) |
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obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o
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obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o
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endif |
@ -0,0 +1,217 @@ |
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/*
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* Copyright (C) 2014, Barco (www.barco.com) |
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* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <asm/imx-common/boot_mode.h> |
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#include "platinum.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
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}; |
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iomux_v3_cfg_t nfc_pads[] = { |
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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struct fsl_esdhc_cfg usdhc_cfg[] = { |
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{ USDHC3_BASE_ADDR }, |
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}; |
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void setup_gpmi_nand(void) |
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{ |
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
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/* config gpmi nand iomux */ |
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imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); |
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/* config gpmi and bch clock to 100 MHz */ |
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clrsetbits_le32(&mxc_ccm->cs2cdr, |
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, |
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); |
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/* enable gpmi and bch clock gating */ |
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setbits_le32(&mxc_ccm->CCGR4, |
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); |
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/* enable apbh clock gating */ |
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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return 0; |
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} |
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int board_ehci_hcd_init(int port) |
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{ |
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return 0; |
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} |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { |
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unsigned sd3_cd = IMX_GPIO_NR(7, 0); |
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gpio_direction_input(sd3_cd); |
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return !gpio_get_value(sd3_cd); |
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} |
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return 0; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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} |
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void board_init_gpio(void) |
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{ |
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platinum_init_gpio(); |
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} |
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void board_init_gpmi_nand(void) |
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{ |
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setup_gpmi_nand(); |
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} |
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void board_init_i2c(void) |
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{ |
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platinum_setup_i2c(); |
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} |
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void board_init_spi(void) |
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{ |
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platinum_setup_spi(); |
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} |
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void board_init_uart(void) |
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{ |
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platinum_setup_uart(); |
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} |
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void board_init_usb(void) |
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{ |
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platinum_init_usb(); |
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} |
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void board_init_finished(void) |
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{ |
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platinum_init_finished(); |
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} |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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return platinum_phy_config(phydev); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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return cpu_eth_init(bis); |
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} |
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int board_early_init_f(void) |
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{ |
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board_init_uart(); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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board_init_spi(); |
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board_init_i2c(); |
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board_init_gpmi_nand(); |
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board_init_gpio(); |
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board_init_usb(); |
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board_init_finished(); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: " CONFIG_PLATINUM_BOARD "\n"); |
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return 0; |
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} |
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static const struct boot_mode board_boot_modes[] = { |
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/* NAND */ |
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{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, |
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/* 4 bit bus width */ |
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{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, |
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{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, |
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{ NULL, 0 }, |
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}; |
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int misc_init_r(void) |
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{ |
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add_board_boot_modes(board_boot_modes); |
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return 0; |
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} |
@ -0,0 +1,89 @@ |
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/*
|
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* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _PLATINUM_H_ |
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#define _PLATINUM_H_ |
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|
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#include <miiphy.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/io.h> |
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|
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/* Defines */ |
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|
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#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS) |
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#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS) |
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#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
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PAD_CTL_HYS) |
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#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS) |
||||
#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
|
||||
PAD_CTL_HYS) |
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
||||
#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ |
||||
PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_SLOW) |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
|
||||
PAD_CTL_HYS) |
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
|
||||
PAD_CTL_HYS) |
||||
|
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
||||
#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) |
||||
|
||||
/* Prototypes */ |
||||
|
||||
int platinum_setup_enet(void); |
||||
int platinum_setup_i2c(void); |
||||
int platinum_setup_spi(void); |
||||
int platinum_setup_uart(void); |
||||
int platinum_phy_config(struct phy_device *phydev); |
||||
int platinum_init_gpio(void); |
||||
int platinum_init_usb(void); |
||||
int platinum_init_finished(void); |
||||
|
||||
static inline void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
writel(0x00C03F3F, &ccm->CCGR0); |
||||
writel(0x0030FC03, &ccm->CCGR1); |
||||
writel(0x0FFFC000, &ccm->CCGR2); |
||||
writel(0x3FF00000, &ccm->CCGR3); |
||||
writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ |
||||
writel(0x0F0000C3, &ccm->CCGR5); |
||||
writel(0x000003FF, &ccm->CCGR6); |
||||
} |
||||
|
||||
static inline void gpr_init(void) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
writel(0xF00000CF, &iomux->gpr[4]); |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
writel(0x007F007F, &iomux->gpr[6]); |
||||
writel(0x007F007F, &iomux->gpr[7]); |
||||
} |
||||
|
||||
#endif /* _PLATINUM_H_ */ |
@ -0,0 +1,244 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Barco (www.barco.com) |
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <i2c.h> |
||||
#include <miiphy.h> |
||||
|
||||
#include "platinum.h" |
||||
|
||||
#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) |
||||
#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) |
||||
#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) |
||||
|
||||
#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) |
||||
#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) |
||||
#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) |
||||
|
||||
#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) |
||||
#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) |
||||
#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) |
||||
|
||||
#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) |
||||
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = { |
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), |
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), |
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), |
||||
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const ecspi2_pads[] = { |
||||
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), |
||||
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), |
||||
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), |
||||
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads[] = { |
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
}; |
||||
|
||||
/* PHY nRESET */ |
||||
iomux_v3_cfg_t const phy_reset_pad = { |
||||
MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = { |
||||
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart4_pads[] = { |
||||
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart5_pads[] = { |
||||
MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const i2c0_mux_pads[] = { |
||||
MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const i2c2_mux_pads[] = { |
||||
MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
struct i2c_pads_info i2c_pad_info0 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, |
||||
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, |
||||
.gp = IMX_GPIO_NR(5, 27) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, |
||||
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, |
||||
.gp = IMX_GPIO_NR(5, 26) |
||||
} |
||||
}; |
||||
|
||||
struct i2c_pads_info i2c_pad_info2 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, |
||||
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, |
||||
.gp = IMX_GPIO_NR(1, 3) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, |
||||
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, |
||||
.gp = IMX_GPIO_NR(1, 6) |
||||
} |
||||
}; |
||||
|
||||
/*
|
||||
* This enet related pin-muxing and GPIO handling is done |
||||
* in SPL U-Boot. For early initialization. And to give the |
||||
* PHY some time to come out of reset before the U-Boot |
||||
* ethernet driver tries to access its registers via MDIO. |
||||
*/ |
||||
int platinum_setup_enet(void) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
unsigned phy_reset = IMX_GPIO_NR(1, 19); |
||||
|
||||
/* First configure PHY reset GPIO pin */ |
||||
imx_iomux_v3_setup_pad(phy_reset_pad); |
||||
|
||||
/* Reconfigure enet muxing while PHY is in reset */ |
||||
gpio_direction_output(phy_reset, 0); |
||||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
||||
mdelay(10); |
||||
gpio_set_value(phy_reset, 1); |
||||
udelay(100); |
||||
|
||||
/* set GPIO_16 as ENET_REF_CLK_OUT */ |
||||
setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); |
||||
|
||||
return enable_fec_anatop_clock(ENET_50MHZ); |
||||
} |
||||
|
||||
int platinum_setup_i2c(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, |
||||
ARRAY_SIZE(i2c0_mux_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, |
||||
ARRAY_SIZE(i2c2_mux_pads)); |
||||
|
||||
mdelay(10); |
||||
|
||||
/* Disable i2c mux 0 */ |
||||
gpio_direction_output(GPIO_I2C0_SEL0, 0); |
||||
gpio_direction_output(GPIO_I2C0_SEL1, 0); |
||||
gpio_direction_output(GPIO_I2C0_ENBN, 1); |
||||
|
||||
/* Disable i2c mux 1 */ |
||||
gpio_direction_output(GPIO_I2C2_SEL0, 0); |
||||
gpio_direction_output(GPIO_I2C2_SEL1, 0); |
||||
gpio_direction_output(GPIO_I2C2_ENBN, 1); |
||||
|
||||
udelay(10); |
||||
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); |
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
||||
|
||||
/* Disable all leds */ |
||||
i2c_set_bus_num(0); |
||||
i2c_reg_write(0x60, 0x05, 0x55); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_setup_spi(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_setup_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_phy_config(struct phy_device *phydev) |
||||
{ |
||||
/* Use generic infrastructure, no specific setup */ |
||||
if (phydev->drv->config) |
||||
phydev->drv->config(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_gpio(void) |
||||
{ |
||||
/* Reset FPGA's */ |
||||
gpio_direction_output(GPIO_IP_NCONFIG, 0); |
||||
gpio_direction_output(GPIO_HK_NCONFIG, 0); |
||||
gpio_direction_output(GPIO_LS_NCONFIG, 0); |
||||
udelay(3); |
||||
gpio_set_value(GPIO_IP_NCONFIG, 1); |
||||
gpio_set_value(GPIO_HK_NCONFIG, 1); |
||||
gpio_set_value(GPIO_LS_NCONFIG, 1); |
||||
|
||||
/* no dmd configuration yet */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_usb(void) |
||||
{ |
||||
/* Reset usb hub */ |
||||
gpio_direction_output(GPIO_USB_RESET, 0); |
||||
udelay(100); |
||||
gpio_set_value(GPIO_USB_RESET, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_finished(void) |
||||
{ |
||||
/* Enable led 0 */ |
||||
i2c_set_bus_num(0); |
||||
i2c_reg_write(0x60, 0x05, 0x54); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Barco (www.barco.com) |
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <miiphy.h> |
||||
#include <micrel.h> |
||||
|
||||
#include "platinum.h" |
||||
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = { |
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), |
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), |
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), |
||||
MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
/* non mounted spi nor flash for booting */ |
||||
MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const ecspi2_pads[] = { |
||||
MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), |
||||
MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), |
||||
MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), |
||||
MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = { |
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
/* pin 35 - 1 (PHY_AD2) on reset */ |
||||
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 32 - 1 - (MODE0) all */ |
||||
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 31 - 1 - (MODE1) all */ |
||||
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 28 - 1 - (MODE2) all */ |
||||
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 27 - 1 - (MODE3) all */ |
||||
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ |
||||
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
/* pin 42 PHY nRST */ |
||||
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads2[] = { |
||||
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = { |
||||
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart2_pads[] = { |
||||
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const uart4_pads[] = { |
||||
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
struct i2c_pads_info i2c_pad_info0 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, |
||||
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, |
||||
.gp = IMX_GPIO_NR(5, 27) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, |
||||
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, |
||||
.gp = IMX_GPIO_NR(5, 26) |
||||
} |
||||
}; |
||||
|
||||
struct i2c_pads_info i2c_pad_info2 = { |
||||
.scl = { |
||||
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, |
||||
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, |
||||
.gp = IMX_GPIO_NR(1, 3) |
||||
}, |
||||
.sda = { |
||||
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, |
||||
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, |
||||
.gp = IMX_GPIO_NR(7, 11) |
||||
} |
||||
}; |
||||
|
||||
/*
|
||||
* This enet related pin-muxing and GPIO handling is done |
||||
* in SPL U-Boot. For early initialization. And to give the |
||||
* PHY some time to come out of reset before the U-Boot |
||||
* ethernet driver tries to access its registers via MDIO. |
||||
*/ |
||||
int platinum_setup_enet(void) |
||||
{ |
||||
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 30), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 25), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 27), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 28), 1); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 29), 1); |
||||
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); |
||||
gpio_direction_output(IMX_GPIO_NR(6, 24), 1); |
||||
|
||||
/* Need delay 10ms according to KSZ9021 spec */ |
||||
mdelay(10); |
||||
gpio_set_value(IMX_GPIO_NR(3, 23), 1); |
||||
udelay(100); |
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_setup_i2c(void) |
||||
{ |
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); |
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_setup_spi(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_setup_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_phy_config(struct phy_device *phydev) |
||||
{ |
||||
/* min rx data delay */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, |
||||
0x0); |
||||
/* min tx data delay */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, |
||||
0x0); |
||||
/* max rx/tx clock delay, min rx/tx control */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, |
||||
0xf0f0); |
||||
if (phydev->drv->config) |
||||
phydev->drv->config(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_gpio(void) |
||||
{ |
||||
/* Default GPIO's */ |
||||
/* Toggle CONFIG_n to reset fpga on every boot */ |
||||
gpio_direction_output(IMX_GPIO_NR(5, 18), 0); |
||||
/* Need delay >=2uS */ |
||||
udelay(3); |
||||
gpio_set_value(IMX_GPIO_NR(5, 18), 1); |
||||
|
||||
/* Default pin 1,15 high - DLP_FLASH_WPZ */ |
||||
gpio_direction_output(IMX_GPIO_NR(1, 15), 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_usb(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int platinum_init_finished(void) |
||||
{ |
||||
return 0; |
||||
} |
@ -0,0 +1,182 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
||||
* |
||||
* Based on: gw_ventana_spl.c which is: |
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <spl.h> |
||||
|
||||
#include "platinum.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ |
||||
|
||||
/* Configure MX6Q/DUAL mmdc DDR io registers */ |
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
||||
.dram_sdclk_0 = 0x00020030, |
||||
.dram_sdclk_1 = 0x00020030, |
||||
.dram_cas = 0x00020030, |
||||
.dram_ras = 0x00020030, |
||||
.dram_reset = 0x00020030, |
||||
/* SDCKE[0:1]: 100k pull-up */ |
||||
.dram_sdcke0 = 0x00003000, |
||||
.dram_sdcke1 = 0x00003000, |
||||
/* SDBA2: pull-up disabled */ |
||||
.dram_sdba2 = 0x00000000, |
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
||||
.dram_sdodt0 = 0x00003030, |
||||
.dram_sdodt1 = 0x00003030, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.dram_sdqs0 = 0x00000030, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_sdqs2 = 0x00000030, |
||||
.dram_sdqs3 = 0x00000030, |
||||
.dram_sdqs4 = 0x00000030, |
||||
.dram_sdqs5 = 0x00000030, |
||||
.dram_sdqs6 = 0x00000030, |
||||
.dram_sdqs7 = 0x00000030, |
||||
/* DQM[0:7]: Differential input, 40 ohm */ |
||||
.dram_dqm0 = 0x00020030, |
||||
.dram_dqm1 = 0x00020030, |
||||
.dram_dqm2 = 0x00020030, |
||||
.dram_dqm3 = 0x00020030, |
||||
.dram_dqm4 = 0x00020030, |
||||
.dram_dqm5 = 0x00020030, |
||||
.dram_dqm6 = 0x00020030, |
||||
.dram_dqm7 = 0x00020030, |
||||
}; |
||||
|
||||
/* Configure MX6Q/DUAL mmdc GRP io registers */ |
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
||||
/* DDR3 */ |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
/* disable DDR pullups */ |
||||
.grp_ddrpke = 0x00000000, |
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
||||
.grp_addds = 0x00000030, |
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
||||
.grp_ctlds = 0x00000030, |
||||
/* DATA[00:63]: Differential input, 40 ohm */ |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_b2ds = 0x00000030, |
||||
.grp_b3ds = 0x00000030, |
||||
.grp_b4ds = 0x00000030, |
||||
.grp_b5ds = 0x00000030, |
||||
.grp_b6ds = 0x00000030, |
||||
.grp_b7ds = 0x00000030, |
||||
}; |
||||
|
||||
/* MT41K256M16HA-125 */ |
||||
static struct mx6_ddr3_cfg mt41k256m16ha_125 = { |
||||
.mem_speed = 1600, |
||||
.density = 4, /* 4Gbit */ |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 15, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
|
||||
/*
|
||||
* Values from running the Freescale DDR stress tool via USB |
||||
*/ |
||||
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { |
||||
/* write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x0044004E, |
||||
.p0_mpwldectrl1 = 0x001F0023, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x02480248, |
||||
.p0_mpdgctrl1 = 0x0210021C, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x42444444, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x36322C32, |
||||
}; |
||||
|
||||
static void spl_dram_init(int width) |
||||
{ |
||||
struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; |
||||
struct mx6_ddr_sysinfo sysinfo = { |
||||
/* width of data bus:0=16,1=32,2=64 */ |
||||
.dsize = width / 32, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, /* 32Gb per CS */ |
||||
/* single chip select */ |
||||
.ncs = 1, |
||||
.cs1_mirror = 1, |
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
||||
#ifdef RTT_NOM_120OHM |
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ |
||||
#else |
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
||||
#endif |
||||
.walat = 0, /* Write additional latency */ |
||||
.ralat = 5, /* Read additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
}; |
||||
|
||||
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); |
||||
} |
||||
|
||||
/*
|
||||
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main) |
||||
* - we have a stack and a place to store GD, both in SRAM |
||||
* - no variable global data is available |
||||
*/ |
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
/* Setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
ccgr_init(); |
||||
gpr_init(); |
||||
|
||||
/* UART iomux */ |
||||
board_early_init_f(); |
||||
|
||||
/* Setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* Init DDR with 32bit width */ |
||||
spl_dram_init(32); |
||||
|
||||
/* Clear the BSS */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/*
|
||||
* Setup enet related MUXing early to give the PHY |
||||
* some time to wake-up from reset |
||||
*/ |
||||
platinum_setup_enet(); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
@ -0,0 +1,185 @@ |
||||
/*
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
||||
* |
||||
* Based on: gw_ventana_spl.c which is: |
||||
* Copyright (C) 2014 Gateworks Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-ddr.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/mxc_i2c.h> |
||||
#include <spl.h> |
||||
|
||||
#include "platinum.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ |
||||
|
||||
/* Configure MX6Q/DUAL mmdc DDR io registers */ |
||||
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ |
||||
.dram_sdclk_0 = 0x00020030, |
||||
.dram_sdclk_1 = 0x00020030, |
||||
.dram_cas = 0x00020030, |
||||
.dram_ras = 0x00020030, |
||||
.dram_reset = 0x00020030, |
||||
/* SDCKE[0:1]: 100k pull-up */ |
||||
.dram_sdcke0 = 0x00003000, |
||||
.dram_sdcke1 = 0x00003000, |
||||
/* SDBA2: pull-up disabled */ |
||||
.dram_sdba2 = 0x00000000, |
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */ |
||||
.dram_sdodt0 = 0x00003030, |
||||
.dram_sdodt1 = 0x00003030, |
||||
/* SDQS[0:7]: Differential input, 40 ohm */ |
||||
.dram_sdqs0 = 0x00000030, |
||||
.dram_sdqs1 = 0x00000030, |
||||
.dram_sdqs2 = 0x00000030, |
||||
.dram_sdqs3 = 0x00000030, |
||||
.dram_sdqs4 = 0x00000030, |
||||
.dram_sdqs5 = 0x00000030, |
||||
.dram_sdqs6 = 0x00000030, |
||||
.dram_sdqs7 = 0x00000030, |
||||
/* DQM[0:7]: Differential input, 40 ohm */ |
||||
.dram_dqm0 = 0x00020030, |
||||
.dram_dqm1 = 0x00020030, |
||||
.dram_dqm2 = 0x00020030, |
||||
.dram_dqm3 = 0x00020030, |
||||
.dram_dqm4 = 0x00020030, |
||||
.dram_dqm5 = 0x00020030, |
||||
.dram_dqm6 = 0x00020030, |
||||
.dram_dqm7 = 0x00020030, |
||||
}; |
||||
|
||||
/* Configure MX6Q/DUAL mmdc GRP io registers */ |
||||
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
||||
/* DDR3 */ |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
/* disable DDR pullups */ |
||||
.grp_ddrpke = 0x00000000, |
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */ |
||||
.grp_addds = 0x00000030, |
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ |
||||
.grp_ctlds = 0x00000030, |
||||
/* DATA[00:63]: Differential input, 40 ohm */ |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = 0x00000030, |
||||
.grp_b1ds = 0x00000030, |
||||
.grp_b2ds = 0x00000030, |
||||
.grp_b3ds = 0x00000030, |
||||
.grp_b4ds = 0x00000030, |
||||
.grp_b5ds = 0x00000030, |
||||
.grp_b6ds = 0x00000030, |
||||
.grp_b7ds = 0x00000030, |
||||
}; |
||||
|
||||
/* MT41J128M16JT-125 */ |
||||
static struct mx6_ddr3_cfg mt41j128m16jt_125 = { |
||||
.mem_speed = 1600, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { |
||||
/* Write leveling calibration determine */ |
||||
.p0_mpwldectrl0 = 0x001f001f, |
||||
.p0_mpwldectrl1 = 0x001f001f, |
||||
.p1_mpwldectrl0 = 0x00440044, |
||||
.p1_mpwldectrl1 = 0x00440044, |
||||
/* Read DQS Gating calibration */ |
||||
.p0_mpdgctrl0 = 0x434b0350, |
||||
.p0_mpdgctrl1 = 0x034c0359, |
||||
.p1_mpdgctrl0 = 0x434b0350, |
||||
.p1_mpdgctrl1 = 0x03650348, |
||||
/* Read Calibration: DQS delay relative to DQ read access */ |
||||
.p0_mprddlctl = 0x4436383b, |
||||
.p1_mprddlctl = 0x39393341, |
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */ |
||||
.p0_mpwrdlctl = 0x35373933, |
||||
.p1_mpwrdlctl = 0x48254a36, |
||||
}; |
||||
|
||||
static void spl_dram_init(int width) |
||||
{ |
||||
struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; |
||||
struct mx6_ddr_sysinfo sysinfo = { |
||||
/* width of data bus:0=16,1=32,2=64 */ |
||||
.dsize = width / 32, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, /* 32Gb per CS */ |
||||
/* single chip select */ |
||||
.ncs = 1, |
||||
.cs1_mirror = 1, |
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
||||
#ifdef RTT_NOM_120OHM |
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ |
||||
#else |
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
||||
#endif |
||||
.walat = 0, /* Write additional latency */ |
||||
.ralat = 5, /* Read additional latency */ |
||||
.mif3_mode = 3, /* Command prediction working mode */ |
||||
.bi_on = 1, /* Bank interleaving enabled */ |
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
||||
}; |
||||
|
||||
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); |
||||
mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); |
||||
} |
||||
|
||||
/*
|
||||
* Called from C runtime startup code (arch/arm/lib/crt0.S:_main) |
||||
* - we have a stack and a place to store GD, both in SRAM |
||||
* - no variable global data is available |
||||
*/ |
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
/* Setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
ccgr_init(); |
||||
gpr_init(); |
||||
|
||||
/* UART iomux */ |
||||
board_early_init_f(); |
||||
|
||||
/* Setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* Init DDR with 32bit width */ |
||||
spl_dram_init(32); |
||||
|
||||
/* Clear the BSS */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/*
|
||||
* Setup enet related MUXing early to give the PHY |
||||
* some time to wake-up from reset |
||||
*/ |
||||
platinum_setup_enet(); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
@ -1,72 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <nand.h> |
||||
#include <bmp_layout.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) |
||||
{ |
||||
struct bmp_header *bmp_hdr; |
||||
int res; |
||||
size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); |
||||
|
||||
if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
res = nand_read_skip_bad(&nand_info[nand_curr_device], |
||||
nand_offset, &bmp_header_size, |
||||
NULL, nand_info[nand_curr_device].size, |
||||
(u_char *)bmp_load_addr); |
||||
if (res < 0) |
||||
return res; |
||||
|
||||
bmp_hdr = (struct bmp_header *)bmp_load_addr; |
||||
bmp_size = le32_to_cpu(bmp_hdr->file_size); |
||||
|
||||
if (bmp_load_addr + bmp_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
return nand_read_skip_bad(&nand_info[nand_curr_device], |
||||
nand_offset, &bmp_size, |
||||
NULL, nand_info[nand_curr_device].size, |
||||
(u_char *)bmp_load_addr); |
||||
|
||||
splash_address_too_high: |
||||
printf("Error: splashimage address too high. Data overwrites U-Boot " |
||||
"and/or placed beyond DRAM boundaries.\n"); |
||||
|
||||
return -1; |
||||
} |
||||
#else |
||||
static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) |
||||
{ |
||||
return -1; |
||||
} |
||||
#endif /* CONFIG_CMD_NAND */ |
||||
|
||||
int cl_splash_screen_prepare(int nand_offset) |
||||
{ |
||||
char *env_splashimage_value; |
||||
u32 bmp_load_addr; |
||||
|
||||
env_splashimage_value = getenv("splashimage"); |
||||
if (env_splashimage_value == NULL) |
||||
return -1; |
||||
|
||||
bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); |
||||
if (bmp_load_addr == 0) { |
||||
printf("Error: bad splashimage address specified\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return splash_load_from_nand(bmp_load_addr, nand_offset); |
||||
} |
@ -0,0 +1,176 @@ |
||||
/*
|
||||
* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Authors: Igor Grinberg <grinberg@compulab.co.il> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <nand.h> |
||||
#include <errno.h> |
||||
#include <splash.h> |
||||
#include <spi_flash.h> |
||||
#include <spi.h> |
||||
#include <bmp_layout.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_SPI_FLASH |
||||
static struct spi_flash *sf; |
||||
static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) |
||||
{ |
||||
if (!sf) { |
||||
sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, |
||||
CONFIG_SF_DEFAULT_CS, |
||||
CONFIG_SF_DEFAULT_SPEED, |
||||
CONFIG_SF_DEFAULT_MODE); |
||||
if (!sf) |
||||
return -ENODEV; |
||||
} |
||||
|
||||
return spi_flash_read(sf, offset, read_size, (void *)bmp_load_addr); |
||||
} |
||||
#else |
||||
static int splash_sf_read(u32 bmp_load_addr, int offset, size_t read_size) |
||||
{ |
||||
debug("%s: sf support not available\n", __func__); |
||||
return -ENOSYS; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) |
||||
{ |
||||
return nand_read_skip_bad(&nand_info[nand_curr_device], offset, |
||||
&read_size, NULL, |
||||
nand_info[nand_curr_device].size, |
||||
(u_char *)bmp_load_addr); |
||||
} |
||||
#else |
||||
static int splash_nand_read(u32 bmp_load_addr, int offset, size_t read_size) |
||||
{ |
||||
debug("%s: nand support not available\n", __func__); |
||||
return -ENOSYS; |
||||
} |
||||
#endif |
||||
|
||||
static int splash_storage_read(struct splash_location *location, |
||||
u32 bmp_load_addr, size_t read_size) |
||||
{ |
||||
u32 offset; |
||||
|
||||
if (!location) |
||||
return -EINVAL; |
||||
|
||||
offset = location->offset; |
||||
switch (location->storage) { |
||||
case SPLASH_STORAGE_NAND: |
||||
return splash_nand_read(bmp_load_addr, offset, read_size); |
||||
case SPLASH_STORAGE_SF: |
||||
return splash_sf_read(bmp_load_addr, offset, read_size); |
||||
default: |
||||
printf("Unknown splash location\n"); |
||||
} |
||||
|
||||
return -EINVAL; |
||||
} |
||||
|
||||
static int splash_load_raw(struct splash_location *location, u32 bmp_load_addr) |
||||
{ |
||||
struct bmp_header *bmp_hdr; |
||||
int res; |
||||
size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); |
||||
|
||||
if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
res = splash_storage_read(location, bmp_load_addr, bmp_header_size); |
||||
if (res < 0) |
||||
return res; |
||||
|
||||
bmp_hdr = (struct bmp_header *)bmp_load_addr; |
||||
bmp_size = le32_to_cpu(bmp_hdr->file_size); |
||||
|
||||
if (bmp_load_addr + bmp_size >= gd->start_addr_sp) |
||||
goto splash_address_too_high; |
||||
|
||||
return splash_storage_read(location, bmp_load_addr, bmp_size); |
||||
|
||||
splash_address_too_high: |
||||
printf("Error: splashimage address too high. Data overwrites U-Boot and/or placed beyond DRAM boundaries.\n"); |
||||
|
||||
return -EFAULT; |
||||
} |
||||
|
||||
/**
|
||||
* select_splash_location - return the splash location based on board support |
||||
* and env variable "splashsource". |
||||
* |
||||
* @locations: An array of supported splash locations. |
||||
* @size: Size of splash_locations array. |
||||
* |
||||
* @return: If a null set of splash locations is given, or |
||||
* splashsource env variable is set to unsupported value |
||||
* return NULL. |
||||
* If splashsource env variable is not defined |
||||
* return the first entry in splash_locations as default. |
||||
* If splashsource env variable contains a supported value |
||||
* return the location selected by splashsource. |
||||
*/ |
||||
static struct splash_location *select_splash_location( |
||||
struct splash_location *locations, uint size) |
||||
{ |
||||
int i; |
||||
char *env_splashsource; |
||||
|
||||
if (!locations || size == 0) |
||||
return NULL; |
||||
|
||||
env_splashsource = getenv("splashsource"); |
||||
if (env_splashsource == NULL) |
||||
return &locations[0]; |
||||
|
||||
for (i = 0; i < size; i++) { |
||||
if (!strcmp(locations[i].name, env_splashsource)) |
||||
return &locations[i]; |
||||
} |
||||
|
||||
printf("splashsource env variable set to unsupported value\n"); |
||||
return NULL; |
||||
} |
||||
|
||||
/**
|
||||
* splash_source_load - load splash image from a supported location. |
||||
* |
||||
* Select a splash image location based on the value of splashsource environment |
||||
* variable and the board supported splash source locations, and load a |
||||
* splashimage to the address pointed to by splashimage environment variable. |
||||
* |
||||
* @locations: An array of supported splash locations. |
||||
* @size: Size of splash_locations array. |
||||
* |
||||
* @return: 0 on success, negative value on failure. |
||||
*/ |
||||
int splash_source_load(struct splash_location *locations, uint size) |
||||
{ |
||||
struct splash_location *splash_location; |
||||
char *env_splashimage_value; |
||||
u32 bmp_load_addr; |
||||
|
||||
env_splashimage_value = getenv("splashimage"); |
||||
if (env_splashimage_value == NULL) |
||||
return -ENOENT; |
||||
|
||||
bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); |
||||
if (bmp_load_addr == 0) { |
||||
printf("Error: bad splashimage address specified\n"); |
||||
return -EFAULT; |
||||
} |
||||
|
||||
splash_location = select_splash_location(locations, size); |
||||
if (!splash_location) |
||||
return -EINVAL; |
||||
|
||||
return splash_load_raw(splash_location, bmp_load_addr); |
||||
} |
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_MX6SXSABRESD=y |
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_OT1200=y |
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_PLATINUM_PICON=y |
@ -0,0 +1,4 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TARGET_PLATINUM_TITANIUM=y |
@ -0,0 +1,319 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Barco (www.barco.com) |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PLATINUM_CONFIG_H__ |
||||
#define __PLATINUM_CONFIG_H__ |
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD |
||||
|
||||
/* SPL */ |
||||
#define CONFIG_SPL_NAND_SUPPORT |
||||
#define CONFIG_SPL_MMC_SUPPORT |
||||
|
||||
/* Location in NAND to read U-Boot from */ |
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) |
||||
|
||||
#include "imx6_spl.h" /* common IMX6 SPL configuration */ |
||||
#include "mx6_common.h" |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
/*
|
||||
* Console configuration |
||||
*/ |
||||
|
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_BMODE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_FUSE |
||||
#define CONFIG_CMD_GPIO |
||||
#define CONFIG_CMD_I2C |
||||
#undef CONFIG_CMD_IMLS |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_TIME |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
#define CONFIG_CMD_USB |
||||
|
||||
/*
|
||||
* Hardware configuration |
||||
*/ |
||||
|
||||
/* GPIO config */ |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
/* UART config */ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_CONS_INDEX 1 |
||||
|
||||
/* I2C config */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* MMC config */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* Ethernet config */ |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_MII |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
|
||||
#define CONFIG_PHYLIB |
||||
|
||||
/* USB config */ |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_MX6 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MXC_USB_PORT 1 |
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
||||
#define CONFIG_MXC_USB_FLAGS 0 |
||||
|
||||
/* Memory config */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
#ifndef PHYS_SDRAM_SIZE |
||||
#define PHYS_SDRAM_SIZE (1024 << 20) |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#ifdef CONFIG_CMD_NAND |
||||
|
||||
/* NAND config */ |
||||
#define CONFIG_NAND_MXS |
||||
#ifndef CONFIG_SYS_NAND_MAX_CHIPS |
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 2 |
||||
#endif |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x40000000 |
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION |
||||
|
||||
/* DMA config, needed for GPMI/MXS NAND support */ |
||||
#define CONFIG_APBH_DMA |
||||
#define CONFIG_APBH_DMA_BURST |
||||
#define CONFIG_APBH_DMA_BURST8 |
||||
|
||||
/* Fuse support */ |
||||
#define CONFIG_MXC_OCOTP |
||||
|
||||
/* Environment in NAND */ |
||||
#define CONFIG_ENV_IS_IN_NAND |
||||
#define CONFIG_ENV_OFFSET (16 << 20) |
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10) |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
#else /* CONFIG_CMD_NAND */ |
||||
|
||||
/* Environment in MMC */ |
||||
#define CONFIG_ENV_SIZE (8 << 10) |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
|
||||
#endif /* CONFIG_CMD_NAND */ |
||||
|
||||
/*
|
||||
* U-Boot configuration |
||||
*/ |
||||
|
||||
/* Console boot messages */ |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/* Tag config */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* Board startup config */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* Device tree support */ |
||||
#define CONFIG_OF_LIBFDT |
||||
|
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ |
||||
PHYS_SDRAM_SIZE - (12 << 20)) |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTCOMMAND "run bootubi_scr" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_PREBOOT |
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* MTD/UBI/UBIFS config */ |
||||
#define CONFIG_LZO |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_RBTREE |
||||
|
||||
#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) |
||||
#define MTDIDS_DEFAULT "nand0=gpmi-nand" |
||||
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ |
||||
"512k(env1),512k(env2),-(ubi)" |
||||
#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) |
||||
#define MTDIDS_DEFAULT "nand0=gpmi-nand" |
||||
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:14M(spl),2M(uboot)," \ |
||||
"512k(env1),512k(env2),495M(ubi0)," \
|
||||
"14M(res0),2M(res1)," \
|
||||
"512k(res2),512k(res3),-(ubi1)" |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment configuration |
||||
*/ |
||||
|
||||
#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) |
||||
#define CONFIG_COMMON_ENV_UBI \ |
||||
"setubipartition=env set ubipartition ubi\0" \
|
||||
"setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" |
||||
#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) |
||||
#define CONFIG_COMMON_ENV_UBI \ |
||||
"setubipartition=env set ubipartition ubi$boot_vol\0" \
|
||||
"setubirfs=env set ubirfs ubi0:rootfs\0" |
||||
#endif |
||||
|
||||
#define CONFIG_COMMON_ENV_MISC \ |
||||
"user=user\0" \
|
||||
"project="CONFIG_PLATINUM_PROJECT"\0" \
|
||||
"uimage=uImage\0" \
|
||||
"dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \
|
||||
"serverip=serverip\0" \
|
||||
"memaddrlinux=0x10800000\0" \
|
||||
"memaddrsrc=0x11000000\0" \
|
||||
"memaddrdtb=0x12000000\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"boot_scr=boot.uboot\0" \
|
||||
"boot_vol=0\0" \
|
||||
"mtdids="MTDIDS_DEFAULT"\0" \
|
||||
"mtdparts="MTDPARTS_DEFAULT"\0" \
|
||||
"mmcfs=ext2\0" \
|
||||
"mmcrootpart=1\0" \
|
||||
\
|
||||
"setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \
|
||||
"settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \
|
||||
"settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \
|
||||
"setubifilelinux=env set ubifilelinux boot/$uimage\0" \
|
||||
"setubipfiledtb=env set ubifiledtb boot/$dtb\0" \
|
||||
"setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \
|
||||
"setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \
|
||||
"setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \
|
||||
\
|
||||
"loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \
|
||||
"loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \
|
||||
"loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \
|
||||
"loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \
|
||||
"loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \
|
||||
"$mmcfilelinux\0" \
|
||||
"loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \
|
||||
"$mmcfiledtb\0" \
|
||||
\
|
||||
"ubipart=ubi part $ubipartition\0" \
|
||||
"ubimount=ubifsmount $ubirfs\0" \
|
||||
\
|
||||
"setbootargscommon=env set bootargs $bootargs " \
|
||||
"console=$console,$baudrate enable_wait_mode=off\0" \
|
||||
"setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \
|
||||
"setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \
|
||||
"setbootargsubirfs=env set bootargs $bootargs " \
|
||||
"ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \
|
||||
"setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \
|
||||
"nfsroot=$serverip:$nfspath,v3,tcp\0" \
|
||||
"setbootargsmmcrfs=env set bootargs $bootargs " \
|
||||
"root=$mmcrootdev rootwait rw\0" \
|
||||
\
|
||||
"bootnet=run settftpfilelinux settftpfiledtb setnfspath " \
|
||||
"setbootargscommon setbootargsmtd setbootargsdhcp " \
|
||||
"setbootargsnfsrfs;" \
|
||||
"run loadtftpkernel loadtftpdtb;" \
|
||||
"bootm $memaddrlinux - $memaddrdtb\0" \
|
||||
"bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \
|
||||
"run setubipartition setubirfs;" \
|
||||
"run setbootargscommon setbootargsmtd " \
|
||||
"setbootargsubirfs;" \
|
||||
"run loadtftpkernel loadtftpdtb;" \
|
||||
"bootm $memaddrlinux - $memaddrdtb\0" \
|
||||
"bootubi=run setubipartition setubirfs setubifilelinux " \
|
||||
"setubipfiledtb;" \
|
||||
"run setbootargscommon setbootargsmtd " \
|
||||
"setbootargsubirfs;" \
|
||||
"run ubipart ubimount loadubikernel loadubidtb;" \
|
||||
"bootm $memaddrlinux - $memaddrdtb\0" \
|
||||
"bootubi_scr=run setubipartition setubirfs;" \
|
||||
"run ubipart ubimount;" \
|
||||
"if ubifsload ${memaddrsrc} boot/${boot_scr}; " \
|
||||
"then source ${memaddrsrc}; else run bootubi; fi\0" \
|
||||
"bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \
|
||||
"setbootargscommon setbootargsmmcrfs;" \
|
||||
"run loadmmckernel loadmmcdtb;" \
|
||||
"bootm $memaddrlinux - $memaddrdtb\0" \
|
||||
\
|
||||
"bootcmd="CONFIG_BOOTCOMMAND"\0" |
||||
|
||||
#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ |
||||
CONFIG_COMMON_ENV_UBI |
||||
#endif /* __PLATINUM_CONFIG_H__ */ |
@ -0,0 +1,31 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Barco (www.barco.com) |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PLATINUM_PICON_CONFIG_H__ |
||||
#define __PLATINUM_PICON_CONFIG_H__ |
||||
|
||||
#define CONFIG_PLATINUM_PICON |
||||
#define CONFIG_PLATINUM_BOARD "Barco Picon" |
||||
#define CONFIG_PLATINUM_PROJECT "picon" |
||||
#define CONFIG_PLATINUM_CPU "imx6dl" |
||||
|
||||
#define CONFIG_MX6 |
||||
|
||||
#include <configs/platinum.h> |
||||
|
||||
#define CONFIG_FEC_XCV_TYPE RMII |
||||
#define CONFIG_FEC_MXC_PHYADDR 0 |
||||
|
||||
#define CONFIG_HOSTNAME picon |
||||
|
||||
#define CONFIG_SYS_PROMPT "picon > " |
||||
|
||||
#define CONFIG_PLATFORM_ENV_SETTINGS "\0" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ |
||||
CONFIG_PLATFORM_ENV_SETTINGS |
||||
|
||||
#endif /* __PLATINUM_PICON_CONFIG_H__ */ |
@ -0,0 +1,38 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Barco (www.barco.com) |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __PLATINUM_TITANIUM_CONFIG_H__ |
||||
#define __PLATINUM_TITANIUM_CONFIG_H__ |
||||
|
||||
#define CONFIG_PLATINUM_TITANIUM |
||||
#define CONFIG_PLATINUM_BOARD "Barco Titanium" |
||||
#define CONFIG_PLATINUM_PROJECT "titanium" |
||||
#define CONFIG_PLATINUM_CPU "imx6q" |
||||
|
||||
#define CONFIG_MX6 |
||||
|
||||
#define PHYS_SDRAM_SIZE (512 << 20) |
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
||||
|
||||
#include <configs/platinum.h> |
||||
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_FEC_MXC_PHYADDR 4 |
||||
|
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
#define CONFIG_PHY_RESET_DELAY 1000 |
||||
|
||||
#define CONFIG_HOSTNAME titanium |
||||
|
||||
#define CONFIG_SYS_PROMPT "titanium > " |
||||
|
||||
#define CONFIG_PLATFORM_ENV_SETTINGS "\0" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ |
||||
CONFIG_PLATFORM_ENV_SETTINGS |
||||
|
||||
#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ |
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