roy zang
18 years ago
committed by
Zang Tiefei
commit
30bddf2c46
@ -1,112 +0,0 @@ |
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/* |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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|
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/* General */ |
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#define TLB_VALID 0x00000200 |
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|
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/* Supported page sizes */ |
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|
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#define SZ_1K 0x00000000 |
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#define SZ_4K 0x00000010 |
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#define SZ_16K 0x00000020 |
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#define SZ_64K 0x00000030 |
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#define SZ_256K 0x00000040 |
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#define SZ_1M 0x00000050 |
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#define SZ_8M 0x00000060 |
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#define SZ_16M 0x00000070 |
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#define SZ_256M 0x00000090 |
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|
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/* Storage attributes */ |
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#define SA_W 0x00000800 /* Write-through */ |
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#define SA_I 0x00000400 /* Caching inhibited */ |
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#define SA_M 0x00000200 /* Memory coherence */ |
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#define SA_G 0x00000100 /* Guarded */ |
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#define SA_E 0x00000080 /* Endian */ |
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|
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/* Access control */ |
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#define AC_X 0x00000024 /* Execute */ |
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#define AC_W 0x00000012 /* Write */ |
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#define AC_R 0x00000009 /* Read */ |
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|
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/* Some handy macros */ |
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|
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#define EPN(e) ((e) & 0xfffffc00) |
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
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#define TLB2(a) ( (a)&0x00000fbf ) |
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|
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#define tlbtab_start\ |
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mflr r1 ;\
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bl 0f ;
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|
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#define tlbtab_end\ |
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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|
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#define tlbentry(epn,sz,rpn,erpn,attr)\ |
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
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|
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|
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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|
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.section .bootpg,"ax" |
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.globl tlbtab
|
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|
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tlbtab: |
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tlbtab_start |
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|
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/* |
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
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* speed up boot process. It is patched after relocation to enable SA_I |
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*/ |
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tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) |
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|
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
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tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) |
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|
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tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
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tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) |
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|
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/* PCI */ |
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tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) |
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tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) |
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|
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/* USB 2.0 Device */ |
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tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) |
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tlbtab_end |
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@ -1,549 +0,0 @@ |
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/*
|
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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#include <spd_sdram.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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|
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int board_early_init_f(void) |
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{ |
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register uint reg; |
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|
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects |
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*-------------------------------------------------------------------*/ |
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mtdcr(ebccfga, xbcfg); |
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reg = mfdcr(ebccfgd); |
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ |
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|
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/*--------------------------------------------------------------------
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* Setup the GPIO pins |
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*-------------------------------------------------------------------*/ |
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/*CPLD cs */ |
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/*setup Address lines for flash size 64Meg. */ |
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); |
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); |
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); |
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|
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/*setup emac */ |
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); |
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); |
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); |
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); |
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); |
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|
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/*UART1 */ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); |
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); |
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); |
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|
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/* external interrupts IRQ0...3 */ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); |
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out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); |
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); |
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|
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#if 0 /* test-only */
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/*setup USB 2.0 */ |
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); |
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); |
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); |
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); |
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); |
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#endif |
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|
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc. |
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*-------------------------------------------------------------------*/ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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mtdcr(uic0er, 0x00000000); /* disable all */ |
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ |
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ |
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ |
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(uic0sr, 0xffffffff); /* clear all */ |
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|
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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mtdcr(uic1er, 0x00000000); /* disable all */ |
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mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ |
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ |
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
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mtdcr(uic1sr, 0xffffffff); /* clear all */ |
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|
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/*--------------------------------------------------------------------
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* Setup other serial configuration |
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*-------------------------------------------------------------------*/ |
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mfsdr(sdr_pci0, reg); |
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ |
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mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ |
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ |
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|
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/*clear tmrclk divisor */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; |
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|
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/*enable ethernet */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; |
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|
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#if 0 /* test-only */
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/*enable usb 1.1 fs device and remove usb 2.0 reset */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; |
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#endif |
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|
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/*get rid of flash write protect */ |
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; |
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return 0; |
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} |
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|
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int misc_init_r (void) |
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{ |
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uint pbcr; |
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int size_val = 0; |
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|
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/* Re-do sizing to get full correct info */ |
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mtdcr(ebccfga, pb0cr); |
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pbcr = mfdcr(ebccfgd); |
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switch (gd->bd->bi_flashsize) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
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case 4 << 20: |
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size_val = 2; |
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break; |
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case 8 << 20: |
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size_val = 3; |
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break; |
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case 16 << 20: |
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size_val = 4; |
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break; |
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case 32 << 20: |
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size_val = 5; |
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break; |
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case 64 << 20: |
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size_val = 6; |
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break; |
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case 128 << 20: |
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size_val = 7; |
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break; |
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} |
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
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mtdcr(ebccfga, pb0cr); |
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mtdcr(ebccfgd, pbcr); |
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|
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/* adjust flash start and offset */ |
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
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gd->bd->bi_flashoffset = 0; |
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|
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, |
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-CFG_MONITOR_LEN, |
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0xffffffff, |
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&flash_info[0]); |
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return 0; |
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} |
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|
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int checkboard(void) |
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{ |
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char *s = getenv("serial#"); |
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u8 rev; |
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u8 val; |
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printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); |
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rev = *(u8 *)(CFG_CPLD + 0); |
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val = *(u8 *)(CFG_CPLD + 5) & 0x01; |
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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putc('\n'); |
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return (0); |
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} |
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|
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/*************************************************************************
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* sdram_init -- doesn't use serial presence detect. |
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* |
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* Assumes: 256 MB, ECC, non-registered |
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* PLB @ 133 MHz |
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* |
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************************************************************************/ |
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#define NUM_TRIES 64 |
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#define NUM_READS 10 |
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|
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void sdram_tr1_set(int ram_address, int* tr1_value) |
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{ |
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int i; |
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int j, k; |
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volatile unsigned int* ram_pointer = (unsigned int*)ram_address; |
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int first_good = -1, last_bad = 0x1ff; |
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|
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unsigned long test[NUM_TRIES] = { |
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, |
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; |
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|
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/* go through all possible SDRAM0_TR1[RDCT] values */ |
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for (i=0; i<=0x1ff; i++) { |
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/* set the current value for TR1 */ |
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mtsdram(mem_tr1, (0x80800800 | i)); |
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|
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/* write values */ |
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for (j=0; j<NUM_TRIES; j++) { |
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ram_pointer[j] = test[j]; |
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|
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/* clear any cache at ram location */ |
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); |
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} |
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|
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/* read values back */ |
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for (j=0; j<NUM_TRIES; j++) { |
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for (k=0; k<NUM_READS; k++) { |
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/* clear any cache at ram location */ |
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); |
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|
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if (ram_pointer[j] != test[j]) |
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break; |
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} |
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|
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/* read error */ |
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if (k != NUM_READS) { |
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break; |
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} |
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} |
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|
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/* we have a SDRAM0_TR1[RDCT] that is part of the window */ |
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if (j == NUM_TRIES) { |
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if (first_good == -1) |
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first_good = i; /* found beginning of window */ |
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} else { /* bad read */ |
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/* if we have not had a good read then don't care */ |
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if(first_good != -1) { |
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/* first failure after a good read */ |
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last_bad = i-1; |
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break; |
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} |
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} |
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} |
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|
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/* return the current value for TR1 */ |
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*tr1_value = (first_good + last_bad) / 2; |
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} |
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|
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void sdram_init(void) |
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{ |
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register uint reg; |
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int tr1_bank1, tr1_bank2; |
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|
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/*--------------------------------------------------------------------
|
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* Setup some default |
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*------------------------------------------------------------------*/ |
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ |
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ |
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mtsdram(mem_clktr, 0x40000000); /* ?? */ |
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mtsdram(mem_wddctr, 0x40000000); /* ?? */ |
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|
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/*clear this first, if the DDR is enabled by a debugger
|
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then you can not make changes. */ |
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mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ |
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|
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/*--------------------------------------------------------------------
|
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* Setup for board-specific specific mem |
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*------------------------------------------------------------------*/ |
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/*
|
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* Following for CAS Latency = 2.5 @ 133 MHz PLB |
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*/ |
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mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
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mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ |
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|
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mtsdram(mem_tr0, 0x410a4012); /* ?? */ |
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mtsdram(mem_rtr, 0x04080000); /* ?? */ |
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ |
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mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */ |
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udelay(400); /* Delay 200 usecs (min) */ |
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|
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/*--------------------------------------------------------------------
|
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* Enable the controller, then wait for DCEN to complete |
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*------------------------------------------------------------------*/ |
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mtsdram(mem_cfg0, 0x80000000); /* Enable */ |
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|
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for (;;) { |
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mfsdram(mem_mcsts, reg); |
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if (reg & 0x80000000) |
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break; |
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} |
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|
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sdram_tr1_set(0x00000000, &tr1_bank1); |
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sdram_tr1_set(0x08000000, &tr1_bank2); |
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mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) ); |
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} |
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|
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/*************************************************************************
|
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* long int initdram |
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* |
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************************************************************************/ |
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long int initdram(int board) |
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{ |
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sdram_init(); |
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return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ |
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} |
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|
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#if defined(CFG_DRAM_TEST) |
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int testdram(void) |
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{ |
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unsigned long *mem = (unsigned long *)0; |
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const unsigned long kend = (1024 / sizeof(unsigned long)); |
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unsigned long k, n; |
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|
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mtmsr(0); |
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|
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for (k = 0; k < CFG_KBYTES_SDRAM; |
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++k, mem += (1024 / sizeof(unsigned long))) { |
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if ((k & 1023) == 0) { |
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printf("%3d MB\r", k / 1024); |
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} |
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|
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memset(mem, 0xaaaaaaaa, 1024); |
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for (n = 0; n < kend; ++n) { |
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if (mem[n] != 0xaaaaaaaa) { |
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printf("SDRAM test fails at: %08x\n", |
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(uint) & mem[n]); |
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return 1; |
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} |
||||
} |
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|
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memset(mem, 0x55555555, 1024); |
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for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0x55555555) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
} |
||||
printf("SDRAM test passes\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned long addr; |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0. |
||||
| Set PLB3 arbiter to fair mode. |
||||
+-------------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp1, addr); |
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb3_acr); |
||||
mtdcr(plb3_acr, addr | 0x80000000); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0. |
||||
+-------------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp0, addr); |
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
||||
mtdcr(plb4_acr, addr); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode. |
||||
+-------------------------------------------------------------------------*/ |
||||
/* Segment0 */ |
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
||||
mtdcr(plb0_acr, addr); |
||||
|
||||
/* Segment1 */ |
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
||||
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
||||
mtdcr(plb1_acr, addr); |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller *hose) |
||||
{ |
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers |
||||
*--------------------------------------------------------------------------*/ |
||||
/*--------------------------------------------------------------------------+
|
||||
| PowerPC440 EP PCI Master configuration. |
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space. |
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
||||
| Use byte reversed out routines to handle endianess. |
||||
| Make this region non-prefetchable. |
||||
+--------------------------------------------------------------------------*/ |
||||
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
||||
|
||||
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Set up Configuration registers |
||||
*--------------------------------------------------------------------------*/ |
||||
|
||||
/* Program the board's subsystem id/vendor id */ |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
||||
CFG_PCI_SUBSYS_VENDORID); |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
||||
|
||||
/* Configure command register as bus master */ |
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
||||
|
||||
/* 240nS PCI clock */ |
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
||||
|
||||
/* No error reporting */ |
||||
pci_write_config_word(0, PCI_ERREN, 0); |
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
||||
|
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
||||
void pci_master_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned short temp_short; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs. |
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM). |
||||
+--------------------------------------------------------------------------*/ |
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short); |
||||
pci_write_config_word(0, PCI_COMMAND, |
||||
temp_short | PCI_COMMAND_MASTER | |
||||
PCI_COMMAND_MEMORY); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
/* Bamboo is always configured as host. */ |
||||
return (1); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
/*************************************************************************
|
||||
* hw_watchdog_reset |
||||
* |
||||
* This routine is called to reset (keep alive) the watchdog timer |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_HW_WATCHDOG) |
||||
void hw_watchdog_reset(void) |
||||
{ |
||||
|
||||
} |
||||
#endif |
||||
|
||||
void board_reset(void) |
||||
{ |
||||
/* give reset to BCSR */ |
||||
*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; |
||||
} |
||||
@ -0,0 +1,261 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* pf5200.c - main board support/init for the esd pf5200. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc5xxx.h> |
||||
#include <pci.h> |
||||
#include <command.h> |
||||
|
||||
#include "mt46v16m16-75.h" |
||||
|
||||
void init_power_switch(void); |
||||
|
||||
static void sdram_start(int hi_addr) |
||||
{ |
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
||||
|
||||
/* unlock mode register */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = |
||||
SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = |
||||
SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register: extended mode */ |
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register: reset DLL */ |
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = |
||||
SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* auto refresh */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = |
||||
SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register */ |
||||
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* normal operation */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
|
||||
/*
|
||||
* ATTENTION: Although partially referenced initdram does NOT make real use |
||||
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
||||
* is something else than 0x00000000. |
||||
*/ |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
ulong test1, test2; |
||||
|
||||
/* setup SDRAM chip selects */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set tap delay */ |
||||
*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* find RAM size using SDRAM CS0 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); |
||||
|
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else { |
||||
dramsize = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize < (1 << 20)) |
||||
dramsize = 0; |
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */ |
||||
if (dramsize > 0) { |
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = |
||||
0x13 + __builtin_ffs(dramsize >> 20) - 1; |
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ |
||||
} else { |
||||
#if 0 |
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */ |
||||
#else |
||||
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = |
||||
0x13 + __builtin_ffs(0x08000000 >> 20) - 1; |
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */ |
||||
#endif |
||||
} |
||||
|
||||
#if 0 |
||||
/* find RAM size using SDRAM CS1 only */ |
||||
sdram_start(0); |
||||
get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
sdram_start(1); |
||||
get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
sdram_start(0); |
||||
#endif |
||||
/* set SDRAM CS1 size according to the amount of RAM found */ |
||||
|
||||
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
||||
|
||||
init_power_switch(); |
||||
return (dramsize); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: esd CPX CPU5200 (mecp5200)\n"); |
||||
return 0; |
||||
} |
||||
|
||||
void flash_preinit(void) |
||||
{ |
||||
/*
|
||||
* Now, when we are in RAM, enable flash write |
||||
* access for detection process. |
||||
* Note that CS_BOOT cannot be cleared when |
||||
* executing in flash. |
||||
*/ |
||||
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
||||
} |
||||
|
||||
void flash_afterinit(ulong size) |
||||
{ |
||||
if (size == CFG_FLASH_SIZE) { |
||||
/* adjust mapping */ |
||||
*(vu_long *) MPC5XXX_BOOTCS_START = |
||||
*(vu_long *) MPC5XXX_CS0_START = |
||||
START_REG(CFG_BOOTCS_START | size); |
||||
*(vu_long *) MPC5XXX_BOOTCS_STOP = |
||||
*(vu_long *) MPC5XXX_CS0_STOP = |
||||
STOP_REG(CFG_BOOTCS_START | size, size); |
||||
} |
||||
} |
||||
|
||||
#ifdef CONFIG_PCI |
||||
static struct pci_controller hose; |
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *); |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_mpc5xxx_init(&hose); |
||||
} |
||||
#endif |
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) |
||||
|
||||
#define GPIO_PSC1_4 0x01000000UL |
||||
|
||||
void init_ide_reset(void) |
||||
{ |
||||
debug("init_ide_reset\n"); |
||||
|
||||
/* Configure PSC1_4 as GPIO output for ATA reset */ |
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
||||
} |
||||
|
||||
void ide_set_reset(int idereset) |
||||
{ |
||||
debug("ide_reset(%d)\n", idereset); |
||||
|
||||
if (idereset) |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
||||
else |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
||||
} |
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ |
||||
|
||||
#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) |
||||
#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) |
||||
#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010) |
||||
#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014) |
||||
|
||||
#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020) |
||||
#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028) |
||||
#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C) |
||||
#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C) |
||||
|
||||
#define GPIO_WU6 0x40000000UL |
||||
#define GPIO_USB0 0x00010000UL |
||||
#define GPIO_USB9 0x08000000UL |
||||
#define GPIO_USB9S 0x00080000UL |
||||
|
||||
void init_power_switch(void) |
||||
{ |
||||
debug("init_power_switch\n"); |
||||
|
||||
/* Configure GPIO_WU6 as GPIO output for ATA reset */ |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; |
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0; |
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0; |
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; |
||||
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { |
||||
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
} |
||||
@ -0,0 +1,37 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#define SDRAM_DDR 1 /* is DDR */ |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x018D0000 |
||||
#define SDRAM_EMODE 0x40090000 |
||||
#define SDRAM_CONTROL 0x705f0f00 |
||||
#define SDRAM_CONFIG1 0x73722930 |
||||
#define SDRAM_CONFIG2 0x47770000 |
||||
#define SDRAM_TAPDELAY 0x10000000 |
||||
|
||||
#else |
||||
#error CONFIG_MPC5200 not defined |
||||
#endif |
||||
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* |
||||
* Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __P3MX_H__ |
||||
#define __P3MX_H__ |
||||
|
||||
#define LED_OFF 1 |
||||
#define LED_GREEN 2 |
||||
#define LED_RED 3 |
||||
#define LED_ORANGE 4 |
||||
|
||||
#endif /* __P3MX_H__ */ |
||||
|
||||
@ -0,0 +1,345 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* (c) 2005 esd gmbh Hannover |
||||
* |
||||
* |
||||
* from IceCube.h file |
||||
* by Reinhard Arlt reinhard.arlt@esd-electronics.com |
||||
* |
||||
*************************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ |
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
||||
#define CONFIG_ICECUBE 1 /* ... on IceCube board */ |
||||
#define CONFIG_MECP5200 1 /* ... on MECP5200 board */ |
||||
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ |
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
||||
#if 0 /* test-only */
|
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
||||
#else |
||||
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ |
||||
#endif |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
|
||||
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ |
||||
|
||||
#define CONFIG_MII |
||||
#if 0 /* test-only !!! */
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_EEPRO100 1 |
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
#define CONFIG_NS8382X 1 |
||||
#endif |
||||
|
||||
#else /* MPC5100 */ |
||||
|
||||
#endif |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* USB */ |
||||
#if 0 |
||||
#define CONFIG_USB_OHCI |
||||
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT |
||||
#define CONFIG_USB_STORAGE |
||||
#else |
||||
#define ADD_USB_CMD 0 |
||||
#endif |
||||
|
||||
/*
|
||||
* Supported commands |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_EXT2 | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_ELF) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
||||
# define CFG_LOWBOOT 1 |
||||
# define CFG_LOWBOOT16 1 |
||||
#endif |
||||
#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ |
||||
# define CFG_LOWBOOT 1 |
||||
# define CFG_LOWBOOT08 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Welcome to CBX-CPU5200 (mecp5200);" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
|
||||
"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
|
||||
"net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
|
||||
"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
|
||||
"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
|
||||
"loadaddr=01000000\0" \
|
||||
"serverip=192.168.2.99\0" \
|
||||
"gatewayip=10.0.0.79\0" \
|
||||
"user=mu\0" \
|
||||
"target=mecp5200.esd\0" \
|
||||
"script=mecp5200.bat\0" \
|
||||
"image=/tftpboot/vxWorks_mecp5200\0" \
|
||||
"ipaddr=10.0.13.196\0" \
|
||||
"netmask=255.255.0.0\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_vxworks0" |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
||||
#endif |
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
||||
|
||||
#define CFG_I2C_SPEED 86000 /* 100 kHz */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
#define CFG_I2C_MULTI_EEPROMS 1 |
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xFFC00000 |
||||
#define CFG_FLASH_SIZE 0x00400000 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000) |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 512 |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#if 1 /* test-only */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#else |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ |
||||
#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ |
||||
/* total size of a CAT24WC32 is 8192 bytes */ |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#endif |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ |
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ |
||||
#if 0 |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#endif |
||||
#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */ |
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ |
||||
|
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Use SRAM until RAM will be available */ |
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ |
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
/*
|
||||
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb |
||||
*/ |
||||
/* #define CONFIG_FEC_10MBIT 1 */ |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
#define CONFIG_UDP_CHECKSUM 1 |
||||
|
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
*/ |
||||
#define CFG_GPS_PORT_CONFIG 0x01052444 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#if defined(CONFIG_MPC5200) |
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CFG_HID0_FINAL HID0_ICE |
||||
#else |
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL 0 |
||||
#endif |
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE |
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
||||
#define CFG_BOOTCS_CFG 0x00085d00 |
||||
|
||||
#define CFG_CS0_START CFG_FLASH_BASE |
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE |
||||
|
||||
#define CFG_CS1_START 0xfd000000 |
||||
#define CFG_CS1_SIZE 0x00010000 |
||||
#define CFG_CS1_CFG 0x10101410 |
||||
|
||||
#define CFG_CS_BURST 0x00000000 |
||||
#define CFG_CS_DEADCYCLE 0x33333333 |
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_USB_CLOCK 0x0001BBBB |
||||
#define CONFIG_USB_CONFIG 0x00001000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */ |
||||
#define CONFIG_IDE_PREINIT |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (0x0060) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET (0x005C) |
||||
|
||||
/* Interval between registers */ |
||||
#define CFG_ATA_STRIDE 4 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,340 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2005-2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* yellowstone.h - configuration for YELLOWSTONE board |
||||
***********************************************************************/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ |
||||
#define CONFIG_440GR 1 /* Specific PPC440EP support */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||
#define CONFIG_BOARD_RESET 1 /* call board_reset() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ |
||||
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ |
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 |
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 |
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 |
||||
|
||||
/*Don't change either of these*/ |
||||
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ |
||||
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
||||
/*Don't change either of these*/ |
||||
|
||||
#define CFG_USB_DEVICE 0x50000000 |
||||
#define CFG_NVRAM_BASE_ADDR 0x80000000 |
||||
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) |
||||
#define CFG_BOOT_BASE_ADDR 0xf0000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in SDRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
||||
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ |
||||
#define CFG_INIT_RAM_END (8 << 10) |
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SERIAL_MULTI 1 |
||||
/*define this if you want console on UART1*/ |
||||
#undef CONFIG_UART1_CONSOLE |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or EEPROM). |
||||
* Note: DENX encourages to use redundant environment in FLASH. |
||||
*/ |
||||
#if 1 |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
#else |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif /* CFG_ENV_IS_IN_FLASH */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
||||
#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
||||
#define CFG_SDRAM_BANKS (2) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_MULTI_EEPROMS |
||||
#define CFG_I2C_EEPROM_ADDR (0xa8>>1) |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ |
||||
#define CFG_ENV_OFFSET 0x0 |
||||
#endif /* CFG_ENV_IS_IN_EEPROM */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=yellowstone\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/yellowstone/uImage\0" \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"ramdisk_addr=fc180000\0" \
|
||||
"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \
|
||||
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
|
||||
"cp.b 100000 fff80000 80000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_NET_MULTI 1 /* required for netconsole */ |
||||
#define CONFIG_PHY1_ADDR 3 |
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
#ifdef CONFIG_440EP |
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
/*Comment this out to enable USB 1.1 device*/ |
||||
#define USB_2_0_DEVICE |
||||
#endif /*CONFIG_440EP*/ |
||||
|
||||
#ifdef DEBUG |
||||
#define CONFIG_PANIC_HANG |
||||
#else |
||||
#define CONFIG_HW_WATCHDOG /* watchdog */ |
||||
#endif |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
#define CONFIG_LYNXKDI 1 /* support kdi files */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT |
||||
#define CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH CFG_FLASH_BASE |
||||
#define CFG_CPLD 0x80000000 |
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */ |
||||
#define CFG_EBC_PB0AP 0x03017300 |
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) |
||||
|
||||
/* Memory Bank 2 (CPLD) initialization */ |
||||
#define CFG_EBC_PB2AP 0x04814500 |
||||
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue