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@ -151,6 +151,103 @@ |
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#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) |
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#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) |
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/* Power bus message definitions */ |
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/* The TWL4030/5030 splits its power-management resources (the various
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* regulators, clock and reset lines) into 3 processor groups - P1, P2 and |
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* P3. These groups can then be configured to transition between sleep, wait-on |
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* and active states by sending messages to the power bus. See Section 5.4.2 |
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* Power Resources of TWL4030 TRM |
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*/ |
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/* Processor groups */ |
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#define DEV_GRP_NULL 0x0 |
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#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ |
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#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ |
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#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ |
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/* Resource groups */ |
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#define RES_GRP_RES 0x0 /* Reserved */ |
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#define RES_GRP_PP 0x1 /* Power providers */ |
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#define RES_GRP_RC 0x2 /* Reset and control */ |
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#define RES_GRP_PP_RC 0x3 |
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#define RES_GRP_PR 0x4 /* Power references */ |
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#define RES_GRP_PP_PR 0x5 |
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#define RES_GRP_RC_PR 0x6 |
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#define RES_GRP_ALL 0x7 /* All resource groups */ |
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#define RES_TYPE2_R0 0x0 |
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#define RES_TYPE_ALL 0x7 |
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/* Resource states */ |
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#define RES_STATE_WRST 0xF |
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#define RES_STATE_ACTIVE 0xE |
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#define RES_STATE_SLEEP 0x8 |
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#define RES_STATE_OFF 0x0 |
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/* Power resources */ |
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/* Power providers */ |
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#define RES_VAUX1 1 |
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#define RES_VAUX2 2 |
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#define RES_VAUX3 3 |
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#define RES_VAUX4 4 |
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#define RES_VMMC1 5 |
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#define RES_VMMC2 6 |
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#define RES_VPLL1 7 |
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#define RES_VPLL2 8 |
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#define RES_VSIM 9 |
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#define RES_VDAC 10 |
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#define RES_VINTANA1 11 |
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#define RES_VINTANA2 12 |
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#define RES_VINTDIG 13 |
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#define RES_VIO 14 |
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#define RES_VDD1 15 |
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#define RES_VDD2 16 |
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#define RES_VUSB_1V5 17 |
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#define RES_VUSB_1V8 18 |
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#define RES_VUSB_3V1 19 |
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#define RES_VUSBCP 20 |
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#define RES_REGEN 21 |
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/* Reset and control */ |
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#define RES_NRES_PWRON 22 |
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#define RES_CLKEN 23 |
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#define RES_SYSEN 24 |
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#define RES_HFCLKOUT 25 |
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#define RES_32KCLKOUT 26 |
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#define RES_RESET 27 |
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/* Power Reference */ |
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#define RES_Main_Ref 28 |
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#define TOTAL_RESOURCES 28 |
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/*
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* Power Bus Message Format ... these can be sent individually by Linux, |
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* but are usually part of downloaded scripts that are run when various |
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* power events are triggered. |
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* |
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* Broadcast Message (16 Bits): |
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* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] |
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* RES_STATE[3:0] |
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* |
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* Singular Message (16 Bits): |
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* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] |
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*/ |
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#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ |
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((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
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| (type) << 4 | (state)) |
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#define MSG_SINGULAR(devgrp, id, state) \ |
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((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) |
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#define MSG_BROADCAST_ALL(devgrp, state) \ |
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((devgrp) << 5 | (state)) |
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#define MSG_BROADCAST_REF MSG_BROADCAST_ALL |
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#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL |
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#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL |
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/* Power Managment Receiver */ |
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#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B |
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#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C |
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@ -311,6 +408,7 @@ |
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#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 |
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#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 |
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#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 |
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#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 |
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/* Device Selection in PM Receiver Module */ |
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#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20 |
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