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@ -18,6 +18,7 @@ |
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#include <common.h> |
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#include <fsl_esdhc.h> |
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#include <mmc.h> |
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#include <netdev.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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@ -29,6 +30,12 @@ DECLARE_GLOBAL_DATA_PTR; |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
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#define ETH_PHY_RESET IMX_GPIO_NR(4, 21) |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
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@ -50,11 +57,35 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { |
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MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const fec_pads[] = { |
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MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), |
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MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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}; |
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
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} |
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static void setup_iomux_fec(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
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/* Reset LAN8720 PHY */ |
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gpio_direction_output(ETH_PHY_RESET , 0); |
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udelay(1000); |
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gpio_set_value(ETH_PHY_RESET, 1); |
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} |
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static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC2_BASE_ADDR}, |
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}; |
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@ -72,6 +103,40 @@ int board_mmc_init(bd_t *bis) |
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
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} |
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#ifdef CONFIG_FEC_MXC |
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int board_eth_init(bd_t *bis) |
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{ |
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int ret; |
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setup_iomux_fec(); |
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ret = cpu_eth_init(bis); |
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if (ret) { |
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printf("FEC MXC: %s:failed\n", __func__); |
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return ret; |
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} |
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return 0; |
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} |
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static int setup_fec(void) |
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{ |
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struct iomuxc_base_regs *iomuxc_regs = |
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(struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; |
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int ret; |
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/* clear gpr1[14], gpr1[18:17] to select anatop clock */ |
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); |
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ret = enable_fec_anatop_clock(); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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#endif |
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int board_early_init_f(void) |
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{ |
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setup_iomux_uart(); |
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@ -83,6 +148,9 @@ int board_init(void) |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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#ifdef CONFIG_FEC_MXC |
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setup_fec(); |
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#endif |
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return 0; |
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} |
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