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x86: Add a x86_ prefix to the x86-specific PCI functions

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These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
master
Simon Glass 10 years ago
parent 5f7bfdd630
commit 31f57c2873
21 changed files with 199 additions and 195 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 5
      arch/x86/cpu/baytrail/early_uart.c
  2. 32
      arch/x86/cpu/ivybridge/bd82x6x.c
  3. 38
      arch/x86/cpu/ivybridge/cpu.c
  4. 58
      arch/x86/cpu/ivybridge/early_init.c
  5. 12
      arch/x86/cpu/ivybridge/early_me.c
  6. 4
      arch/x86/cpu/ivybridge/gma.c
  7. 74
      arch/x86/cpu/ivybridge/lpc.c
  8. 6
      arch/x86/cpu/ivybridge/northbridge.c
  9. 4
      arch/x86/cpu/ivybridge/pch.c
  10. 4
      arch/x86/cpu/ivybridge/pci.c
  11. 4
      arch/x86/cpu/ivybridge/report_platform.c
  12. 61
      arch/x86/cpu/ivybridge/sata.c
  13. 20
      arch/x86/cpu/ivybridge/sdram.c
  14. 4
      arch/x86/cpu/ivybridge/usb_ehci.c
  15. 8
      arch/x86/cpu/ivybridge/usb_xhci.c
  16. 12
      arch/x86/cpu/pci.c
  17. 4
      arch/x86/cpu/quark/quark.c
  18. 4
      arch/x86/cpu/queensbay/tnc.c
  19. 12
      arch/x86/include/asm/pci.h
  20. 12
      arch/x86/lib/bios_interrupts.c
  21. 16
      drivers/gpio/intel_ich6_gpio.c

5
arch/x86/cpu/baytrail/early_uart.c
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@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
static void pci_write_config32(int dev, unsigned int where, u32 value)
static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where, u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
1);
/*
* Set up the pads to the UART function. This allows the signals to

32
arch/x86/cpu/ivybridge/bd82x6x.c
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@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug("bd82x6x PCI init.\n");
/* Enable Bus Master */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, reg16);
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
reg16 = pci_read_config16(dev, BCTRL);
reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
pci_write_config16(dev, BCTRL, reg16);
x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
reg8 = x86_pci_read_config8(dev, SMLT);
reg8 &= 0x07;
reg8 |= (0x04 << 3);
pci_write_config8(dev, SMLT, reg8);
x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, PSTS);
reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
pci_write_config16(dev, PSTS, reg16);
x86_pci_write_config16(dev, PSTS, reg16);
reg16 = pci_read_config16(dev, SECSTS);
reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
pci_write_config16(dev, SECSTS, reg16);
x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
command = pci_read_config16(dev, PCI_COMMAND);
command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
@ -67,7 +67,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
* ROM and APICs to become invisible.
*/
debug("%x cmd <- %02x\n", dev, command);
pci_write_config16(dev, PCI_COMMAND, command);
x86_pci_write_config16(dev, PCI_COMMAND, command);
#else
printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
@ -77,11 +77,11 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
{
uint16_t ctrl;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= PCI_COMMAND_IO;
ctrl |= PCI_BRIDGE_CTL_VGA;
debug("%x bridge ctrl <- %04x\n", dev, ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
bd82x6x_pci_dev_enable_resources(dev);
}

38
arch/x86/cpu/ivybridge/cpu.c
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@ -167,21 +167,21 @@ static int enable_smbus(void)
dev = PCI_BDF(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
value = pci_read_config16(dev, 0x0);
value = x86_pci_read_config16(dev, 0x0);
if (value != 0x8086) {
printf("SMBus controller not found\n");
return -ENOSYS;
}
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
x86_pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
x86_pci_write_config8(dev, HOSTC, HST_EN);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* Disable interrupt generation. */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
@ -214,25 +214,25 @@ static void enable_usb_bar(void)
u32 cmd;
/* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI0_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI0_TEMP_BAR0);
cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 1 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
/* USB3 Controller */
pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
PCH_XHCI_TEMP_BAR0);
cmd = pci_read_config32(usb3, PCI_COMMAND);
x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
PCH_XHCI_TEMP_BAR0);
cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb3, PCI_COMMAND, cmd);
x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
}
static int report_bist_failure(void)
@ -320,8 +320,8 @@ int print_cpuinfo(void)
gd->arch.pei_boot_mode = boot_mode;
/* TODO: Move this to the board or driver */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
/* Print processor name */
name = cpu_get_name(processor_name);

58
arch/x86/cpu/ivybridge/early_init.c
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@ -17,10 +17,10 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
{
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
debug("Disabling watchdog reboot\n");
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
@ -28,25 +28,27 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
/* Set up all hardcoded northbridge BARs */
debug("Setting up static registers\n");
pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
x86_pci_write_config32(pch_dev, MCHBAR + 4,
(0LL + DEFAULT_MCHBAR) >> 32);
/* 64MB - busses 0-63 */
pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
pci_write_config32(pch_dev, PCIEXBAR + 4,
(0LL + DEFAULT_PCIEXBAR) >> 32);
pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
(0LL + DEFAULT_PCIEXBAR) >> 32);
x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
x86_pci_write_config32(pch_dev, DMIBAR + 4,
(0LL + DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(pch_dev, PAM0, 0x30);
pci_write_config8(pch_dev, PAM1, 0x33);
pci_write_config8(pch_dev, PAM2, 0x33);
pci_write_config8(pch_dev, PAM3, 0x33);
pci_write_config8(pch_dev, PAM4, 0x33);
pci_write_config8(pch_dev, PAM5, 0x33);
pci_write_config8(pch_dev, PAM6, 0x33);
x86_pci_write_config8(pch_dev, PAM0, 0x30);
x86_pci_write_config8(pch_dev, PAM1, 0x33);
x86_pci_write_config8(pch_dev, PAM2, 0x33);
x86_pci_write_config8(pch_dev, PAM3, 0x33);
x86_pci_write_config8(pch_dev, PAM4, 0x33);
x86_pci_write_config8(pch_dev, PAM5, 0x33);
x86_pci_write_config8(pch_dev, PAM6, 0x33);
}
static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
@ -55,7 +57,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
u16 reg16;
u8 reg8;
reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
switch (reg16) {
case 0x0102: /* GT1 Desktop */
case 0x0106: /* GT1 Mobile */
@ -75,7 +77,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
debug("Initialising Graphics\n");
/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
reg16 = pci_read_config16(pch_dev, GGC);
reg16 = x86_pci_read_config16(pch_dev, GGC);
reg16 &= ~0x00f8;
reg16 |= 1 << 3;
/* Program GTT memory by setting GGC[9:8] = 2MB */
@ -83,13 +85,13 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
reg16 |= 2 << 8;
/* Enable VGA decode */
reg16 &= ~0x0002;
pci_write_config16(pch_dev, GGC, reg16);
x86_pci_write_config16(pch_dev, GGC, reg16);
/* Enable 256MB aperture */
reg8 = pci_read_config8(video_dev, MSAC);
reg8 = x86_pci_read_config8(video_dev, MSAC);
reg8 &= ~0x06;
reg8 |= 0x02;
pci_write_config8(video_dev, MSAC, reg8);
x86_pci_write_config8(video_dev, MSAC, reg8);
/* Erratum workarounds */
reg32 = readl(MCHBAR_REG(0x5f00));
@ -124,22 +126,22 @@ void sandybridge_early_init(int chipset_type)
u8 reg8;
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(pch_dev, 0xe4);
capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
if (capid0_a & (1 << 10)) {
reg8 = pci_read_config8(pch_dev, 0xf3);
reg8 = x86_pci_read_config8(pch_dev, 0xf3);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == SANDYBRIDGE_MOBILE)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(pch_dev, 0xf3, reg8);
x86_pci_write_config8(pch_dev, 0xf3, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
sandybridge_setup_bars(pch_dev, lpc_dev);
/* Device Enable */
pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
sandybridge_setup_graphics(pch_dev, video_dev);
}

12
arch/x86/cpu/ivybridge/early_me.c
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@ -29,7 +29,7 @@ static inline void pci_read_dword_ptr(void *ptr, int offset)
{
u32 dword;
dword = pci_read_config32(PCH_ME_DEV, offset);
dword = x86_pci_read_config32(PCH_ME_DEV, offset);
memcpy(ptr, &dword, sizeof(dword));
}
@ -37,7 +37,7 @@ static inline void pci_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
pci_write_config32(PCH_ME_DEV, offset, dword);
x86_pci_write_config32(PCH_ME_DEV, offset, dword);
}
void intel_early_me_status(void)
@ -101,7 +101,7 @@ static inline void set_global_reset(int enable)
{
u32 etr3;
etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
@ -112,7 +112,7 @@ static inline void set_global_reset(int enable)
else
etr3 &= ~ETR3_CF9GR;
pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
}
int intel_early_me_init_done(u8 status)
@ -127,8 +127,8 @@ int intel_early_me_init_done(u8 status)
};
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
mebase_h &= 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);

4
arch/x86/cpu/ivybridge/gma.c
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@ -741,9 +741,9 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
int ret;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
x86_pci_write_config32(dev, PCI_COMMAND, reg32);
/* Use write-combining for the graphics memory, 256MB */
base = pci_read_bar32(hose, dev, 2);

74
arch/x86/cpu/ivybridge/lpc.c
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@ -29,7 +29,7 @@ static int pch_enable_apic(pci_dev_t dev)
int i;
/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
pci_write_config8(dev, ACPI_CNTL, 0x80);
x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
writel(0, IO_APIC_INDEX);
writel(1 << 25, IO_APIC_DATA);
@ -72,9 +72,9 @@ static void pch_enable_serial_irqs(pci_dev_t dev)
/* Set packet length and toggle silent mode bit for one frame. */
value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
pci_write_config8(dev, SERIRQ_CNTL, value);
x86_pci_write_config8(dev, SERIRQ_CNTL, value);
#else
pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
#endif
}
@ -86,15 +86,15 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
sizeof(route)))
return -EINVAL;
ptr = route;
pci_write_config8(dev, PIRQA_ROUT, *ptr++);
pci_write_config8(dev, PIRQB_ROUT, *ptr++);
pci_write_config8(dev, PIRQC_ROUT, *ptr++);
pci_write_config8(dev, PIRQD_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
pci_write_config8(dev, PIRQE_ROUT, *ptr++);
pci_write_config8(dev, PIRQF_ROUT, *ptr++);
pci_write_config8(dev, PIRQG_ROUT, *ptr++);
pci_write_config8(dev, PIRQH_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
/*
* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
@ -116,7 +116,7 @@ static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
reg |= route[gpi] << (gpi * 2);
pci_write_config32(dev, 0xb8, reg);
x86_pci_write_config32(dev, 0xb8, reg);
return 0;
}
@ -141,7 +141,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
*/
pwr_on = MAINBOARD_POWER_ON;
reg16 = pci_read_config16(dev, GEN_PMCON_3);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
@ -168,7 +168,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
pci_write_config16(dev, GEN_PMCON_3, reg16);
x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
debug("Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
@ -192,21 +192,21 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
reg16 |= (3 << 0); /* Periodic SMI every 8s */
#endif
pci_write_config16(dev, GEN_PMCON_1, reg16);
x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
/* Set the board's GPI routing. */
ret = pch_gpi_routing(blob, node, dev);
if (ret)
return ret;
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
"intel,gpe0-enable", 0));
@ -231,11 +231,11 @@ static void pch_rtc_init(pci_dev_t dev)
int rtc_failed;
u8 reg8;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
}
debug("rtc_failed = 0x%x\n", rtc_failed);
@ -258,7 +258,7 @@ static void pch_rtc_init(pci_dev_t dev)
static void cpt_pm_init(pci_dev_t dev)
{
debug("CougarPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
x86_pci_write_config8(dev, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
setbits_le32(RCB_REG(0x228c), 1 << 0);
@ -302,7 +302,7 @@ static void cpt_pm_init(pci_dev_t dev)
static void ppt_pm_init(pci_dev_t dev)
{
debug("PantherPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
x86_pci_write_config8(dev, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), 1 << 0);
setbits_le32(RCB_REG(0x228c), 1 << 0);
setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
@ -356,9 +356,9 @@ static void enable_clock_gating(pci_dev_t dev)
setbits_le32(RCB_REG(0x2234), 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
reg16 |= (1 << 2) | (1 << 11);
pci_write_config16(dev, GEN_PMCON_1, reg16);
x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
@ -412,15 +412,15 @@ static void pch_lock_smm(pci_dev_t dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
debug("Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
debug("ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
@ -428,9 +428,9 @@ static void pch_lock_smm(pci_dev_t dev)
writeb(0, 0xfff00000);
debug("Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
debug("Done.\n");
@ -443,9 +443,9 @@ static void pch_disable_smm_only_flashing(pci_dev_t dev)
u8 reg8;
debug("Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
}
static void pch_fixups(pci_dev_t dev)
@ -453,9 +453,9 @@ static void pch_fixups(pci_dev_t dev)
u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */
gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
gen_pmcon_2 |= (1 << 7);
pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
/* Enable DMI ASPM in the PCH */
clrbits_le32(RCB_REG(0x2304), 1 << 10);
@ -478,10 +478,10 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
return -EINVAL;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */
@ -491,7 +491,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
pci_write_config32(dev, LPC_GENX_DEC(i), reg);
x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
}
return 0;
@ -514,7 +514,7 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev)
return -ENOENT;
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
pch_enable_apic(dev);

6
arch/x86/cpu/ivybridge/northbridge.c
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@ -30,7 +30,7 @@ int bridge_silicon_revision(void)
result = cpuid(1);
stepping = result.eax & 0xf;
dev = PCI_BDF(0, 0, 0);
bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
@ -55,7 +55,7 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = 0;
*len = 0;
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
@ -170,7 +170,7 @@ void northbridge_init(pci_dev_t dev)
void northbridge_enable(pci_dev_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
switch (pci_read_config32(dev, SKPAD)) {
switch (x86_pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
debug("Normal boot.\n");
apci_set_slp_type(0);

4
arch/x86/cpu/ivybridge/pch.c
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@ -21,7 +21,7 @@ int pch_silicon_revision(void)
dev = PCH_LPC_DEV;
if (pch_revision_id < 0)
pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
return pch_revision_id;
}
@ -32,7 +32,7 @@ int pch_silicon_type(void)
dev = PCH_LPC_DEV;
if (pch_type < 0)
pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
return pch_type;
}

4
arch/x86/cpu/ivybridge/pci.c
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@ -70,9 +70,9 @@ int board_pci_pre_scan(struct pci_controller *hose)
reg16 = 0xff;
dev = PCH_DEV;
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.

4
arch/x86/cpu/ivybridge/report_platform.c
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@ -70,14 +70,14 @@ static void report_pch_info(void)
u16 dev_id;
uint8_t rev_id;
dev_id = pci_read_config16(PCH_LPC_DEV, 2);
dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {
pch_type = pch_table[i].dev_name;
break;
}
}
rev_id = pci_read_config8(PCH_LPC_DEV, 8);
rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
rev_id);
}

61
arch/x86/cpu/ivybridge/sata.c
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@ -14,14 +14,14 @@
static inline u32 sir_read(pci_dev_t dev, int idx)
{
pci_write_config32(dev, SATA_SIRI, idx);
return pci_read_config32(dev, SATA_SIRD);
x86_pci_write_config32(dev, SATA_SIRI, idx);
return x86_pci_read_config32(dev, SATA_SIRD);
}
static inline void sir_write(pci_dev_t dev, int idx, u32 value)
{
pci_write_config32(dev, SATA_SIRI, idx);
pci_write_config32(dev, SATA_SIRD, value);
x86_pci_write_config32(dev, SATA_SIRI, idx);
x86_pci_write_config32(dev, SATA_SIRD, value);
}
static void common_sata_init(pci_dev_t dev, unsigned int port_map)
@ -31,17 +31,17 @@ static void common_sata_init(pci_dev_t dev, unsigned int port_map)
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
x86_pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port enable */
reg16 = pci_read_config16(dev, 0x92);
reg16 = x86_pci_read_config16(dev, 0x92);
reg16 &= ~0x3f;
reg16 |= port_map;
pci_write_config16(dev, 0x92, reg16);
x86_pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */
port_map &= 0xff;
pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
}
void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
@ -60,7 +60,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
"sata_interface_speed_support", 0);
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
if (!mode || !strcmp(mode, "ahci")) {
@ -69,18 +69,18 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
debug("SATA: Controller in AHCI mode\n");
/* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
x86_pci_write_config8(dev, INTR_LN, 0x0a);
/* Set timings */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
common_sata_init(dev, 0x8000 | port_map);
@ -115,22 +115,22 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
/* No AHCI: clear AHCI base */
pci_write_bar32(hose, dev, 5, 0x00000000);
/* And without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
pci_write_config8(dev, 0x09, 0x80);
x86_pci_write_config8(dev, 0x09, 0x80);
/* Set timings */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
common_sata_init(dev, port_map);
} else {
@ -140,31 +140,32 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
pci_write_bar32(hose, dev, 5, 0x00000000);
/* And without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/*
* Native mode capable on both primary and secondary (0xa)
* OR'ed with enabled (0x50) = 0xf
*/
pci_write_config8(dev, 0x09, 0x8f);
x86_pci_write_config8(dev, 0x09, 0x8f);
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0xff);
x86_pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_SITRE | IDE_ISP_3_CLOCKS |
IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
x86_pci_write_config16(dev, IDE_SDMA_CNT,
IDE_SSDE0 | IDE_PSDE0);
x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
common_sata_init(dev, port_map);
}
@ -221,5 +222,5 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
map |= (port_map ^ 0x3f) << 8;
pci_write_config16(dev, 0x90, map);
x86_pci_write_config16(dev, 0x90, map);
}

20
arch/x86/cpu/ivybridge/sdram.c
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@ -444,7 +444,7 @@ int sdram_initialise(struct pei_data *pei_data)
* Send ME init done for SandyBridge here. This is done inside the
* SystemAgent binary on IvyBridge
*/
done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
done &= BASE_REV_MASK;
if (BASE_REV_SNB == done)
intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
@ -615,24 +615,24 @@ static int sdram_find(pci_dev_t dev)
*/
/* Top of Upper Usable DRAM, including remap */
touud = pci_read_config32(dev, TOUUD+4);
touud = x86_pci_read_config32(dev, TOUUD+4);
touud <<= 32;
touud |= pci_read_config32(dev, TOUUD);
touud |= x86_pci_read_config32(dev, TOUUD);
/* Top of Lower Usable DRAM */
tolud = pci_read_config32(dev, TOLUD);
tolud = x86_pci_read_config32(dev, TOLUD);
/* Top of Memory - does not account for any UMA */
tom = pci_read_config32(dev, 0xa4);
tom = x86_pci_read_config32(dev, 0xa4);
tom <<= 32;
tom |= pci_read_config32(dev, 0xa0);
tom |= x86_pci_read_config32(dev, 0xa0);
debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
/* ME UMA needs excluding if total memory <4GB */
me_base = pci_read_config32(dev, 0x74);
me_base = x86_pci_read_config32(dev, 0x74);
me_base <<= 32;
me_base |= pci_read_config32(dev, 0x70);
me_base |= x86_pci_read_config32(dev, 0x70);
debug("MEBASE %llx\n", me_base);
@ -650,7 +650,7 @@ static int sdram_find(pci_dev_t dev)
}
/* Graphics memory comes next */
ggc = pci_read_config16(dev, GGC);
ggc = x86_pci_read_config16(dev, GGC);
if (!(ggc & 2)) {
debug("IGD decoded, subtracting ");
@ -670,7 +670,7 @@ static int sdram_find(pci_dev_t dev)
}
/* Calculate TSEG size from its base which must be below GTT */
tseg_base = pci_read_config32(dev, 0xb8);
tseg_base = x86_pci_read_config32(dev, 0xb8);
uma_size = (uma_memory_base - tseg_base) >> 10;
tomk -= uma_size;
uma_memory_base = tomk * 1024ULL;

4
arch/x86/cpu/ivybridge/usb_ehci.c
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@ -20,10 +20,10 @@ void bd82x6x_usb_ehci_init(pci_dev_t dev)
writel(reg32, RCB_REG(0x35b0));
debug("EHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
/* reg32 |= PCI_COMMAND_SERR; */
pci_write_config32(dev, PCI_COMMAND, reg32);
x86_pci_write_config32(dev, PCI_COMMAND, reg32);
debug("done.\n");
}

8
arch/x86/cpu/ivybridge/usb_xhci.c
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@ -16,17 +16,17 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev)
debug("XHCI: Setting up controller.. ");
/* lock overcurrent map */
reg32 = pci_read_config32(dev, 0x44);
reg32 = x86_pci_read_config32(dev, 0x44);
reg32 |= 1;
pci_write_config32(dev, 0x44, reg32);
x86_pci_write_config32(dev, 0x44, reg32);
/* Enable clock gating */
reg32 = pci_read_config32(dev, 0x40);
reg32 = x86_pci_read_config32(dev, 0x40);
reg32 &= ~((1 << 20) | (1 << 21));
reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
reg32 |= (1 << 31); /* lock */
pci_write_config32(dev, 0x40, reg32);
x86_pci_write_config32(dev, 0x40, reg32);
debug("done.\n");
}

12
arch/x86/cpu/pci.c
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@ -70,7 +70,7 @@ static struct pci_controller *get_hose(void)
return pci_bus_to_hose(0);
}
unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
{
uint8_t value;
@ -79,7 +79,7 @@ unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
return value;
}
unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
{
uint16_t value;
@ -88,7 +88,7 @@ unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
return value;
}
unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
{
uint32_t value;
@ -97,17 +97,17 @@ unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
return value;
}
void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_byte(get_hose(), dev, where, value);
}
void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_word(get_hose(), dev, where, value);
}
void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
{
pci_hose_write_config_dword(get_hose(), dev, where, value);
}

4
arch/x86/cpu/quark/quark.c
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@ -30,9 +30,9 @@ static void unprotect_spi_flash(void)
{
u32 bc;
bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
bc |= 0x1; /* unprotect the flash */
pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}
static void quark_setup_bars(void)

4
arch/x86/cpu/queensbay/tnc.c
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@ -16,9 +16,9 @@ static void unprotect_spi_flash(void)
{
u32 bc;
bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
bc = x86_pci_read_config32(PCH_LPC_DEV, 0xd8);
bc |= 0x1; /* unprotect the flash */
pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
x86_pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
}
int arch_cpu_init(void)

12
arch/x86/include/asm/pci.h
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@ -48,13 +48,13 @@ int board_pci_post_scan(struct pci_controller *hose);
* Simple PCI access routines - these work from either the early PCI hose
* or the 'real' one, created after U-Boot has memory available
*/
unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
#endif /* __ASSEMBLY__ */

12
arch/x86/lib/bios_interrupts.c
Unescape View File

@ -172,28 +172,28 @@ int int1a_handler(void)
}
switch (func) {
case 0xb108: /* Read Config Byte */
byte = pci_read_config8(dev, reg);
byte = x86_pci_read_config8(dev, reg);
M.x86.R_ECX = byte;
break;
case 0xb109: /* Read Config Word */
word = pci_read_config16(dev, reg);
word = x86_pci_read_config16(dev, reg);
M.x86.R_ECX = word;
break;
case 0xb10a: /* Read Config Dword */
dword = pci_read_config32(dev, reg);
dword = x86_pci_read_config32(dev, reg);
M.x86.R_ECX = dword;
break;
case 0xb10b: /* Write Config Byte */
byte = M.x86.R_ECX;
pci_write_config8(dev, reg, byte);
x86_pci_write_config8(dev, reg, byte);
break;
case 0xb10c: /* Write Config Word */
word = M.x86.R_ECX;
pci_write_config16(dev, reg, word);
x86_pci_write_config16(dev, reg, word);
break;
case 0xb10d: /* Write Config Dword */
dword = M.x86.R_ECX;
pci_write_config32(dev, reg, dword);
x86_pci_write_config32(dev, reg, dword);
break;
}

16
drivers/gpio/intel_ich6_gpio.c
Unescape View File

@ -64,13 +64,13 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
pci_dev = PCI_BDF(0, 0x1f, 0);
/* Is the device present? */
tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID);
if (tmpword != PCI_VENDOR_ID_INTEL) {
debug("%s: wrong VendorID\n", __func__);
return -ENODEV;
}
tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID);
debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
/*
* We'd like to validate the Device ID too, but pretty much any
@ -80,34 +80,34 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
*/
/* I/O should already be enabled (it's a RO bit). */
tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND);
if (!(tmpword & PCI_COMMAND_IO)) {
debug("%s: device IO not enabled\n", __func__);
return -ENODEV;
}
/* Header Type must be normal (bits 6-0 only; see spec.) */
tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE);
if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
debug("%s: invalid Header type\n", __func__);
return -ENODEV;
}
/* Base Class must be a bridge device */
tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE);
if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
debug("%s: invalid class\n", __func__);
return -ENODEV;
}
/* Sub Class must be ISA */
tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
debug("%s: invalid subclass\n", __func__);
return -ENODEV;
}
/* Programming Interface must be 0x00 (no others exist) */
tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG);
if (tmpbyte != 0x00) {
debug("%s: invalid interface type\n", __func__);
return -ENODEV;
@ -123,7 +123,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
* while on the Ivybridge the bit0 is used to indicate it is an
* I/O space.
*/
tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
tmplong = x86_pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
debug("%s: unexpected GPIOBASE value\n", __func__);
return -ENODEV;

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