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@ -36,7 +36,24 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: |
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-------------------------------------- |
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12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de> |
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12/15/2003 Initial port to u-boot by |
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Sascha Hauer <saschahauer@web.de> |
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06/03/2008 Remy Bohmer <linux@bohmer.net> |
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- Fixed the driver to work with DM9000A. |
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(check on ISR receive status bit before reading the |
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FIFO as described in DM9000 programming guide and |
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application notes) |
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- Added autodetect of databus width. |
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- Made debug code compile again. |
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- Adapt eth_send such that it matches the DM9000* |
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application notes. Needed to make it work properly |
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for DM9000A. |
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- Adapted reset procedure to match DM9000 application |
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notes (i.e. double reset) |
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- some minor code cleanups |
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These changes are tested with DM9000{A,EP,E} together |
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with a 200MHz Atmel AT91SAM92161 core |
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TODO: Homerun NIC and longrun NIC are not functional, only internal at the |
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moment. |
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@ -47,8 +64,6 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the |
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#include <net.h> |
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#include <asm/io.h> |
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#ifdef CONFIG_DRIVER_DM9000 |
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#include "dm9000x.h" |
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/* Board/System/Debug information/definition ---------------- */ |
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@ -60,9 +75,21 @@ TODO: Homerun NIC and longrun NIC are not functional, only internal at the |
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#ifdef CONFIG_DM9000_DEBUG |
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#define DM9000_DBG(fmt,args...) printf(fmt, ##args) |
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#else /* */ |
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#define DM9000_DMP_PACKET(func,packet,length) \ |
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do { \
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int i; \
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printf(func ": length: %d\n", length); \
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for (i = 0; i < length; i++) { \
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if (i % 8 == 0) \
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printf("\n%s: %02x: ", func, i); \
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printf("%02x ", ((unsigned char *) packet)[i]); \
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} printf("\n"); \
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} while(0) |
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#else |
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#define DM9000_DBG(fmt,args...) |
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#endif /* */ |
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#define DM9000_DMP_PACKET(func,packet,length) |
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#endif |
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enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = |
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1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = |
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8, DM9000_1M_HPNA = 0x10 |
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@ -84,8 +111,11 @@ typedef struct board_info { |
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u8 device_wait_reset; /* device state */ |
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u8 nic_type; /* NIC type */ |
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unsigned char srom[128]; |
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void (*outblk)(volatile void *data_ptr, int count); |
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void (*inblk)(void *data_ptr, int count); |
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void (*rx_status)(u16 *RxStatus, u16 *RxLen); |
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} board_info_t; |
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board_info_t dmfe_info; |
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static board_info_t dm9000_info; |
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/* For module input parameter */ |
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static int media_mode = DM9000_AUTO; |
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@ -124,10 +154,85 @@ dump_regs(void) |
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DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); |
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DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); |
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DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); |
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DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); |
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DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR)); |
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DM9000_DBG("\n"); |
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} |
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#endif /* */ |
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#endif |
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static void dm9000_outblk_8bit(volatile void *data_ptr, int count) |
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{ |
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int i; |
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for (i = 0; i < count; i++) |
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DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); |
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} |
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static void dm9000_outblk_16bit(volatile void *data_ptr, int count) |
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{ |
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int i; |
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u32 tmplen = (count + 1) / 2; |
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for (i = 0; i < tmplen; i++) |
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DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); |
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} |
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static void dm9000_outblk_32bit(volatile void *data_ptr, int count) |
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{ |
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int i; |
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u32 tmplen = (count + 3) / 4; |
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for (i = 0; i < tmplen; i++) |
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DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); |
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} |
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static void dm9000_inblk_8bit(void *data_ptr, int count) |
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{ |
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int i; |
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for (i = 0; i < count; i++) |
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((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA); |
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} |
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static void dm9000_inblk_16bit(void *data_ptr, int count) |
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{ |
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int i; |
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u32 tmplen = (count + 1) / 2; |
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for (i = 0; i < tmplen; i++) |
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((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA); |
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} |
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static void dm9000_inblk_32bit(void *data_ptr, int count) |
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{ |
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int i; |
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u32 tmplen = (count + 3) / 4; |
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for (i = 0; i < tmplen; i++) |
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((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA); |
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} |
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static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen) |
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{ |
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u32 tmpdata; |
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DM9000_outb(DM9000_MRCMD, DM9000_IO); |
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tmpdata = DM9000_inl(DM9000_DATA); |
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*RxStatus = tmpdata; |
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*RxLen = tmpdata >> 16; |
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} |
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static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen) |
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{ |
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DM9000_outb(DM9000_MRCMD, DM9000_IO); |
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*RxStatus = DM9000_inw(DM9000_DATA); |
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*RxLen = DM9000_inw(DM9000_DATA); |
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} |
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static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen) |
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{ |
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DM9000_outb(DM9000_MRCMD, DM9000_IO); |
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*RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); |
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*RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); |
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} |
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/*
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Search DM9000 board, allocate space and register it |
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@ -236,7 +341,7 @@ program_dm9802(void) |
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static void |
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identify_nic(void) |
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{ |
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struct board_info *db = &dmfe_info; /* Point a board information structure */ |
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struct board_info *db = &dm9000_info; |
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u16 phy_reg3; |
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DM9000_iow(DM9000_NCR, NCR_EXT_PHY); |
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phy_reg3 = phy_read(3); |
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@ -263,9 +368,35 @@ identify_nic(void) |
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static void |
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dm9000_reset(void) |
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{ |
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DM9000_DBG("resetting\n"); |
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DM9000_iow(DM9000_NCR, NCR_RST); |
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udelay(1000); /* delay 1ms */ |
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DM9000_DBG("resetting DM9000\n"); |
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/* Reset DM9000,
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see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ |
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/* DEBUG: Make all GPIO pins outputs */ |
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DM9000_iow(DM9000_GPCR, 0x0F); |
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/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ |
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DM9000_iow(DM9000_GPR, 0); |
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/* Step 2: Software reset */ |
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DM9000_iow(DM9000_NCR, 3); |
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do { |
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DM9000_DBG("resetting the DM9000, 1st reset\n"); |
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udelay(25); /* Wait at least 20 us */ |
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} while (DM9000_ior(DM9000_NCR) & 1); |
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DM9000_iow(DM9000_NCR, 0); |
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DM9000_iow(DM9000_NCR, 3); /* Issue a second reset */ |
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do { |
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DM9000_DBG("resetting the DM9000, 2nd reset\n"); |
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udelay(25); /* Wait at least 20 us */ |
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} while (DM9000_ior(DM9000_NCR) & 1); |
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/* Check whether the ethernet controller is present */ |
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if ((DM9000_ior(DM9000_PIDL) != 0x0) || |
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(DM9000_ior(DM9000_PIDH) != 0x90)) |
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printf("ERROR: resetting DM9000 -> not responding\n"); |
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} |
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/* Initilize dm9000 board
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@ -274,12 +405,46 @@ int |
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eth_init(bd_t * bd) |
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{ |
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int i, oft, lnk; |
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u8 io_mode; |
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struct board_info *db = &dm9000_info; |
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DM9000_DBG("eth_init()\n"); |
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/* RESET device */ |
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dm9000_reset(); |
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dm9000_probe(); |
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/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ |
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io_mode = DM9000_ior(DM9000_ISR) >> 6; |
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switch (io_mode) { |
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case 0x0: /* 16-bit mode */ |
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printf("DM9000: running in 16 bit mode\n"); |
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db->outblk = dm9000_outblk_16bit; |
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db->inblk = dm9000_inblk_16bit; |
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db->rx_status = dm9000_rx_status_16bit; |
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break; |
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case 0x01: /* 32-bit mode */ |
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printf("DM9000: running in 32 bit mode\n"); |
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db->outblk = dm9000_outblk_32bit; |
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db->inblk = dm9000_inblk_32bit; |
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db->rx_status = dm9000_rx_status_32bit; |
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break; |
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case 0x02: /* 8 bit mode */ |
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printf("DM9000: running in 8 bit mode\n"); |
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db->outblk = dm9000_outblk_8bit; |
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db->inblk = dm9000_inblk_8bit; |
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db->rx_status = dm9000_rx_status_8bit; |
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break; |
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default: |
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/* Assume 8 bit mode, will probably not work anyway */ |
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printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); |
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db->outblk = dm9000_outblk_8bit; |
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db->inblk = dm9000_inblk_8bit; |
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db->rx_status = dm9000_rx_status_8bit; |
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break; |
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} |
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/* NIC Type: FASTETHER, HOMERUN, LONGRUN */ |
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identify_nic(); |
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@ -289,15 +454,22 @@ eth_init(bd_t * bd) |
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/* Set PHY */ |
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set_PHY_mode(); |
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/* Program operating register */ |
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DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ |
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DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ |
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DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ |
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DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ |
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DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ |
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DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ |
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DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ |
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DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ |
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/* Program operating register, only intern phy supported by now */ |
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DM9000_iow(DM9000_NCR, 0x0); |
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/* TX Polling clear */ |
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DM9000_iow(DM9000_TCR, 0); |
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/* Less 3Kb, 200us */ |
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DM9000_iow(DM9000_BPTR, 0x3f); |
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/* Flow Control : High/Low Water */ |
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DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); |
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/* SH FIXME: This looks strange! Flow Control */ |
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DM9000_iow(DM9000_FCR, 0x0); |
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/* Special Mode */ |
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DM9000_iow(DM9000_SMCR, 0); |
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/* clear TX status */ |
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DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); |
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/* Clear interrupt status */ |
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DM9000_iow(DM9000_ISR, 0x0f); |
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/* Set Node address */ |
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#ifndef CONFIG_AT91SAM9261EK |
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@ -333,8 +505,11 @@ eth_init(bd_t * bd) |
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DM9000_DBG("\n"); |
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/* Activate DM9000 */ |
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DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ |
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DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ |
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/* RX enable */ |
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DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); |
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/* Enable TX/RX interrupt mask */ |
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DM9000_iow(DM9000_IMR, IMR_PAR); |
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i = 0; |
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while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ |
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udelay(1000); |
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@ -376,38 +551,18 @@ eth_init(bd_t * bd) |
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int |
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eth_send(volatile void *packet, int length) |
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{ |
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char *data_ptr; |
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u32 tmplen, i; |
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int tmo; |
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DM9000_DBG("eth_send: length: %d\n", length); |
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for (i = 0; i < length; i++) { |
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if (i % 8 == 0) |
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DM9000_DBG("\nSend: 02x: ", i); |
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DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); |
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} DM9000_DBG("\n"); |
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struct board_info *db = &dm9000_info; |
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/* Move data to DM9000 TX RAM */ |
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data_ptr = (char *) packet; |
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DM9000_outb(DM9000_MWCMD, DM9000_IO); |
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DM9000_DMP_PACKET("eth_send", packet, length); |
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#ifdef CONFIG_DM9000_USE_8BIT |
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/* Byte mode */ |
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for (i = 0; i < length; i++) |
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DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); |
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DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ |
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#endif /* */ |
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#ifdef CONFIG_DM9000_USE_16BIT |
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tmplen = (length + 1) / 2; |
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for (i = 0; i < tmplen; i++) |
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DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); |
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#endif /* */ |
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#ifdef CONFIG_DM9000_USE_32BIT |
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tmplen = (length + 3) / 4; |
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for (i = 0; i < tmplen; i++) |
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DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); |
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/* Move data to DM9000 TX RAM */ |
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DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ |
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#endif /* */ |
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/* push the data to the TX-fifo */ |
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(db->outblk)(packet, length); |
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/* Set TX length to DM9000 */ |
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DM9000_iow(DM9000_TXPLL, length & 0xff); |
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@ -418,12 +573,15 @@ eth_send(volatile void *packet, int length) |
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/* wait for end of transmission */ |
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tmo = get_timer(0) + 5 * CFG_HZ; |
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while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { |
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while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || |
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!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { |
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if (get_timer(0) >= tmo) { |
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printf("transmission timeout\n"); |
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break; |
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} |
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} |
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DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ |
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DM9000_DBG("transmit done\n\n"); |
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return 0; |
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} |
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@ -452,65 +610,46 @@ eth_rx(void) |
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{ |
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u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; |
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u16 RxStatus, RxLen = 0; |
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u32 tmplen, i; |
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#ifdef CONFIG_DM9000_USE_32BIT |
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u32 tmpdata; |
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#endif |
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struct board_info *db = &dm9000_info; |
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/* Check packet ready or not */ |
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DM9000_ior(DM9000_MRCMDX); /* Dummy read */ |
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rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ |
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if (rxbyte == 0) |
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/* Check packet ready or not, we must check
|
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the ISR status first for DM9000A */ |
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if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ |
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return 0; |
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DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ |
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/* There is _at least_ 1 package in the fifo, read them all */ |
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for (;;) { |
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DM9000_ior(DM9000_MRCMDX); /* Dummy read */ |
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/* Get most updated data,
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only look at bits 0:1, See application notes DM9000 */ |
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rxbyte = DM9000_inb(DM9000_DATA) & 0x03; |
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|
/* Status check: this byte must be 0 or 1 */ |
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|
if (rxbyte > 1) { |
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|
if (rxbyte > DM9000_PKT_RDY) { |
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DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ |
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DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ |
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|
DM9000_DBG("rx status check: %d\n", rxbyte); |
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|
|
printf("DM9000 error: status check fail: 0x%x\n", |
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|
|
rxbyte); |
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|
return 0; |
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|
} |
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|
DM9000_DBG("receiving packet\n"); |
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|
/* A packet ready now & Get status/length */ |
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|
DM9000_outb(DM9000_MRCMD, DM9000_IO); |
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|
|
#ifdef CONFIG_DM9000_USE_8BIT |
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|
RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); |
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|
RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); |
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|
|
if (rxbyte != DM9000_PKT_RDY) |
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|
|
return 0; /* No packet received, ignore */ |
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|
|
#endif /* */ |
|
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|
|
#ifdef CONFIG_DM9000_USE_16BIT |
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|
|
RxStatus = DM9000_inw(DM9000_DATA); |
|
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|
|
RxLen = DM9000_inw(DM9000_DATA); |
|
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|
|
DM9000_DBG("receiving packet\n"); |
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|
|
#endif /* */ |
|
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|
|
#ifdef CONFIG_DM9000_USE_32BIT |
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|
|
tmpdata = DM9000_inl(DM9000_DATA); |
|
|
|
|
RxStatus = tmpdata; |
|
|
|
|
RxLen = tmpdata >> 16; |
|
|
|
|
/* A packet ready now & Get status/length */ |
|
|
|
|
(db->rx_status)(&RxStatus, &RxLen); |
|
|
|
|
|
|
|
|
|
#endif /* */ |
|
|
|
|
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); |
|
|
|
|
|
|
|
|
|
/* Move data from DM9000 */ |
|
|
|
|
/* Read received packet from RX SRAM */ |
|
|
|
|
#ifdef CONFIG_DM9000_USE_8BIT |
|
|
|
|
for (i = 0; i < RxLen; i++) |
|
|
|
|
rdptr[i] = DM9000_inb(DM9000_DATA); |
|
|
|
|
(db->inblk)(rdptr, RxLen); |
|
|
|
|
|
|
|
|
|
#endif /* */ |
|
|
|
|
#ifdef CONFIG_DM9000_USE_16BIT |
|
|
|
|
tmplen = (RxLen + 1) / 2; |
|
|
|
|
for (i = 0; i < tmplen; i++) |
|
|
|
|
((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); |
|
|
|
|
|
|
|
|
|
#endif /* */ |
|
|
|
|
#ifdef CONFIG_DM9000_USE_32BIT |
|
|
|
|
tmplen = (RxLen + 3) / 4; |
|
|
|
|
for (i = 0; i < tmplen; i++) |
|
|
|
|
((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); |
|
|
|
|
|
|
|
|
|
#endif /* */ |
|
|
|
|
if ((RxStatus & 0xbf00) || (RxLen < 0x40) |
|
|
|
|
|| (RxLen > DM9000_PKT_MAX)) { |
|
|
|
|
if (RxStatus & 0x100) { |
|
|
|
|
@ -527,11 +666,11 @@ eth_rx(void) |
|
|
|
|
dm9000_reset(); |
|
|
|
|
} |
|
|
|
|
} else { |
|
|
|
|
DM9000_DMP_PACKET("eth_rx", rdptr, RxLen); |
|
|
|
|
|
|
|
|
|
/* Pass to upper layer */ |
|
|
|
|
DM9000_DBG("passing packet to upper layer\n"); |
|
|
|
|
NetReceive(NetRxPackets[0], RxLen); |
|
|
|
|
return RxLen; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
@ -597,7 +736,7 @@ phy_read(int reg) |
|
|
|
|
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); |
|
|
|
|
|
|
|
|
|
/* The read data keeps on REG_0D & REG_0E */ |
|
|
|
|
DM9000_DBG("phy_read(%d): %d\n", reg, val); |
|
|
|
|
DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val); |
|
|
|
|
return val; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
@ -617,6 +756,5 @@ phy_write(int reg, u16 value) |
|
|
|
|
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ |
|
|
|
|
udelay(500); /* Wait write complete */ |
|
|
|
|
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
|
|
|
|
DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); |
|
|
|
|
DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); |
|
|
|
|
} |
|
|
|
|
#endif /* CONFIG_DRIVER_DM9000 */ |
|
|
|
|
|
Wolfgang Denk
17 years ago