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@ -120,13 +120,14 @@ CCR_D_DISABLE: .long 0x0808 |
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FRQCR_A: .long FRQCR |
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FRQCR_D: |
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#ifdef CONFIG_CPU_TYPE_R |
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.long 0x00000e1a /* 12:3:3 */ |
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.word 0x0e1a /* 12:3:3 */ |
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#else /* CONFIG_CPU_TYPE_R */ |
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#ifdef CONFIG_GOOD_SESH4 |
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.long 0x00000e13 /* 6:2:1 */ |
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.word 0x00e13 /* 6:2:1 */ |
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#else |
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.long 0x00000e23 /* 6:1:1 */ |
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.word 0x00e23 /* 6:1:1 */ |
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#endif |
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.align 2
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#endif /* CONFIG_CPU_TYPE_R */ |
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BCR1_A: .long BCR1 |
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@ -140,15 +141,19 @@ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ |
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WCR3_A: .long WCR3 |
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ |
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RTCSR_A: .long RTCSR |
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RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ |
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RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ |
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.align 2
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RTCNT_A: .long RTCNT |
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RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ |
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RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ |
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.align 2
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RTCOR_A: .long RTCOR |
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RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ |
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RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ |
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.align 2
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SDMR3_A: .long SDMR3_ADDRESS |
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SDMR3_D: .long 0x00 |
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MCR_A: .long MCR |
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MCR_D1: .long MCR_D1_VALUE |
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MCR_D2: .long MCR_D2_VALUE |
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RFCR_A: .long RFCR |
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RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ |
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RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ |
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.align 2
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